PeiSiliconPolicyUpdateLib.c 24 KB

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  1. /** @file
  2. Provides silicon policy update library functions.
  3. Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiPei.h>
  7. #include <ConfigBlock.h>
  8. #include <SaPolicyCommon.h>
  9. #include <CpuPolicyCommon.h>
  10. #include <PchPreMemPolicyCommon.h>
  11. #include <Pi/PiFirmwareFile.h>
  12. #include <Register/Cpuid.h>
  13. #include <PchHsioPtssTables.h>
  14. #include <Library/PchInfoLib.h>
  15. #include <Library/SiliconPolicyUpdateLib.h>
  16. #include <Library/PcdLib.h>
  17. #include <Library/DebugLib.h>
  18. #include <Library/ConfigBlockLib.h>
  19. #include <Library/PeiLib.h>
  20. #include <Library/PeiServicesLib.h>
  21. #include <Library/BaseMemoryLib.h>
  22. #include <Library/MemoryAllocationLib.h>
  23. #include <Library/CpuPlatformLib.h>
  24. #include <Library/PchHsioLib.h>
  25. #include <Library/PchPcieRpLib.h>
  26. #include <Library/MmPciLib.h>
  27. #include <Library/IoLib.h>
  28. /**
  29. Get the next microcode patch pointer.
  30. @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found,
  31. and output points to the next patch address found.
  32. @retval EFI_SUCCESS - Patch found.
  33. @retval EFI_NOT_FOUND - Patch not found.
  34. **/
  35. EFI_STATUS
  36. EFIAPI
  37. RetrieveMicrocode (
  38. IN OUT CPU_MICROCODE_HEADER **MicrocodeData
  39. )
  40. {
  41. UINTN MicrocodeStart;
  42. UINTN MicrocodeEnd;
  43. UINTN TotalSize;
  44. if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) {
  45. return EFI_NOT_FOUND;
  46. }
  47. ///
  48. /// Microcode binary in SEC
  49. ///
  50. MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
  51. ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength +
  52. sizeof (EFI_FFS_FILE_HEADER);
  53. MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize);
  54. if (*MicrocodeData == NULL) {
  55. *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;
  56. } else {
  57. if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) {
  58. DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n"));
  59. return EFI_NOT_FOUND;
  60. }
  61. TotalSize = (UINTN) ((*MicrocodeData)->TotalSize);
  62. if (TotalSize == 0) {
  63. TotalSize = 2048;
  64. }
  65. *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize);
  66. if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) {
  67. DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n"));
  68. return EFI_NOT_FOUND;
  69. }
  70. }
  71. return EFI_SUCCESS;
  72. }
  73. /**
  74. Get the microcode patch pointer.
  75. @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found.
  76. **/
  77. EFI_PHYSICAL_ADDRESS
  78. PlatformCpuLocateMicrocodePatch (
  79. VOID
  80. )
  81. {
  82. EFI_STATUS Status;
  83. CPU_MICROCODE_HEADER *MicrocodeData;
  84. EFI_CPUID_REGISTER Cpuid;
  85. UINT32 UcodeRevision;
  86. UINTN MicrocodeBufferSize;
  87. VOID *MicrocodeBuffer = NULL;
  88. AsmCpuid (
  89. CPUID_VERSION_INFO,
  90. &Cpuid.RegEax,
  91. &Cpuid.RegEbx,
  92. &Cpuid.RegEcx,
  93. &Cpuid.RegEdx
  94. );
  95. UcodeRevision = GetCpuUcodeRevision ();
  96. MicrocodeData = NULL;
  97. while (TRUE) {
  98. ///
  99. /// Find the next patch address
  100. ///
  101. Status = RetrieveMicrocode (&MicrocodeData);
  102. DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData));
  103. if (Status != EFI_SUCCESS) {
  104. break;
  105. } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) {
  106. break;
  107. }
  108. }
  109. if (EFI_ERROR (Status)) {
  110. return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
  111. }
  112. ///
  113. /// Check that microcode patch size is <= 128K max size,
  114. /// then copy the patch from FV to temp buffer for faster access.
  115. ///
  116. MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize;
  117. if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) {
  118. MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize));
  119. if (MicrocodeBuffer != NULL) {
  120. DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));
  121. CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);
  122. return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;
  123. } else {
  124. DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
  125. }
  126. } else {
  127. DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n"));
  128. }
  129. return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
  130. }
  131. /**
  132. Update HSIO policy per board.
  133. @param[in] Policy - Policy PPI pointer (caller should ensure it is valid pointer)
  134. **/
  135. VOID
  136. InstallPlatformHsioPtssTable (
  137. IN VOID *Policy
  138. )
  139. {
  140. HSIO_PTSS_TABLES *UnknowPtssTables;
  141. HSIO_PTSS_TABLES *SpecificPtssTables;
  142. HSIO_PTSS_TABLES *PtssTables;
  143. UINT8 PtssTableIndex;
  144. UINT32 UnknowTableSize;
  145. UINT32 SpecificTableSize;
  146. UINT32 TableSize;
  147. UINT32 Entry;
  148. UINT8 LaneNum;
  149. UINT8 Index;
  150. UINT8 MaxSataPorts;
  151. UINT8 MaxPciePorts;
  152. UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
  153. UINT8 PciePort;
  154. UINTN RpBase;
  155. UINTN RpDevice;
  156. UINTN RpFunction;
  157. UINT32 StrapFuseCfg;
  158. UINT8 PcieControllerCfg;
  159. PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
  160. PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
  161. EFI_STATUS Status;
  162. Status = GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
  163. ASSERT_EFI_ERROR (Status);
  164. Status = GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
  165. ASSERT_EFI_ERROR (Status);
  166. UnknowPtssTables = NULL;
  167. UnknowTableSize = 0;
  168. SpecificPtssTables = NULL;
  169. SpecificTableSize = 0;
  170. if (GetPchGeneration () == SklPch) {
  171. switch (PchStepping ()) {
  172. case PchLpB0:
  173. case PchLpB1:
  174. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
  175. UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
  176. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
  177. SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
  178. break;
  179. case PchLpC0:
  180. case PchLpC1:
  181. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
  182. UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
  183. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
  184. SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
  185. break;
  186. case PchHB0:
  187. case PchHC0:
  188. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
  189. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
  190. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
  191. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
  192. break;
  193. case PchHD0:
  194. case PchHD1:
  195. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
  196. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
  197. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
  198. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
  199. break;
  200. default:
  201. UnknowPtssTables = NULL;
  202. UnknowTableSize = 0;
  203. SpecificPtssTables = NULL;
  204. SpecificTableSize = 0;
  205. DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
  206. }
  207. } else {
  208. switch (PchStepping ()) {
  209. case KblPchHA0:
  210. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
  211. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
  212. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
  213. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
  214. break;
  215. default:
  216. UnknowPtssTables = NULL;
  217. UnknowTableSize = 0;
  218. SpecificPtssTables = NULL;
  219. SpecificTableSize = 0;
  220. DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
  221. }
  222. }
  223. PtssTableIndex = 0;
  224. MaxSataPorts = GetPchMaxSataPortNum ();
  225. MaxPciePorts = GetPchMaxPciePortNum ();
  226. ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
  227. //
  228. //Populate PCIe topology based on lane configuration
  229. //
  230. for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
  231. Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
  232. ASSERT_EFI_ERROR (Status);
  233. RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
  234. StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
  235. PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
  236. DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
  237. }
  238. for (Index = 0; Index < MaxPciePorts; Index++) {
  239. DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
  240. }
  241. //
  242. //Case 1: BoardId is known, Topology is known/unknown
  243. //Case 1a: SATA
  244. //
  245. PtssTables = SpecificPtssTables;
  246. TableSize = SpecificTableSize;
  247. for (Index = 0; Index < MaxSataPorts; Index++) {
  248. if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  249. for (Entry = 0; Entry < TableSize; Entry++) {
  250. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  251. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
  252. )
  253. {
  254. PtssTableIndex++;
  255. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
  256. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
  257. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
  258. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
  259. } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
  260. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
  261. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
  262. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
  263. }
  264. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
  265. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
  266. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
  267. }
  268. } else {
  269. ASSERT (FALSE);
  270. }
  271. }
  272. }
  273. }
  274. }
  275. //
  276. //Case 1b: PCIe
  277. //
  278. for (Index = 0; Index < MaxPciePorts; Index++) {
  279. if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  280. for (Entry = 0; Entry < TableSize; Entry++) {
  281. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  282. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
  283. (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
  284. PtssTableIndex++;
  285. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
  286. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
  287. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE;
  288. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
  289. } else {
  290. ASSERT (FALSE);
  291. }
  292. }
  293. }
  294. }
  295. }
  296. //
  297. //Case 2: BoardId is unknown, Topology is known/unknown
  298. //
  299. if (PtssTableIndex == 0) {
  300. DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
  301. PtssTables = UnknowPtssTables;
  302. TableSize = UnknowTableSize;
  303. for (Index = 0; Index < MaxSataPorts; Index++) {
  304. if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  305. for (Entry = 0; Entry < TableSize; Entry++) {
  306. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  307. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
  308. )
  309. {
  310. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
  311. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
  312. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
  313. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
  314. } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
  315. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
  316. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
  317. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
  318. }
  319. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
  320. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
  321. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
  322. }
  323. } else {
  324. ASSERT (FALSE);
  325. }
  326. }
  327. }
  328. }
  329. }
  330. for (Index = 0; Index < MaxPciePorts; Index++) {
  331. if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  332. for (Entry = 0; Entry < TableSize; Entry++) {
  333. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  334. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
  335. (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
  336. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
  337. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
  338. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE;
  339. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
  340. } else {
  341. ASSERT (FALSE);
  342. }
  343. }
  344. }
  345. }
  346. }
  347. }
  348. }
  349. /**
  350. Update PreMem phase silicon policy per board.
  351. @param[in] Policy - Policy PPI pointer.
  352. @retval Policy - Policy PPI pointer.
  353. **/
  354. VOID *
  355. EFIAPI
  356. SiliconPolicyUpdatePreMem (
  357. IN VOID *Policy
  358. )
  359. {
  360. EFI_STATUS Status;
  361. SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
  362. MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
  363. VOID *Buffer;
  364. UINTN FspNvsBufferSize;
  365. VOID *FspNvsBufferPtr;
  366. UINT8 SpdAddressTable[4];
  367. DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n"));
  368. if (Policy != NULL) {
  369. SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
  370. SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
  371. SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
  372. SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
  373. MiscPeiPreMemConfig = NULL;
  374. Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
  375. ASSERT_EFI_ERROR (Status);
  376. if (MiscPeiPreMemConfig != NULL) {
  377. //
  378. // Pass board specific SpdAddressTable to policy
  379. //
  380. CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4));
  381. //
  382. // Set size of SMRAM
  383. //
  384. MiscPeiPreMemConfig->TsegSize = PcdGet32 (PcdTsegSize);
  385. //
  386. // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
  387. // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI added in FSP 2.1, hence
  388. // the platform specific S3DataPtr must be used instead.
  389. //
  390. FspNvsBufferPtr = NULL;
  391. FspNvsBufferSize = 0;
  392. Status = PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableGuid, &FspNvsBufferPtr, &FspNvsBufferSize);
  393. if (Status == EFI_SUCCESS) {
  394. DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid - %r\n", Status));
  395. DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize));
  396. MiscPeiPreMemConfig->S3DataPtr = FspNvsBufferPtr;
  397. }
  398. //
  399. // In FSP Dispatch Mode these BAR values are initialized by SiliconPolicyInitPreMem() in
  400. // KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c; this function calls
  401. // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to initialize all Config Blocks
  402. // with default policy values (including these BAR values.) PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  403. // is implemented in the FSP. Make sure the value that FSP is using matches the value we are using.
  404. //
  405. ASSERT (PcdGet64 (PcdMchBaseAddress) <= 0xFFFFFFFF);
  406. ASSERT (MiscPeiPreMemConfig->MchBar == (UINT32) PcdGet64 (PcdMchBaseAddress));
  407. ASSERT (MiscPeiPreMemConfig->SmbusBar == PcdGet16 (PcdSmbusBaseAddress));
  408. }
  409. MemConfigNoCrc = NULL;
  410. Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
  411. ASSERT_EFI_ERROR (Status);
  412. if (MemConfigNoCrc != NULL) {
  413. MemConfigNoCrc->PlatformMemorySize = PcdGet32 (PcdPeiMinMemorySize);
  414. //
  415. // Only if SpdAddressTables are all zero we need to pass hard-coded SPD data buffer.
  416. // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTables policy.
  417. //
  418. if (*((UINT32 *) (UINTN) SpdAddressTable) == 0) {
  419. DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n"));
  420. CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
  421. CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
  422. }
  423. DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
  424. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
  425. if (Buffer) {
  426. CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer, 12);
  427. CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*) Buffer + 12, 12);
  428. }
  429. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
  430. if (Buffer) {
  431. CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffer, 8);
  432. CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8);
  433. }
  434. DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
  435. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
  436. if (Buffer) {
  437. CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), Buffer, 6);
  438. }
  439. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
  440. if (Buffer) {
  441. CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Buffer, 10);
  442. }
  443. }
  444. //
  445. // Update PCD policy
  446. //
  447. InstallPlatformHsioPtssTable (Policy);
  448. }
  449. return Policy;
  450. }
  451. /**
  452. Update PostMem phase silicon policy per board.
  453. @param[in] Policy - Policy PPI pointer.
  454. @retval Policy - Policy PPI pointer.
  455. **/
  456. VOID *
  457. EFIAPI
  458. SiliconPolicyUpdatePostMem (
  459. IN VOID *Policy
  460. )
  461. {
  462. EFI_STATUS Status;
  463. EFI_BOOT_MODE BootMode;
  464. VOID *Buffer;
  465. VOID *MemBuffer;
  466. UINT32 Size;
  467. GRAPHICS_PEI_CONFIG *GtConfig;
  468. CPU_CONFIG *CpuConfig;
  469. DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
  470. Status = PeiServicesGetBootMode (&BootMode);
  471. ASSERT_EFI_ERROR (Status);
  472. GtConfig = NULL;
  473. Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
  474. ASSERT_EFI_ERROR (Status);
  475. if (GtConfig != NULL) {
  476. //
  477. // Always enable PEI graphics initialization.
  478. //
  479. GtConfig->PeiGraphicsPeimInit = 1;
  480. Size = 0;
  481. Buffer = NULL;
  482. PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
  483. if (Buffer == NULL) {
  484. DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
  485. //
  486. // Graphics initialization is unnecessary,
  487. // OS has present framebuffer.
  488. //
  489. } else if (BootMode != BOOT_ON_S3_RESUME) {
  490. MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
  491. if ((MemBuffer != NULL) && (Buffer != NULL)) {
  492. CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
  493. GtConfig->GraphicsConfigPtr = MemBuffer;
  494. } else {
  495. DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
  496. GtConfig->GraphicsConfigPtr = 0;
  497. }
  498. }
  499. DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
  500. DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
  501. Size = 0;
  502. Buffer = NULL;
  503. PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
  504. if (Buffer == NULL) {
  505. DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
  506. } else {
  507. MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
  508. if ((MemBuffer != NULL) && (Buffer != NULL)) {
  509. CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
  510. GtConfig->LogoPtr = MemBuffer;
  511. GtConfig->LogoSize = Size;
  512. } else {
  513. DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
  514. GtConfig->LogoPtr = 0;
  515. GtConfig->LogoSize = 0;
  516. }
  517. }
  518. DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr));
  519. DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoSize));
  520. }
  521. CpuConfig = NULL;
  522. Status = GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID *)&CpuConfig);
  523. ASSERT_EFI_ERROR (Status);
  524. if (CpuConfig != NULL) {
  525. CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch ();
  526. }
  527. return Policy;
  528. }
  529. /**
  530. Update late phase silicon policy per board.
  531. @param[in] Policy - Policy PPI pointer.
  532. @retval Policy - Policy PPI pointer.
  533. **/
  534. VOID *
  535. EFIAPI
  536. SiliconPolicyUpdateLate (
  537. IN VOID *Policy
  538. )
  539. {
  540. return Policy;
  541. }