PeiKabylakeRvp3InitPreMemLib.c 9.9 KB

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  1. /** @file
  2. Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include <PiPei.h>
  6. #include <SaPolicyCommon.h>
  7. #include <Library/DebugLib.h>
  8. #include <Library/BaseMemoryLib.h>
  9. #include <Library/IoLib.h>
  10. #include <Library/HobLib.h>
  11. #include <Library/PcdLib.h>
  12. #include <Library/PchCycleDecodingLib.h>
  13. #include <Library/PchPmcLib.h>
  14. #include <Library/PciLib.h>
  15. #include <Library/PcdLib.h>
  16. #include <Library/BaseMemoryLib.h>
  17. #include <Library/PeiSaPolicyLib.h>
  18. #include <Library/BoardInitLib.h>
  19. #include <PchAccess.h>
  20. #include <Library/GpioNativeLib.h>
  21. #include <Library/GpioLib.h>
  22. #include <GpioPinsSklLp.h>
  23. #include <GpioPinsSklH.h>
  24. #include <Library/GpioExpanderLib.h>
  25. #include <SioRegs.h>
  26. #include <Library/PchPcrLib.h>
  27. #include <Library/SiliconInitLib.h>
  28. #include <Library/PchResetLib.h>
  29. #include "PeiKabylakeRvp3InitLib.h"
  30. #include <ConfigBlock.h>
  31. #include <ConfigBlock/MemoryConfig.h>
  32. //
  33. // Reference RCOMP resistors on motherboard - for SKL RVP1
  34. //
  35. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
  36. //
  37. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
  38. //
  39. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
  40. /**
  41. SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
  42. PEI_BOARD_CONFIG_PCD_INIT
  43. @param Content pointer to the buffer contain init information for board init.
  44. @retval EFI_SUCCESS The function completed successfully.
  45. @retval EFI_INVALID_PARAMETER The parameter is NULL.
  46. **/
  47. EFI_STATUS
  48. EFIAPI
  49. KabylakeRvp3InitPreMem (
  50. VOID
  51. )
  52. {
  53. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  54. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  55. PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
  56. PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
  57. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  58. PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
  59. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  60. //
  61. // HSIO PTSS Table
  62. //
  63. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
  64. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
  65. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
  66. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
  67. //
  68. // DRAM related definition
  69. //
  70. PcdSet8S (PcdSaMiscUserBd, 5);
  71. PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
  72. PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
  73. PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
  74. PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
  75. PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
  76. PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
  77. //
  78. // Example policy for DIMM slots implementation boards:
  79. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  80. // by reading from DIMM SPD.
  81. // 2. No need to apply hardcoded SpdData buffers here for such board.
  82. // Example:
  83. // PcdMrcSpdAddressTable0 = 0xA0
  84. // PcdMrcSpdAddressTable1 = 0xA2
  85. // PcdMrcSpdAddressTable2 = 0xA4
  86. // PcdMrcSpdAddressTable3 = 0xA6
  87. // PcdMrcSpdData = 0
  88. // PcdMrcSpdDataSize = 0
  89. //
  90. // Kabylake RVP3 has 8GB Memory down implementation withouit SPD,
  91. // So assign all SpdAddress to 0 and apply static SpdData buffers:
  92. // PcdMrcSpdAddressTable0 = 0
  93. // PcdMrcSpdAddressTable1 = 0
  94. // PcdMrcSpdAddressTable2 = 0
  95. // PcdMrcSpdAddressTable3 = 0
  96. // PcdMrcSpdData = static data buffer
  97. // PcdMrcSpdDataSize = sizeof (static data buffer)
  98. //
  99. PcdSet8S (PcdMrcSpdAddressTable0, 0);
  100. PcdSet8S (PcdMrcSpdAddressTable1, 0);
  101. PcdSet8S (PcdMrcSpdAddressTable2, 0);
  102. PcdSet8S (PcdMrcSpdAddressTable3, 0);
  103. PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);
  104. PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);
  105. PcdSetBoolS (PcdIoExpanderPresent, TRUE);
  106. return EFI_SUCCESS;
  107. }
  108. /**
  109. SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
  110. PEI_BOARD_CONFIG_PCD_INIT
  111. @param Content pointer to the buffer contain init information for board init.
  112. @retval EFI_SUCCESS The function completed successfully.
  113. @retval EFI_INVALID_PARAMETER The parameter is NULL.
  114. **/
  115. EFI_STATUS
  116. EFIAPI
  117. SkylakeRvp3InitPreMem (
  118. VOID
  119. )
  120. {
  121. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  122. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  123. PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
  124. PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
  125. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  126. PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
  127. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  128. //
  129. // HSIO PTSS Table
  130. //
  131. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
  132. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
  133. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
  134. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
  135. //
  136. // DRAM related definition
  137. //
  138. PcdSet8S (PcdSaMiscUserBd, 5);
  139. PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
  140. PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
  141. PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
  142. PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
  143. PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
  144. PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
  145. //
  146. // Example policy for DIMM slots implementation boards:
  147. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  148. // by reading from DIMM SPD.
  149. // 2. No need to apply hardcoded SpdData buffers here for such board.
  150. // Example:
  151. // PcdMrcSpdAddressTable0 = 0xA0
  152. // PcdMrcSpdAddressTable1 = 0xA2
  153. // PcdMrcSpdAddressTable2 = 0xA4
  154. // PcdMrcSpdAddressTable3 = 0xA6
  155. // PcdMrcSpdData = 0
  156. // PcdMrcSpdDataSize = 0
  157. //
  158. // Skylake RVP3 has 4GB Memory down implementation withouit SPD,
  159. // So assign all SpdAddress to 0 and apply static SpdData buffers:
  160. // PcdMrcSpdAddressTable0 = 0
  161. // PcdMrcSpdAddressTable1 = 0
  162. // PcdMrcSpdAddressTable2 = 0
  163. // PcdMrcSpdAddressTable3 = 0
  164. // PcdMrcSpdData = static data buffer
  165. // PcdMrcSpdDataSize = sizeof (static data buffer)
  166. //
  167. PcdSet8S (PcdMrcSpdAddressTable0, 0);
  168. PcdSet8S (PcdMrcSpdAddressTable1, 0);
  169. PcdSet8S (PcdMrcSpdAddressTable2, 0);
  170. PcdSet8S (PcdMrcSpdAddressTable3, 0);
  171. PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd);
  172. PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize);
  173. PcdSetBoolS (PcdIoExpanderPresent, TRUE);
  174. return EFI_SUCCESS;
  175. }
  176. #define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
  177. /**
  178. Configures GPIO.
  179. @param[in] GpioTable Point to Platform Gpio table
  180. @param[in] GpioTableCount Number of Gpio table entries
  181. **/
  182. VOID
  183. ConfigureGpio (
  184. IN GPIO_INIT_CONFIG *GpioDefinition,
  185. IN UINT16 GpioTableCount
  186. )
  187. {
  188. EFI_STATUS Status;
  189. DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
  190. Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
  191. DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
  192. }
  193. /**
  194. Configure GPIO Before Memory is not ready.
  195. **/
  196. VOID
  197. GpioInitPreMem (
  198. VOID
  199. )
  200. {
  201. // ConfigureGpio ();
  202. }
  203. /**
  204. Configure Super IO.
  205. **/
  206. VOID
  207. SioInit (
  208. VOID
  209. )
  210. {
  211. //
  212. // Program and Enable Default Super IO Configuration Port Addresses and range
  213. //
  214. PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
  215. //
  216. // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
  217. //
  218. PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
  219. return;
  220. }
  221. /**
  222. Configures the IC2 Controller on which GPIO Expander Communicates.
  223. This Function is to enable the I2CGPIOExapanderLib to program the Gpios
  224. Complete initialization will be done in later Stage
  225. **/
  226. VOID
  227. EFIAPI
  228. I2CGpioExpanderInitPreMem(
  229. VOID
  230. )
  231. {
  232. ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
  233. SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
  234. }
  235. /**
  236. Configure GPIO and SIO before memory ready.
  237. @retval EFI_SUCCESS Operation success.
  238. **/
  239. EFI_STATUS
  240. EFIAPI
  241. KabylakeRvp3BoardInitBeforeMemoryInit (
  242. VOID
  243. )
  244. {
  245. EFI_STATUS Status;
  246. if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
  247. KabylakeRvp3InitPreMem ();
  248. } else if (LibPcdGetSku () == BoardIdSkylakeRvp3) {
  249. SkylakeRvp3InitPreMem ();
  250. }
  251. //
  252. // Configures the I2CGpioExpander
  253. //
  254. if (PcdGetBool (PcdIoExpanderPresent)) {
  255. I2CGpioExpanderInitPreMem();
  256. }
  257. GpioInitPreMem ();
  258. SioInit ();
  259. ///
  260. /// Do basic PCH init
  261. ///
  262. SiliconInit ();
  263. //
  264. // Install PCH RESET PPI and EFI RESET2 PeiService
  265. //
  266. Status = PchInitializeReset ();
  267. ASSERT_EFI_ERROR (Status);
  268. return EFI_SUCCESS;
  269. }
  270. EFI_STATUS
  271. EFIAPI
  272. KabylakeRvp3BoardDebugInit (
  273. VOID
  274. )
  275. {
  276. return EFI_SUCCESS;
  277. }
  278. EFI_BOOT_MODE
  279. EFIAPI
  280. KabylakeRvp3BoardBootModeDetect (
  281. VOID
  282. )
  283. {
  284. EFI_BOOT_MODE BootMode;
  285. UINT32 SleepType;
  286. DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
  287. // Known sane defaults
  288. BootMode = BOOT_WITH_FULL_CONFIGURATION;
  289. if (GetSleepTypeAfterWakeup (&SleepType)) {
  290. switch (SleepType) {
  291. case V_PCH_ACPI_PM1_CNT_S3:
  292. BootMode = BOOT_ON_S3_RESUME;
  293. break;
  294. case V_PCH_ACPI_PM1_CNT_S4:
  295. BootMode = BOOT_ON_S4_RESUME;
  296. break;
  297. case V_PCH_ACPI_PM1_CNT_S5:
  298. BootMode = BOOT_ON_S5_RESUME;
  299. break;
  300. }
  301. }
  302. DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
  303. return BootMode;
  304. }