PeiGalagoPro3InitPreMemLib.c 6.3 KB

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  1. /** @file
  2. System 76 GalagoPro3 board pre-memory initialization.
  3. Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiPei.h>
  7. #include <SaPolicyCommon.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/BaseMemoryLib.h>
  10. #include <Library/IoLib.h>
  11. #include <Library/HobLib.h>
  12. #include <Library/PcdLib.h>
  13. #include <Library/PchCycleDecodingLib.h>
  14. #include <Library/PchPmcLib.h>
  15. #include <Library/PciLib.h>
  16. #include <Library/PcdLib.h>
  17. #include <Library/BaseMemoryLib.h>
  18. #include <Library/PeiSaPolicyLib.h>
  19. #include <Library/BoardInitLib.h>
  20. #include <PchAccess.h>
  21. #include <Library/GpioNativeLib.h>
  22. #include <Library/GpioLib.h>
  23. #include <GpioPinsSklLp.h>
  24. #include <GpioPinsSklH.h>
  25. #include <Library/GpioExpanderLib.h>
  26. #include <SioRegs.h>
  27. #include <Library/PchPcrLib.h>
  28. #include <Library/SiliconInitLib.h>
  29. #include <Library/PchResetLib.h>
  30. #include "PeiGalagoPro3InitLib.h"
  31. #include <ConfigBlock.h>
  32. #include <ConfigBlock/MemoryConfig.h>
  33. //
  34. // Reference RCOMP resistors on motherboard - for SKL RVP1
  35. //
  36. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
  37. //
  38. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
  39. //
  40. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
  41. //
  42. // Reference RCOMP resistors on motherboard - for SKL RVP2
  43. //
  44. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp2[SA_MRC_MAX_RCOMP] = { 121, 81, 100 };
  45. //
  46. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP2
  47. //
  48. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp2[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 20, 20, 26 };
  49. /**
  50. N 1XX WU board configuration init function for PEI pre-memory phase.
  51. PEI_BOARD_CONFIG_PCD_INIT
  52. @param Content pointer to the buffer contain init information for board init.
  53. @retval EFI_SUCCESS The function completed successfully.
  54. @retval EFI_INVALID_PARAMETER The parameter is NULL.
  55. **/
  56. EFI_STATUS
  57. EFIAPI
  58. GalagoPro3InitPreMem (
  59. VOID
  60. )
  61. {
  62. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  63. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  64. PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
  65. PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
  66. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  67. PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
  68. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  69. //
  70. // HSIO PTSS Table
  71. //
  72. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_GalagoPro3);
  73. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_GALAGO_PRO_3_Size);
  74. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_GalagoPro3);
  75. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_GALAGO_PRO_3_Size);
  76. //
  77. // DRAM related definition
  78. //
  79. PcdSet8S (PcdSaMiscUserBd, 5);
  80. PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
  81. PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
  82. PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
  83. PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);
  84. PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
  85. PcdSetBoolS(PcdMrcDqPinsInterleaved, TRUE);
  86. PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorSklRvp2);
  87. PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetSklRvp2);
  88. PcdSet8S(PcdMrcCaVrefConfig, 2); // DDR4 boards
  89. PcdSetBoolS (PcdIoExpanderPresent, TRUE);
  90. return EFI_SUCCESS;
  91. }
  92. #define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
  93. /**
  94. Configures GPIO
  95. @param[in] GpioTable Point to Platform Gpio table
  96. @param[in] GpioTableCount Number of Gpio table entries
  97. **/
  98. VOID
  99. ConfigureGpio (
  100. IN GPIO_INIT_CONFIG *GpioDefinition,
  101. IN UINT16 GpioTableCount
  102. )
  103. {
  104. EFI_STATUS Status;
  105. DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
  106. Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
  107. DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
  108. }
  109. /**
  110. Configure GPIO Before Memory is not ready.
  111. **/
  112. VOID
  113. GpioInitPreMem (
  114. VOID
  115. )
  116. {
  117. // ConfigureGpio ();
  118. }
  119. /**
  120. Configure Super IO
  121. **/
  122. VOID
  123. SioInit (
  124. VOID
  125. )
  126. {
  127. //
  128. // Program and Enable Default Super IO Configuration Port Addresses and range
  129. //
  130. PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
  131. //
  132. // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
  133. //
  134. PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
  135. return;
  136. }
  137. /**
  138. Configures the IC2 Controller on which GPIO Expander Communicates.
  139. This Function is to enable the I2CGPIOExapanderLib to program the Gpios
  140. Complete initialization will be done in later Stage
  141. **/
  142. VOID
  143. EFIAPI
  144. I2CGpioExpanderInitPreMem(
  145. VOID
  146. )
  147. {
  148. ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
  149. SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
  150. }
  151. /**
  152. Configure GPIO and SIO before memory ready
  153. @retval EFI_SUCCESS Operation success.
  154. **/
  155. EFI_STATUS
  156. EFIAPI
  157. GalagoPro3BoardInitBeforeMemoryInit (
  158. VOID
  159. )
  160. {
  161. EFI_STATUS Status;
  162. GalagoPro3InitPreMem ();
  163. //
  164. // Configures the I2CGpioExpander
  165. //
  166. if (PcdGetBool (PcdIoExpanderPresent)) {
  167. I2CGpioExpanderInitPreMem();
  168. }
  169. GpioInitPreMem ();
  170. SioInit ();
  171. ///
  172. /// Do basic PCH init
  173. ///
  174. SiliconInit ();
  175. //
  176. // Install PCH RESET PPI and EFI RESET2 PeiService
  177. //
  178. Status = PchInitializeReset ();
  179. ASSERT_EFI_ERROR (Status);
  180. return EFI_SUCCESS;
  181. }
  182. EFI_STATUS
  183. EFIAPI
  184. GalagoPro3BoardDebugInit (
  185. VOID
  186. )
  187. {
  188. return EFI_SUCCESS;
  189. }
  190. EFI_BOOT_MODE
  191. EFIAPI
  192. GalagoPro3BoardBootModeDetect (
  193. VOID
  194. )
  195. {
  196. EFI_BOOT_MODE BootMode;
  197. UINT32 SleepType;
  198. DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
  199. // Known sane defaults
  200. BootMode = BOOT_WITH_FULL_CONFIGURATION;
  201. if (GetSleepTypeAfterWakeup (&SleepType)) {
  202. switch (SleepType) {
  203. case V_PCH_ACPI_PM1_CNT_S3:
  204. BootMode = BOOT_ON_S3_RESUME;
  205. break;
  206. case V_PCH_ACPI_PM1_CNT_S4:
  207. BootMode = BOOT_ON_S4_RESUME;
  208. break;
  209. case V_PCH_ACPI_PM1_CNT_S5:
  210. BootMode = BOOT_ON_S5_RESUME;
  211. break;
  212. }
  213. }
  214. DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
  215. return BootMode;
  216. }