PeiSiliconPolicyUpdateLib.c 25 KB

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  1. /** @file
  2. Provides silicon policy update library functions.
  3. Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiPei.h>
  7. #include <ConfigBlock.h>
  8. #include <SaPolicyCommon.h>
  9. #include <CpuPolicyCommon.h>
  10. #include <PchPreMemPolicyCommon.h>
  11. #include <Pi/PiFirmwareFile.h>
  12. #include <Register/Cpuid.h>
  13. #include <PchHsioPtssTables.h>
  14. #include <Library/PchInfoLib.h>
  15. #include <Library/SiliconPolicyUpdateLib.h>
  16. #include <Library/PcdLib.h>
  17. #include <Library/DebugLib.h>
  18. #include <Library/ConfigBlockLib.h>
  19. #include <Library/PeiLib.h>
  20. #include <Library/PeiServicesLib.h>
  21. #include <Library/BaseMemoryLib.h>
  22. #include <Library/MemoryAllocationLib.h>
  23. #include <Library/CpuPlatformLib.h>
  24. #include <Library/PchHsioLib.h>
  25. #include <Library/PchPcieRpLib.h>
  26. #include <Library/MmPciLib.h>
  27. #include <Library/IoLib.h>
  28. //
  29. // Function prototypes
  30. //
  31. /**
  32. Performs the remainder of board-specific FSP Policy initialization.
  33. @param[in] Policy - Policy PPI pointer.
  34. @retval EFI_SUCCESS FSP UPD Data is updated.
  35. @retval EFI_NOT_FOUND Fail to locate required PPI.
  36. @retval Other FSP UPD Data update process fail.
  37. **/
  38. EFI_STATUS
  39. EFIAPI
  40. PeiFspBoardPolicyUpdatePreMem (
  41. IN VOID *Policy
  42. );
  43. /**
  44. Performs the remainder of board-specific FSP Policy initialization.
  45. @param[in] Policy - Policy PPI pointer.
  46. @retval EFI_SUCCESS FSP UPD Data is updated.
  47. @retval EFI_NOT_FOUND Fail to locate required PPI.
  48. @retval Other FSP UPD Data update process fail.
  49. **/
  50. EFI_STATUS
  51. EFIAPI
  52. PeiFspBoardPolicyUpdate (
  53. IN VOID *Policy
  54. );
  55. /**
  56. Get the next microcode patch pointer.
  57. @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found,
  58. and output points to the next patch address found.
  59. @retval EFI_SUCCESS - Patch found.
  60. @retval EFI_NOT_FOUND - Patch not found.
  61. **/
  62. EFI_STATUS
  63. EFIAPI
  64. RetrieveMicrocode (
  65. IN OUT CPU_MICROCODE_HEADER **MicrocodeData
  66. )
  67. {
  68. UINTN MicrocodeStart;
  69. UINTN MicrocodeEnd;
  70. UINTN TotalSize;
  71. if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) {
  72. return EFI_NOT_FOUND;
  73. }
  74. ///
  75. /// Microcode binary in SEC
  76. ///
  77. MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
  78. ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength +
  79. sizeof (EFI_FFS_FILE_HEADER);
  80. MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize);
  81. if (*MicrocodeData == NULL) {
  82. *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;
  83. } else {
  84. if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) {
  85. DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n"));
  86. return EFI_NOT_FOUND;
  87. }
  88. TotalSize = (UINTN) ((*MicrocodeData)->TotalSize);
  89. if (TotalSize == 0) {
  90. TotalSize = 2048;
  91. }
  92. *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize);
  93. if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) {
  94. DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n"));
  95. return EFI_NOT_FOUND;
  96. }
  97. }
  98. return EFI_SUCCESS;
  99. }
  100. /**
  101. Get the microcode patch pointer.
  102. @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found.
  103. **/
  104. EFI_PHYSICAL_ADDRESS
  105. PlatformCpuLocateMicrocodePatch (
  106. VOID
  107. )
  108. {
  109. EFI_STATUS Status;
  110. CPU_MICROCODE_HEADER *MicrocodeData;
  111. EFI_CPUID_REGISTER Cpuid;
  112. UINT32 UcodeRevision;
  113. UINTN MicrocodeBufferSize;
  114. VOID *MicrocodeBuffer = NULL;
  115. AsmCpuid (
  116. CPUID_VERSION_INFO,
  117. &Cpuid.RegEax,
  118. &Cpuid.RegEbx,
  119. &Cpuid.RegEcx,
  120. &Cpuid.RegEdx
  121. );
  122. UcodeRevision = GetCpuUcodeRevision ();
  123. MicrocodeData = NULL;
  124. while (TRUE) {
  125. ///
  126. /// Find the next patch address
  127. ///
  128. Status = RetrieveMicrocode (&MicrocodeData);
  129. DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData));
  130. if (Status != EFI_SUCCESS) {
  131. break;
  132. } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) {
  133. break;
  134. }
  135. }
  136. if (EFI_ERROR (Status)) {
  137. return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
  138. }
  139. ///
  140. /// Check that microcode patch size is <= 128K max size,
  141. /// then copy the patch from FV to temp buffer for faster access.
  142. ///
  143. MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize;
  144. if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) {
  145. MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize));
  146. if (MicrocodeBuffer != NULL) {
  147. DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));
  148. CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);
  149. return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;
  150. } else {
  151. DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
  152. }
  153. } else {
  154. DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n"));
  155. }
  156. return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
  157. }
  158. /**
  159. Update HSIO policy per board.
  160. @param[in] Policy - Policy PPI pointer (caller should ensure it is valid pointer)
  161. **/
  162. VOID
  163. InstallPlatformHsioPtssTable (
  164. IN VOID *Policy
  165. )
  166. {
  167. HSIO_PTSS_TABLES *UnknowPtssTables;
  168. HSIO_PTSS_TABLES *SpecificPtssTables;
  169. HSIO_PTSS_TABLES *PtssTables;
  170. UINT8 PtssTableIndex;
  171. UINT32 UnknowTableSize;
  172. UINT32 SpecificTableSize;
  173. UINT32 TableSize;
  174. UINT32 Entry;
  175. UINT8 LaneNum;
  176. UINT8 Index;
  177. UINT8 MaxSataPorts;
  178. UINT8 MaxPciePorts;
  179. UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
  180. UINT8 PciePort;
  181. UINTN RpBase;
  182. UINTN RpDevice;
  183. UINTN RpFunction;
  184. UINT32 StrapFuseCfg;
  185. UINT8 PcieControllerCfg;
  186. PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
  187. PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
  188. EFI_STATUS Status;
  189. Status = GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
  190. ASSERT_EFI_ERROR (Status);
  191. Status = GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
  192. ASSERT_EFI_ERROR (Status);
  193. UnknowPtssTables = NULL;
  194. UnknowTableSize = 0;
  195. SpecificPtssTables = NULL;
  196. SpecificTableSize = 0;
  197. if (GetPchGeneration () == SklPch) {
  198. switch (PchStepping ()) {
  199. case PchLpB0:
  200. case PchLpB1:
  201. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
  202. UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
  203. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
  204. SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
  205. break;
  206. case PchLpC0:
  207. case PchLpC1:
  208. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
  209. UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
  210. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
  211. SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
  212. break;
  213. case PchHB0:
  214. case PchHC0:
  215. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
  216. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
  217. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
  218. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
  219. break;
  220. case PchHD0:
  221. case PchHD1:
  222. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
  223. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
  224. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
  225. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
  226. break;
  227. default:
  228. UnknowPtssTables = NULL;
  229. UnknowTableSize = 0;
  230. SpecificPtssTables = NULL;
  231. SpecificTableSize = 0;
  232. DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
  233. }
  234. } else {
  235. switch (PchStepping ()) {
  236. case KblPchHA0:
  237. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
  238. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
  239. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
  240. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
  241. break;
  242. default:
  243. UnknowPtssTables = NULL;
  244. UnknowTableSize = 0;
  245. SpecificPtssTables = NULL;
  246. SpecificTableSize = 0;
  247. DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
  248. }
  249. }
  250. PtssTableIndex = 0;
  251. MaxSataPorts = GetPchMaxSataPortNum ();
  252. MaxPciePorts = GetPchMaxPciePortNum ();
  253. ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
  254. //
  255. //Populate PCIe topology based on lane configuration
  256. //
  257. for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
  258. Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
  259. ASSERT_EFI_ERROR (Status);
  260. RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
  261. StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
  262. PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
  263. DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
  264. }
  265. for (Index = 0; Index < MaxPciePorts; Index++) {
  266. DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
  267. }
  268. //
  269. //Case 1: BoardId is known, Topology is known/unknown
  270. //Case 1a: SATA
  271. //
  272. PtssTables = SpecificPtssTables;
  273. TableSize = SpecificTableSize;
  274. for (Index = 0; Index < MaxSataPorts; Index++) {
  275. if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  276. for (Entry = 0; Entry < TableSize; Entry++) {
  277. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  278. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
  279. )
  280. {
  281. PtssTableIndex++;
  282. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
  283. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
  284. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
  285. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
  286. } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
  287. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
  288. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
  289. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
  290. }
  291. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
  292. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
  293. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
  294. }
  295. } else {
  296. ASSERT (FALSE);
  297. }
  298. }
  299. }
  300. }
  301. }
  302. //
  303. //Case 1b: PCIe
  304. //
  305. for (Index = 0; Index < MaxPciePorts; Index++) {
  306. if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  307. for (Entry = 0; Entry < TableSize; Entry++) {
  308. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  309. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
  310. (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
  311. PtssTableIndex++;
  312. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
  313. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
  314. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE;
  315. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
  316. } else {
  317. ASSERT (FALSE);
  318. }
  319. }
  320. }
  321. }
  322. }
  323. //
  324. //Case 2: BoardId is unknown, Topology is known/unknown
  325. //
  326. if (PtssTableIndex == 0) {
  327. DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
  328. PtssTables = UnknowPtssTables;
  329. TableSize = UnknowTableSize;
  330. for (Index = 0; Index < MaxSataPorts; Index++) {
  331. if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  332. for (Entry = 0; Entry < TableSize; Entry++) {
  333. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  334. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
  335. )
  336. {
  337. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
  338. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
  339. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
  340. HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
  341. } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
  342. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
  343. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
  344. HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
  345. }
  346. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
  347. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
  348. HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
  349. }
  350. } else {
  351. ASSERT (FALSE);
  352. }
  353. }
  354. }
  355. }
  356. }
  357. for (Index = 0; Index < MaxPciePorts; Index++) {
  358. if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  359. for (Entry = 0; Entry < TableSize; Entry++) {
  360. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  361. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
  362. (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
  363. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
  364. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
  365. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = TRUE;
  366. HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
  367. } else {
  368. ASSERT (FALSE);
  369. }
  370. }
  371. }
  372. }
  373. }
  374. }
  375. }
  376. /**
  377. Update PreMem phase silicon policy per board.
  378. @param[in] Policy - Policy PPI pointer.
  379. @retval Policy - Policy PPI pointer.
  380. **/
  381. VOID *
  382. EFIAPI
  383. SiliconPolicyUpdatePreMem (
  384. IN VOID *Policy
  385. )
  386. {
  387. EFI_STATUS Status;
  388. SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
  389. MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
  390. VOID *Buffer;
  391. UINTN FspNvsBufferSize;
  392. VOID *FspNvsBufferPtr;
  393. UINT8 SpdAddressTable[4];
  394. DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n"));
  395. if (Policy != NULL) {
  396. SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
  397. SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
  398. SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
  399. SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
  400. MiscPeiPreMemConfig = NULL;
  401. Status = GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
  402. ASSERT_EFI_ERROR (Status);
  403. if (MiscPeiPreMemConfig != NULL) {
  404. //
  405. // Pass board specific SpdAddressTable to policy
  406. //
  407. CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4));
  408. //
  409. // Set size of SMRAM
  410. //
  411. MiscPeiPreMemConfig->TsegSize = PcdGet32 (PcdTsegSize);
  412. //
  413. // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
  414. // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI added in FSP 2.1, hence
  415. // the platform specific S3DataPtr must be used instead.
  416. //
  417. FspNvsBufferPtr = NULL;
  418. FspNvsBufferSize = 0;
  419. Status = PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableGuid, &FspNvsBufferPtr, &FspNvsBufferSize);
  420. if (Status == EFI_SUCCESS) {
  421. DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid - %r\n", Status));
  422. DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize));
  423. MiscPeiPreMemConfig->S3DataPtr = FspNvsBufferPtr;
  424. }
  425. //
  426. // In FSP Dispatch Mode these BAR values are initialized by SiliconPolicyInitPreMem() in
  427. // KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c; this function calls
  428. // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to initialize all Config Blocks
  429. // with default policy values (including these BAR values.) PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  430. // is implemented in the FSP. Make sure the value that FSP is using matches the value we are using.
  431. //
  432. ASSERT (PcdGet64 (PcdMchBaseAddress) <= 0xFFFFFFFF);
  433. ASSERT (MiscPeiPreMemConfig->MchBar == (UINT32) PcdGet64 (PcdMchBaseAddress));
  434. ASSERT (MiscPeiPreMemConfig->SmbusBar == PcdGet16 (PcdSmbusBaseAddress));
  435. }
  436. MemConfigNoCrc = NULL;
  437. Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
  438. ASSERT_EFI_ERROR (Status);
  439. if (MemConfigNoCrc != NULL) {
  440. MemConfigNoCrc->PlatformMemorySize = PcdGet32 (PcdPeiMinMemorySize);
  441. //
  442. // Only if SpdAddressTables are all zero we need to pass hard-coded SPD data buffer.
  443. // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTables policy.
  444. //
  445. if (*((UINT32 *) (UINTN) SpdAddressTable) == 0) {
  446. DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n"));
  447. CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
  448. CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
  449. }
  450. DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
  451. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
  452. if (Buffer) {
  453. CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer, 12);
  454. CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*) Buffer + 12, 12);
  455. }
  456. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
  457. if (Buffer) {
  458. CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffer, 8);
  459. CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8);
  460. }
  461. DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
  462. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
  463. if (Buffer) {
  464. CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), Buffer, 6);
  465. }
  466. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
  467. if (Buffer) {
  468. CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Buffer, 10);
  469. }
  470. }
  471. //
  472. // Update PCD policy
  473. //
  474. InstallPlatformHsioPtssTable (Policy);
  475. // Board-specific policy overrides
  476. PeiFspBoardPolicyUpdatePreMem (Policy);
  477. }
  478. return Policy;
  479. }
  480. /**
  481. Update PostMem phase silicon policy per board.
  482. @param[in] Policy - Policy PPI pointer.
  483. @retval Policy - Policy PPI pointer.
  484. **/
  485. VOID *
  486. EFIAPI
  487. SiliconPolicyUpdatePostMem (
  488. IN VOID *Policy
  489. )
  490. {
  491. EFI_STATUS Status;
  492. EFI_BOOT_MODE BootMode;
  493. VOID *Buffer;
  494. VOID *MemBuffer;
  495. UINT32 Size;
  496. GRAPHICS_PEI_CONFIG *GtConfig;
  497. CPU_CONFIG *CpuConfig;
  498. DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
  499. Status = PeiServicesGetBootMode (&BootMode);
  500. ASSERT_EFI_ERROR (Status);
  501. GtConfig = NULL;
  502. Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
  503. ASSERT_EFI_ERROR (Status);
  504. if (GtConfig != NULL) {
  505. //
  506. // Always enable PEI graphics initialization.
  507. //
  508. GtConfig->PeiGraphicsPeimInit = 1;
  509. Size = 0;
  510. Buffer = NULL;
  511. PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
  512. if (Buffer == NULL) {
  513. DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
  514. //
  515. // Graphics initialization is unnecessary,
  516. // OS has present framebuffer.
  517. //
  518. } else if (BootMode != BOOT_ON_S3_RESUME) {
  519. MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
  520. if ((MemBuffer != NULL) && (Buffer != NULL)) {
  521. CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
  522. GtConfig->GraphicsConfigPtr = MemBuffer;
  523. } else {
  524. DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
  525. GtConfig->GraphicsConfigPtr = 0;
  526. }
  527. }
  528. DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
  529. DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
  530. Size = 0;
  531. Buffer = NULL;
  532. PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
  533. if (Buffer == NULL) {
  534. DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
  535. } else {
  536. MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
  537. if ((MemBuffer != NULL) && (Buffer != NULL)) {
  538. CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
  539. GtConfig->LogoPtr = MemBuffer;
  540. GtConfig->LogoSize = Size;
  541. } else {
  542. DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
  543. GtConfig->LogoPtr = 0;
  544. GtConfig->LogoSize = 0;
  545. }
  546. }
  547. DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr));
  548. DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoSize));
  549. }
  550. CpuConfig = NULL;
  551. Status = GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID *)&CpuConfig);
  552. ASSERT_EFI_ERROR (Status);
  553. if (CpuConfig != NULL) {
  554. CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch ();
  555. }
  556. if (Policy != NULL) {
  557. // Board-specific policy overrides
  558. PeiFspBoardPolicyUpdate (Policy);
  559. }
  560. return Policy;
  561. }
  562. /**
  563. Update late phase silicon policy per board.
  564. @param[in] Policy - Policy PPI pointer.
  565. @retval Policy - Policy PPI pointer.
  566. **/
  567. VOID *
  568. EFIAPI
  569. SiliconPolicyUpdateLate (
  570. IN VOID *Policy
  571. )
  572. {
  573. return Policy;
  574. }