PeiAspireVn7Dash572GInitPreMemLib.c 7.7 KB

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  1. /** @file
  2. Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include <PiPei.h>
  6. #include <Library/DebugLib.h>
  7. #include <Library/IoLib.h>
  8. #include <Library/MemoryAllocationLib.h>
  9. #include <Library/PcdLib.h>
  10. #include <Library/PchCycleDecodingLib.h>
  11. #include <Library/PchPmcLib.h>
  12. #include <Library/PchResetLib.h>
  13. #include <Library/PciLib.h>
  14. #include <Library/SiliconInitLib.h>
  15. #include <Library/TimerLib.h>
  16. #include <Library/PeiLib.h>
  17. #include <Library/GpioLib.h>
  18. #include <GpioPinsSklLp.h>
  19. #include <IndustryStandard/TpmPtp.h>
  20. #include <PchAccess.h>
  21. #include "PeiAspireVn7Dash572GInitLib.h"
  22. #include <ConfigBlock.h>
  23. #include <ConfigBlock/MemoryConfig.h>
  24. #ifndef STALL_ONE_MILLI_SECOND
  25. #define STALL_ONE_MILLI_SECOND 1000
  26. #endif
  27. //
  28. // Reference RCOMP resistors on motherboard - for Aspire VN7-572G
  29. //
  30. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorAspireVn7Dash572G[SA_MRC_MAX_RCOMP] = { 121, 80, 100 };
  31. //
  32. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for Aspire VN7-572G
  33. //
  34. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAspireVn7Dash572G[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
  35. //
  36. // dGPU power GPIO definitions
  37. #define DGPU_PRESENT GPIO_SKL_LP_GPP_A20 /* Active low */
  38. #define DGPU_HOLD_RST GPIO_SKL_LP_GPP_B4 /* Active low */
  39. #define DGPU_PWR_EN GPIO_SKL_LP_GPP_B21 /* Active low */
  40. EFI_STATUS
  41. EFIAPI
  42. AspireVn7Dash572GBoardDetect (
  43. VOID
  44. );
  45. /**
  46. Aspire VN7-572G board configuration init function for PEI pre-memory phase.
  47. **/
  48. VOID
  49. AspireVn7Dash572GInitPreMem (
  50. VOID
  51. )
  52. {
  53. //
  54. // HSIO PTSS Table
  55. //
  56. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
  57. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
  58. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
  59. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
  60. //
  61. // DRAM related definition
  62. //
  63. PcdSet8S (PcdSaMiscUserBd, 5); // ULT/ULX/Mobile Halo
  64. PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4: "VREF_CA to CH_A and VREF_DQ_B to CH_B"
  65. // TODO: Clear Dq/Dqs?
  66. PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);
  67. PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorAspireVn7Dash572G);
  68. PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAspireVn7Dash572G);
  69. //
  70. // Example policy for DIMM slots implementation boards:
  71. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  72. // by reading from DIMM SPD.
  73. // 2. No need to apply hardcoded SpdData buffers here for such board.
  74. // Example:
  75. // PcdMrcSpdAddressTable0 = 0xA0
  76. // PcdMrcSpdAddressTable1 = 0xA2
  77. // PcdMrcSpdAddressTable2 = 0xA4
  78. // PcdMrcSpdAddressTable3 = 0xA6
  79. // PcdMrcSpdData = 0
  80. // PcdMrcSpdDataSize = 0
  81. //
  82. PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
  83. PcdSet8S (PcdMrcSpdAddressTable1, 0);
  84. PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
  85. PcdSet8S (PcdMrcSpdAddressTable3, 0);
  86. PcdSet32S (PcdMrcSpdData, 0);
  87. PcdSet16S (PcdMrcSpdDataSize, 0);
  88. }
  89. /**
  90. Configures GPIO before memory is ready.
  91. **/
  92. EFI_STATUS
  93. EFIAPI
  94. GpioInitPreMem (
  95. VOID
  96. )
  97. {
  98. EFI_STATUS Status;
  99. DEBUG ((DEBUG_INFO, "GpioInitPreMem() Start\n"));
  100. Status = GpioConfigurePads (mGpioTableAspireVn7Dash572G_earlySize, mGpioTableAspireVn7Dash572G_early);
  101. if (EFI_ERROR (Status)) {
  102. DEBUG ((DEBUG_ERROR, "Failed to configure early GPIOs!\n"));
  103. return EFI_DEVICE_ERROR;
  104. }
  105. DEBUG ((DEBUG_INFO, "GpioInitPreMem() End\n"));
  106. return EFI_SUCCESS;
  107. }
  108. /**
  109. Initialises the dGPU.
  110. **/
  111. VOID
  112. DgpuPowerOn (
  113. VOID
  114. )
  115. {
  116. UINT32 OutputVal;
  117. DEBUG ((DEBUG_INFO, "DgpuPowerOn() Start\n"));
  118. GpioGetOutputValue (DGPU_PRESENT, &OutputVal);
  119. if (!OutputVal) {
  120. DEBUG ((DEBUG_INFO, "dGPU present, enable power...\n"));
  121. GpioSetOutputValue (DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
  122. MicroSecondDelay (2 * STALL_ONE_MILLI_SECOND);
  123. GpioSetOutputValue (DGPU_PWR_EN, 0); // Assert dGPU_PWR_EN#
  124. MicroSecondDelay (7 * STALL_ONE_MILLI_SECOND);
  125. GpioSetOutputValue (DGPU_HOLD_RST, 1); // Deassert dGPU_HOLD_RST#
  126. MicroSecondDelay (30 * STALL_ONE_MILLI_SECOND);
  127. } else {
  128. DEBUG ((DEBUG_INFO, "dGPU not present, disable power...\n"));
  129. GpioSetOutputValue (DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
  130. GpioSetOutputValue (DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN#
  131. }
  132. DEBUG ((DEBUG_INFO, "DgpuPowerOn() End\n"));
  133. }
  134. /**
  135. Configure LPC.
  136. **/
  137. VOID
  138. LpcInit (
  139. VOID
  140. )
  141. {
  142. //
  143. // Program and Enable EC (sideband) Port Addresses and range
  144. //
  145. PchLpcGenIoRangeSet (0x68, 0x08);
  146. //
  147. // Program and Enable EC (index) Port Addresses and range
  148. //
  149. PchLpcGenIoRangeSet (0x1200, 0x10);
  150. }
  151. /**
  152. Configure GPIO and SIO before memory ready.
  153. @retval EFI_SUCCESS Operation success.
  154. **/
  155. EFI_STATUS
  156. EFIAPI
  157. AspireVn7Dash572GBoardInitBeforeMemoryInit (
  158. VOID
  159. )
  160. {
  161. EFI_STATUS Status;
  162. Status = GpioInitPreMem ();
  163. if (!EFI_ERROR (Status)) {
  164. DgpuPowerOn ();
  165. }
  166. AspireVn7Dash572GInitPreMem ();
  167. ///
  168. /// Do basic PCH init
  169. ///
  170. SiliconInit ();
  171. //
  172. // Fix-up LPC configuration
  173. // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64h and 62h/66h.
  174. //
  175. PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
  176. PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
  177. //
  178. // Install PCH RESET PPI and EFI RESET2 PeiService
  179. //
  180. Status = PchInitializeReset ();
  181. ASSERT_EFI_ERROR (Status);
  182. return EFI_SUCCESS;
  183. }
  184. /**
  185. Configure GPIO and SIO before memory ready.
  186. @retval EFI_SUCCESS Operation success.
  187. **/
  188. EFI_STATUS
  189. EFIAPI
  190. AspireVn7Dash572GBoardInitAfterMemoryInit (
  191. VOID
  192. )
  193. {
  194. EFI_STATUS Status;
  195. // BUGBUG: Workaround for a misbehaving system firmware not setting goIdle
  196. // - Based on prior investigation for coreboot, I suspect FSP
  197. if ((MmioRead32 (0xFED40044) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0) {
  198. DEBUG ((DEBUG_WARN, "TPM no-IdleBypass bug: workaround enabled\n"));
  199. MmioWrite32 (0xFED40040, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
  200. }
  201. // Program the same 64K range of EC memory as vendor FW
  202. Status = PchLpcMemRangeSet (0xFE800000);
  203. if (EFI_ERROR (Status)) {
  204. DEBUG ((DEBUG_WARN, "Failed to enable LGMR. Were ACPI tables built for LGMR memory map?\n"));
  205. }
  206. return EFI_SUCCESS;
  207. }
  208. EFI_STATUS
  209. EFIAPI
  210. AspireVn7Dash572GBoardDebugInit (
  211. VOID
  212. )
  213. {
  214. ///
  215. /// Do Early PCH init
  216. ///
  217. LpcInit ();
  218. // NB: MinPlatform specification defines platform initialisation flow.
  219. // Therefore, we defer board detection until we can program LPC.
  220. // - Alternatively, move the preceding calls to BoardDetect()
  221. AspireVn7Dash572GBoardDetect ();
  222. return EFI_SUCCESS;
  223. }
  224. EFI_BOOT_MODE
  225. EFIAPI
  226. AspireVn7Dash572GBoardBootModeDetect (
  227. VOID
  228. )
  229. {
  230. EFI_BOOT_MODE BootMode;
  231. UINT32 SleepType;
  232. DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
  233. // Known sane defaults; TODO: Consider "default"?
  234. BootMode = BOOT_WITH_FULL_CONFIGURATION;
  235. // TODO: Perform advanced detection (capsule/recovery)
  236. // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assume"
  237. if (GetSleepTypeAfterWakeup (&SleepType)) {
  238. switch (SleepType) {
  239. case V_PCH_ACPI_PM1_CNT_S3:
  240. BootMode = BOOT_ON_S3_RESUME;
  241. break;
  242. case V_PCH_ACPI_PM1_CNT_S4:
  243. BootMode = BOOT_ON_S4_RESUME;
  244. break;
  245. case V_PCH_ACPI_PM1_CNT_S5:
  246. BootMode = BOOT_ON_S5_RESUME;
  247. break;
  248. }
  249. }
  250. DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
  251. return BootMode;
  252. }