Platform.c 17 KB

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  1. /** @file
  2. Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
  3. Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. //
  7. // The package level header files this module uses
  8. //
  9. #include <PiPei.h>
  10. //
  11. // The Library classes this module consumes
  12. //
  13. #include <Library/DebugLib.h>
  14. #include <Library/HobLib.h>
  15. #include <Library/IoLib.h>
  16. #include <Library/MemoryAllocationLib.h>
  17. #include <Library/PcdLib.h>
  18. #include <Library/PciLib.h>
  19. #include <Library/PeimEntryPoint.h>
  20. #include <Library/PeiServicesLib.h>
  21. #include <Library/ResourcePublicationLib.h>
  22. #include <Library/CmosAccessLib.h>
  23. #include <Guid/MemoryTypeInformation.h>
  24. #include <Ppi/MasterBootMode.h>
  25. #include <IndustryStandard/Pci22.h>
  26. #include <SimicsPlatforms.h>
  27. #include "Platform.h"
  28. EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  29. { EfiACPIMemoryNVS, 0x004 },
  30. { EfiACPIReclaimMemory, 0x008 },
  31. { EfiReservedMemoryType, 0x004 },
  32. { EfiRuntimeServicesData, 0x024 },
  33. { EfiRuntimeServicesCode, 0x030 },
  34. { EfiBootServicesCode, 0x180 },
  35. { EfiBootServicesData, 0xF00 },
  36. { EfiMaxMemoryType, 0x000 }
  37. };
  38. EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
  39. {
  40. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  41. &gEfiPeiMasterBootModePpiGuid,
  42. NULL
  43. }
  44. };
  45. UINT16 mHostBridgeDevId;
  46. EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  47. BOOLEAN mS3Supported = FALSE;
  48. UINT32 mMaxCpuCount;
  49. VOID
  50. AddIoMemoryBaseSizeHob (
  51. EFI_PHYSICAL_ADDRESS MemoryBase,
  52. UINT64 MemorySize
  53. )
  54. {
  55. BuildResourceDescriptorHob (
  56. EFI_RESOURCE_MEMORY_MAPPED_IO,
  57. EFI_RESOURCE_ATTRIBUTE_PRESENT |
  58. EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  59. EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  60. EFI_RESOURCE_ATTRIBUTE_TESTED,
  61. MemoryBase,
  62. MemorySize
  63. );
  64. }
  65. VOID
  66. AddReservedMemoryBaseSizeHob (
  67. EFI_PHYSICAL_ADDRESS MemoryBase,
  68. UINT64 MemorySize,
  69. BOOLEAN Cacheable
  70. )
  71. {
  72. BuildResourceDescriptorHob (
  73. EFI_RESOURCE_MEMORY_RESERVED,
  74. EFI_RESOURCE_ATTRIBUTE_PRESENT |
  75. EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  76. EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  77. (Cacheable ?
  78. EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  79. EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  80. EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
  81. 0
  82. ) |
  83. EFI_RESOURCE_ATTRIBUTE_TESTED,
  84. MemoryBase,
  85. MemorySize
  86. );
  87. }
  88. VOID
  89. AddIoMemoryRangeHob (
  90. EFI_PHYSICAL_ADDRESS MemoryBase,
  91. EFI_PHYSICAL_ADDRESS MemoryLimit
  92. )
  93. {
  94. AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
  95. }
  96. VOID
  97. AddMemoryBaseSizeHob (
  98. EFI_PHYSICAL_ADDRESS MemoryBase,
  99. UINT64 MemorySize
  100. )
  101. {
  102. BuildResourceDescriptorHob (
  103. EFI_RESOURCE_SYSTEM_MEMORY,
  104. EFI_RESOURCE_ATTRIBUTE_PRESENT |
  105. EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  106. EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  107. EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  108. EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  109. EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
  110. EFI_RESOURCE_ATTRIBUTE_TESTED,
  111. MemoryBase,
  112. MemorySize
  113. );
  114. }
  115. VOID
  116. AddMemoryRangeHob (
  117. EFI_PHYSICAL_ADDRESS MemoryBase,
  118. EFI_PHYSICAL_ADDRESS MemoryLimit
  119. )
  120. {
  121. AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
  122. }
  123. VOID
  124. AddUntestedMemoryBaseSizeHob (
  125. EFI_PHYSICAL_ADDRESS MemoryBase,
  126. UINT64 MemorySize
  127. )
  128. {
  129. BuildResourceDescriptorHob (
  130. EFI_RESOURCE_SYSTEM_MEMORY,
  131. EFI_RESOURCE_ATTRIBUTE_PRESENT |
  132. EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  133. EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  134. EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  135. EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  136. EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
  137. MemoryBase,
  138. MemorySize
  139. );
  140. }
  141. VOID
  142. AddUntestedMemoryRangeHob (
  143. EFI_PHYSICAL_ADDRESS MemoryBase,
  144. EFI_PHYSICAL_ADDRESS MemoryLimit
  145. )
  146. {
  147. AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
  148. }
  149. VOID
  150. AddFlashDeviceRange (
  151. EFI_PHYSICAL_ADDRESS MemoryBase,
  152. UINT64 MemorySize
  153. )
  154. {
  155. BuildResourceDescriptorHob (
  156. EFI_RESOURCE_FIRMWARE_DEVICE,
  157. (EFI_RESOURCE_ATTRIBUTE_PRESENT |
  158. EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  159. EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
  160. MemoryBase,
  161. MemorySize
  162. );
  163. BuildMemoryAllocationHob (
  164. MemoryBase,
  165. MemorySize,
  166. EfiMemoryMappedIO
  167. );
  168. }
  169. VOID
  170. MemMapInitialization (
  171. VOID
  172. )
  173. {
  174. UINT64 PciIoBase;
  175. UINT64 PciIoSize;
  176. UINT32 TopOfLowRam;
  177. UINT64 PciExBarBase;
  178. UINT32 PciBase;
  179. UINT32 PciSize;
  180. PciIoBase = 0xC000;
  181. PciIoSize = 0x4000;
  182. //
  183. // Create Memory Type Information HOB
  184. //
  185. BuildGuidDataHob (
  186. &gEfiMemoryTypeInformationGuid,
  187. mDefaultMemoryTypeInformation,
  188. sizeof(mDefaultMemoryTypeInformation)
  189. );
  190. //
  191. // Video memory + Legacy BIOS region
  192. //
  193. AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
  194. TopOfLowRam = GetSystemMemorySizeBelow4gb ();
  195. PciExBarBase = 0;
  196. if (mHostBridgeDevId == INTEL_ICH10_DEVICE_ID) {
  197. //
  198. // The MMCONFIG area is expected to fall between the top of low RAM and
  199. // the base of the 32-bit PCI host aperture.
  200. //
  201. PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
  202. ASSERT (TopOfLowRam <= PciExBarBase);
  203. ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
  204. PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
  205. } else {
  206. PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
  207. }
  208. //
  209. // address purpose size
  210. // ------------ -------- -------------------------
  211. // 0x00000000 TopOfLowRam 0xDF000000
  212. // 0xDF000000 Tseg+UMA 0x01000000
  213. // 0xE0000000 PciExBarBase 0x10000000
  214. // 0xF0000000 PciBase 0x0C000000
  215. // -------------------------------------------------
  216. // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
  217. // 0xFC000000 gap 44 MB
  218. // 0xFEC00000 IO-APIC 4 KB
  219. // 0xFEC01000 gap 1020 KB
  220. // 0xFED00000 HPET 1 KB
  221. // 0xFED00400 gap 111 KB
  222. // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
  223. // 0xFED20000 gap 896 KB
  224. // 0xFEE00000 LAPIC 1 MB
  225. //
  226. PciSize = 0xFC000000 - PciBase;
  227. AddIoMemoryBaseSizeHob (PciBase, PciSize);
  228. PcdSet64S (PcdPciMmio32Base, PciBase);
  229. PcdSet64S (PcdPciMmio32Size, PciSize);
  230. AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
  231. AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
  232. if (mHostBridgeDevId == INTEL_ICH10_DEVICE_ID) {
  233. AddIoMemoryBaseSizeHob (ICH10_ROOT_COMPLEX_BASE, SIZE_16KB);
  234. //
  235. // Note: there should be an
  236. //
  237. // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
  238. // BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB, EfiMemoryMappedIO);
  239. //
  240. // call below, just like the one above for RCBA. However, Linux insists
  241. // that the MMCONFIG area be marked in the E820 or UEFI memory map as
  242. // "reserved memory" -- Linux does not content itself with a simple gap
  243. // in the memory map wherever the MCFG ACPI table points to.
  244. //
  245. // This appears to be a safety measure. The PCI Firmware Specification
  246. // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
  247. // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
  248. // [...]". (Emphasis added here.)
  249. //
  250. // Normally we add memory resource descriptor HOBs in
  251. // QemuInitializeRam(), and pre-allocate from those with memory
  252. // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
  253. // is most definitely not RAM; so, as an exception, cover it with
  254. // uncacheable reserved memory right here.
  255. //
  256. AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
  257. BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
  258. EfiReservedMemoryType);
  259. }
  260. AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
  261. // Add PCI IO Port space available for PCI resource allocations.
  262. //
  263. BuildResourceDescriptorHob (
  264. EFI_RESOURCE_IO,
  265. EFI_RESOURCE_ATTRIBUTE_PRESENT |
  266. EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
  267. PciIoBase,
  268. PciIoSize
  269. );
  270. PcdSet64S (PcdPciIoBase, PciIoBase);
  271. PcdSet64S (PcdPciIoSize, PciIoSize);
  272. //
  273. // Add flash range.
  274. //
  275. AddFlashDeviceRange (PcdGet32(PcdFlashAreaBaseAddress), PcdGet32(PcdFlashAreaSize));
  276. //
  277. // Video memory / ABSEG
  278. //
  279. AddIoMemoryBaseSizeHob (0x0A0000, 0x20000);
  280. //
  281. // Legacy BIOS region.
  282. //
  283. AddReservedMemoryBaseSizeHob (0xC0000, 0x40000, TRUE);
  284. }
  285. VOID
  286. MiscInitialization (
  287. VOID
  288. )
  289. {
  290. UINTN PmCmd;
  291. UINTN Pmba;
  292. UINT32 PmbaAndVal;
  293. UINT32 PmbaOrVal;
  294. UINTN AcpiCtlReg;
  295. UINT8 AcpiEnBit;
  296. //
  297. // Disable A20 Mask
  298. //
  299. IoOr8 (0x92, BIT1);
  300. //
  301. // Build the CPU HOB with guest RAM size dependent address width and 16-bits
  302. // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
  303. // S3 resume as well, so we build it unconditionally.)
  304. //
  305. BuildCpuHob (mPhysMemAddressWidth, 16);
  306. //
  307. // Determine platform type and save Host Bridge DID to PCD
  308. //
  309. switch (mHostBridgeDevId) {
  310. case INTEL_82441_DEVICE_ID:
  311. PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
  312. Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
  313. PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
  314. PmbaOrVal = PIIX4_PMBA_VALUE;
  315. AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
  316. AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
  317. break;
  318. case INTEL_ICH10_DEVICE_ID:
  319. PmCmd = POWER_MGMT_REGISTER_ICH10 (PCI_COMMAND_OFFSET);
  320. Pmba = POWER_MGMT_REGISTER_ICH10 (ICH10_PMBASE);
  321. PmbaAndVal = ~(UINT32)ICH10_PMBASE_MASK;
  322. PmbaOrVal = ICH10_PMBASE_VALUE;
  323. AcpiCtlReg = POWER_MGMT_REGISTER_ICH10 (ICH10_ACPI_CNTL);
  324. AcpiEnBit = ICH10_ACPI_CNTL_ACPI_EN;
  325. break;
  326. default:
  327. DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
  328. __FUNCTION__, mHostBridgeDevId));
  329. ASSERT (FALSE);
  330. return;
  331. }
  332. PcdSet16S (PcdSimicsX58HostBridgePciDevId, mHostBridgeDevId);
  333. //
  334. // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
  335. // has been configured and skip the setup here.
  336. // This matches the logic in AcpiTimerLibConstructor ().
  337. //
  338. if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
  339. //
  340. // The PEI phase should be exited with fully accessibe ACPI PM IO space:
  341. // 1. set PMBA
  342. //
  343. PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
  344. //
  345. // 2. set PCICMD/IOSE
  346. //
  347. PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
  348. //
  349. // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
  350. //
  351. PciOr8 (AcpiCtlReg, AcpiEnBit);
  352. }
  353. if (mHostBridgeDevId == INTEL_ICH10_DEVICE_ID) {
  354. //
  355. // Set Root Complex Register Block BAR
  356. //
  357. PciWrite32 (
  358. POWER_MGMT_REGISTER_ICH10 (ICH10_RCBA),
  359. ICH10_ROOT_COMPLEX_BASE | ICH10_RCBA_EN
  360. );
  361. }
  362. //
  363. // Set the PM I/O base address to 0x400
  364. //
  365. PciAndThenOr32 (
  366. PCI_LIB_ADDRESS (
  367. 0,
  368. 31,
  369. 0,
  370. 0x40
  371. ),
  372. (UINT32) ~0xfc0, ICH10_PMBASE_VALUE
  373. );
  374. //
  375. // Enable AHCI and all ports on the SATA controller.
  376. //
  377. // Address MAP Reg, setting AHCI mode
  378. //
  379. PciOr16 (PCI_LIB_ADDRESS (0, 31, 2, 0x90), 0x0060);
  380. //
  381. //Enabling Ports 0-5
  382. //
  383. PciOr16 (PCI_LIB_ADDRESS (0, 31, 2, 0x92), 0x003F);
  384. //
  385. //Disabling Sata Controller 2, bit 25 = 1, bit 0 = 1
  386. //
  387. MmioWrite32(0xFED1F418, 0x02000001);
  388. //
  389. //Enable HPET at FED0_0000h ? FED0_03FFh
  390. //
  391. MmioWrite8(ICH10_ROOT_COMPLEX_BASE + 0x3404, 0x80);
  392. //
  393. //Config and enable APIC
  394. //
  395. MmioWrite32(0xFEC00000 + 0X0, 0);
  396. MmioWrite32(0xFEC00000 + 0X10, PcdGet8(PcdIoApicId)<<24);
  397. MmioWrite8(ICH10_ROOT_COMPLEX_BASE + 0x31FF, 0x01);
  398. }
  399. VOID
  400. BootModeInitialization (
  401. VOID
  402. )
  403. {
  404. EFI_STATUS Status;
  405. DEBUG((EFI_D_INFO, "modeValue = %x\n", IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12)));
  406. if (IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12) == 0x5) {
  407. mBootMode = BOOT_ON_S3_RESUME;
  408. }
  409. Status = PeiServicesSetBootMode (mBootMode);
  410. ASSERT_EFI_ERROR (Status);
  411. Status = PeiServicesInstallPpi (mPpiBootMode);
  412. ASSERT_EFI_ERROR (Status);
  413. }
  414. VOID
  415. ReserveEmuVariableNvStore (
  416. )
  417. {
  418. EFI_PHYSICAL_ADDRESS VariableStore;
  419. //
  420. // Allocate storage for NV variables early on so it will be
  421. // at a consistent address. Since VM memory is preserved
  422. // across reboots, this allows the NV variable storage to survive
  423. // a VM reboot.
  424. //
  425. VariableStore =
  426. (EFI_PHYSICAL_ADDRESS)(UINTN)
  427. AllocateRuntimePages (
  428. EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
  429. );
  430. DEBUG ((EFI_D_INFO,
  431. "Reserved variable store memory: 0x%lX; size: %dkb\n",
  432. VariableStore,
  433. (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
  434. ));
  435. PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
  436. }
  437. VOID
  438. SimicsVersionCheck(
  439. VOID
  440. )
  441. {
  442. UINTN PciAddrPtr;
  443. UINT8 CapOffset;
  444. STATIC CHAR8 SimicsStr[0x100];
  445. UINTN i;
  446. UINT32 MajorVersion;
  447. UINT32 MinorVersion;
  448. UINT32 ModelNumber;
  449. PciAddrPtr = PCI_LIB_ADDRESS(0, SIMICS_SIDEBANDPCI_DEV, SIMICS_SIDEBANDPCI_FUNC, 0);
  450. CapOffset = PciRead8(PciAddrPtr + PCI_CAPBILITY_POINTER_OFFSET);
  451. if (CapOffset != 0xFF) {
  452. ModelNumber = PciRead32(PciAddrPtr + CapOffset + 4);
  453. MajorVersion = PciRead32(PciAddrPtr + CapOffset + 8);
  454. MinorVersion = PciRead32(PciAddrPtr + CapOffset + 0xc);
  455. for (i = 0; i < 0x80; i++) {
  456. SimicsStr[i] = PciRead8(PciAddrPtr + CapOffset + 0x10 + i);
  457. }
  458. DEBUG((EFI_D_INFO, "=============SIMICS Version info=============\n"));
  459. DEBUG((EFI_D_INFO, "Model number = %d\n", ModelNumber));
  460. DEBUG((EFI_D_INFO, "Major version = %d\n", MajorVersion));
  461. DEBUG((EFI_D_INFO, "Minor version = %d\n", MinorVersion));
  462. DEBUG((EFI_D_INFO, "%a\n", SimicsStr));
  463. DEBUG((EFI_D_INFO, "=============================================\n"));
  464. }
  465. }
  466. VOID
  467. DebugDumpCmos (
  468. VOID
  469. )
  470. {
  471. UINT8 Loop;
  472. DEBUG ((EFI_D_INFO, "CMOS:\n"));
  473. for (Loop = 0; Loop < 0x80; Loop++) {
  474. if ((Loop % 0x10) == 0) {
  475. DEBUG ((EFI_D_INFO, "%02x:", Loop));
  476. }
  477. DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
  478. if ((Loop % 0x10) == 0xf) {
  479. DEBUG ((EFI_D_INFO, "\n"));
  480. }
  481. }
  482. }
  483. /**
  484. Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
  485. Set the mMaxCpuCount variable.
  486. **/
  487. VOID
  488. MaxCpuCountInitialization (
  489. VOID
  490. )
  491. {
  492. mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
  493. return;
  494. }
  495. /**
  496. Determine if S3 support is explicitly enabled.
  497. @retval TRUE If S3 support is explicitly enabled. Other functions in this
  498. library may be called (subject to their individual
  499. restrictions).
  500. FALSE Otherwise. This includes unavailability of the firmware
  501. configuration interface. No other function in this library
  502. must be called.
  503. **/
  504. BOOLEAN
  505. EFIAPI
  506. QemuFwCfgS3Enabled(
  507. VOID
  508. )
  509. {
  510. //TO DO IF NEEDED
  511. return TRUE;
  512. }
  513. /**
  514. Perform Platform PEI initialization.
  515. @param FileHandle Handle of the file being invoked.
  516. @param PeiServices Describes the list of possible PEI Services.
  517. @return EFI_SUCCESS The PEIM initialized successfully.
  518. **/
  519. EFI_STATUS
  520. EFIAPI
  521. InitializePlatform (
  522. IN EFI_PEI_FILE_HANDLE FileHandle,
  523. IN CONST EFI_PEI_SERVICES **PeiServices
  524. )
  525. {
  526. EFI_STATUS Status;
  527. DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
  528. SimicsVersionCheck ();
  529. DebugDumpCmos ();
  530. if (QemuFwCfgS3Enabled ()) {
  531. DEBUG ((EFI_D_INFO, "S3 support was detected on SIMICS\n"));
  532. mS3Supported = TRUE;
  533. Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
  534. ASSERT_EFI_ERROR (Status);
  535. }
  536. AddressWidthInitialization ();
  537. MaxCpuCountInitialization ();
  538. mHostBridgeDevId = PciRead16(SIMICS_HOSTBRIDGE_DID);
  539. if (FeaturePcdGet (PcdSmmSmramRequire)) {
  540. X58TsegMbytesInitialization ();
  541. }
  542. PublishPeiMemory ();
  543. InitializeRamRegions ();
  544. if (mBootMode != BOOT_ON_S3_RESUME) {
  545. if (!FeaturePcdGet (PcdSmmSmramRequire)) {
  546. ReserveEmuVariableNvStore ();
  547. }
  548. MemMapInitialization ();
  549. }
  550. MiscInitialization ();
  551. InstallFeatureControlCallback ();
  552. return EFI_SUCCESS;
  553. }