PlatformCpuPolicy.c 35 KB

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  1. /** @file
  2. Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include <PiDxe.h>
  6. #include <Protocol/IntelCpuPcdsSetDone.h>
  7. #include <Setup/IioUniversalData.h>
  8. #include <Guid/SetupVariable.h>
  9. #include <Library/BaseLib.h>
  10. #include <Library/MemoryAllocationLib.h>
  11. #include <Library/BaseMemoryLib.h>
  12. #include <Library/PcdLib.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/UefiBootServicesTableLib.h>
  15. #include <Library/UefiRuntimeServicesTableLib.h>
  16. #include <Library/CpuConfigLib.h>
  17. #include <Library/HobLib.h>
  18. #include <Library/UefiLib.h>
  19. #include <Library/IoLib.h>
  20. #include <Library/CpuPpmLib.h>
  21. #include <SetupTable.h>
  22. #include <Platform.h>
  23. #include "PlatformHost.h"
  24. #include <Register/Cpuid.h>
  25. CHAR16 mCpuSocketStr[8][5] = {L"CPU0", L"CPU1", L"CPU2", L"CPU3", L"CPU4", L"CPU5", L"CPU6", L"CPU7"};
  26. CHAR16 mCpuAssetTagStr[] = L"UNKNOWN";
  27. IIO_UDS *mIioUds;
  28. /**
  29. GC_TODO: add routine description
  30. @param None
  31. @retval None
  32. **/
  33. VOID
  34. CheckAndReAssignSocketId(
  35. VOID
  36. )
  37. {
  38. #define APICID_MASK_BIT14_8 0x7F //current Si support programmable APICID up to 15bits
  39. CPU_SOCKET_ID_INFO *pcdSktIdPtr;
  40. UINT32 i, IntraPackageIdBits;
  41. UINTN PcdSize;
  42. EFI_STATUS Status;
  43. UINT32 MaxSocketCount;
  44. MaxSocketCount = FixedPcdGet32(PcdMaxCpuSocketCount);
  45. DEBUG ((EFI_D_ERROR, "::SocketCount %08x\n", MaxSocketCount));
  46. pcdSktIdPtr = (CPU_SOCKET_ID_INFO *)PcdGetPtr(PcdCpuSocketId);
  47. PcdSize = PcdGetSize (PcdCpuSocketId); //MAX_SOCKET * sizeof(CPU_SOCKET_ID_INFO);
  48. ASSERT(PcdSize == (MAX_SOCKET * sizeof(CPU_SOCKET_ID_INFO)));
  49. Status = PcdSetPtrS (PcdCpuSocketId, &PcdSize, (VOID *)pcdSktIdPtr);
  50. ASSERT_EFI_ERROR (Status);
  51. if (EFI_ERROR(Status)) return;
  52. DEBUG ((EFI_D_INFO, "::SockeId Pcd at %08x, size %x\n", PcdGetPtr(PcdCpuSocketId), PcdSize));
  53. for(i = 0; i < MAX_SOCKET; i++) {
  54. if(mIioUds->PlatformData.CpuQpiInfo[i].Valid) {
  55. pcdSktIdPtr[i].DefaultSocketId = mIioUds->PlatformData.CpuQpiInfo[i].SocId;
  56. pcdSktIdPtr[i].NewSocketId = mIioUds->PlatformData.CpuQpiInfo[i].SocId;
  57. } else {
  58. pcdSktIdPtr[i].DefaultSocketId = (UINT32)-1; //make sure Default and New are same
  59. pcdSktIdPtr[i].NewSocketId = (UINT32)-1;
  60. }
  61. }
  62. AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &IntraPackageIdBits, NULL, NULL, NULL);
  63. //assign new socketId
  64. for(i = 0; i < MAX_SOCKET; i++) {
  65. if(pcdSktIdPtr[i].DefaultSocketId == (UINT32)-1) continue;
  66. switch(IntraPackageIdBits) {
  67. case 4: //socket bit starts from bit4 of ApicId
  68. case 5: //socket bit starts from bit5 of ApicId
  69. if(MAX_SOCKET == 4) {
  70. pcdSktIdPtr[i].NewSocketId |= (APICID_MASK_BIT14_8 << (8 - IntraPackageIdBits));
  71. } else {
  72. //3bit in lower 8bit as skt field, to avoid ApicID= FFs, leave bit8 untouched for 8S
  73. pcdSktIdPtr[i].NewSocketId |= (0x7E << (8 - IntraPackageIdBits)); //leave bit8 to 0 so we don't have FFs in ApicId
  74. }
  75. break;
  76. case 6: //socket bit starts from bit6 of ApicId
  77. if(MAX_SOCKET == 4) {
  78. //only 2bit in lower 8bit as skt field, to avoid ApicID= FFs, leave bit8 untouched for 4S
  79. pcdSktIdPtr[i].NewSocketId |= (0x7E << (8 - IntraPackageIdBits));
  80. } else {
  81. //only 2bit in lower 8bit as skt field, to avoid ApicID= FFs, leave bit9 untouched for 8S
  82. pcdSktIdPtr[i].NewSocketId |= (0x7C << (8 - IntraPackageIdBits));
  83. }
  84. break;
  85. default:
  86. DEBUG ((EFI_D_INFO, "::Need more info to make sure we can support!!!\n"));
  87. break;
  88. } //end switch
  89. }
  90. }
  91. /**
  92. This is the EFI driver entry point for the CpuPolicy Driver. This
  93. driver is responsible for getting microcode patches from FV.
  94. @param ImageHandle - Handle for the image of this driver.
  95. @param SystemTable - Pointer to the EFI System Table.
  96. @retval EFI_SUCCESS - Protocol installed sucessfully.
  97. **/
  98. EFI_STATUS
  99. EFIAPI
  100. PlatformCpuPolicyEntryPoint (
  101. IN EFI_HANDLE ImageHandle,
  102. IN EFI_SYSTEM_TABLE *SystemTable
  103. )
  104. {
  105. EFI_STATUS Status;
  106. SETUP_DATA SetupData;
  107. UINT32 CpuPolicy;
  108. UINT32 CpuPolicyEx1;
  109. EFI_HANDLE Handle;
  110. UINT32 CsrSapmCtl = 0;
  111. UINT32 CsrPerfPlimitCtl = 0;
  112. UINT8 PCPSOptions = 0;
  113. UINT32 AdvPwrMgtCtl;
  114. UINT8 socket;
  115. UINT32 *UpiInPkgCEntry = NULL;
  116. UINT32 *PcieInPkgCEntry = NULL;
  117. UINT32 MsrPowerCtlLow = 0;
  118. UINT32 MsrTurboPowerLimitHigh = 0;
  119. UINT32 MsrTurboPowerLimitLow = 0;
  120. UINT32 MsrPriPlaneCurrentCfgCtlHigh = 0;
  121. UINT32 MsrPriPlaneCurrentCfgCtlLow = 0;
  122. UINT32 CsrDynamicPerfPowerCtl = 0;
  123. UINT32 CsrPcieIltrOvrd = 0;
  124. UINT32 MsrPerfBiasConfig = 0;
  125. MSR_REGISTER *CStateLatencyCtrl = NULL;
  126. UINT32 CpuFamilyModelStepping;
  127. UINT64 i;
  128. UINT64 *Addr;
  129. EFI_PPM_STRUCT *ppm = NULL;
  130. XE_STRUCT *XePtr = NULL;
  131. TURBO_RATIO_LIMIT_RATIO_CORES *TurboRatioLimitRatioCores = NULL;
  132. UINT8 PackageCStateSetting = 0;
  133. UINT8 CpuCStateValue = 0;
  134. EFI_GUID UniversalDataGuid = IIO_UNIVERSAL_DATA_GUID;
  135. EFI_HOB_GUID_TYPE *GuidHob;
  136. GuidHob = GetFirstGuidHob (&UniversalDataGuid);
  137. ASSERT (GuidHob != NULL);
  138. if(GuidHob == NULL) {
  139. return EFI_NOT_FOUND;
  140. }
  141. mIioUds = GET_GUID_HOB_DATA(GuidHob);
  142. AsmCpuid (1, &CpuFamilyModelStepping, NULL, NULL, NULL);
  143. Status = gBS->AllocatePool (
  144. EfiBootServicesData,
  145. sizeof(EFI_PPM_STRUCT),
  146. (VOID **) &Addr
  147. );
  148. if(Status != EFI_SUCCESS) {
  149. DEBUG ((EFI_D_INFO, "::Failed to allocate mem for PPM Struct\n"));
  150. ASSERT_EFI_ERROR (Status); //may need to create a default
  151. } else {
  152. ZeroMem(Addr, sizeof(EFI_PPM_STRUCT));
  153. i = (UINT32)(*(UINT64 *)(&Addr));
  154. ppm = (EFI_PPM_STRUCT *)(Addr);
  155. Status = PcdSet64S (PcdCpuPmStructAddr, i);
  156. ASSERT_EFI_ERROR (Status);
  157. if (EFI_ERROR(Status)) return Status;
  158. DEBUG ((EFI_D_INFO, "::PPM mem allocate @ %x %X %X\n", i, PcdGet64(PcdCpuPmStructAddr), ppm));
  159. UpiInPkgCEntry = (UINT32 *)(((EFI_PPM_STRUCT *)Addr)->Cst.PkgCstEntryCriteriaMaskKti);
  160. PcieInPkgCEntry = (UINT32 *)(((EFI_PPM_STRUCT *)Addr)->Cst.PkgCstEntryCriteriaMaskPcie);
  161. XePtr = (XE_STRUCT *)(&((EFI_PPM_STRUCT *)Addr)->Xe);
  162. TurboRatioLimitRatioCores = (TURBO_RATIO_LIMIT_RATIO_CORES *)(&((EFI_PPM_STRUCT *)Addr)->TurboRatioLimitRatioCores);
  163. DEBUG ((EFI_D_INFO, ":: XE @ %X\n", (UINTN) XePtr));
  164. CStateLatencyCtrl = (MSR_REGISTER *)(ppm->Cst.LatencyCtrl);
  165. DEBUG ((EFI_D_INFO, "CStateLatencyCtrl[%X]\n", (UINTN) CStateLatencyCtrl));
  166. }
  167. //
  168. // Read the current system configuration variable store.
  169. //
  170. ZeroMem (&SetupData, sizeof(SETUP_DATA));
  171. CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
  172. CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketCommonRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION));
  173. CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION));
  174. CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemoryConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION));
  175. CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
  176. CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGetPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
  177. CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM_CONFIGURATION));
  178. CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
  179. {
  180. if (SetupData.SocketConfig.PowerManagementConfig.PackageCState == PPM_AUTO) {
  181. PackageCStateSetting = 3; //POR Default = C6
  182. } else {
  183. PackageCStateSetting = SetupData.SocketConfig.PowerManagementConfig.PackageCState;
  184. }
  185. // Temporary override to prevent accidental enabling until CR dungeon approves
  186. if (SetupData.SocketConfig.PowerManagementConfig.PackageCState != 0) {
  187. DEBUG((EFI_D_ERROR, "Crystal Ridge Configuration Warning: Package c-states are not disabled\n"));
  188. }
  189. if ((SetupData.SocketConfig.PowerManagementConfig.C6Enable == PPM_AUTO) ||
  190. SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomousCstateEnable) {
  191. CpuCStateValue |= C6_ENABLE; //POR Default = Enabled
  192. } else {
  193. CpuCStateValue |= (SetupData.SocketConfig.PowerManagementConfig.C6Enable * C6_ENABLE);
  194. }
  195. Status = PcdSet8S (PcdCpuCoreCStateValue, CpuCStateValue);
  196. ASSERT_EFI_ERROR (Status);
  197. if (EFI_ERROR(Status)) return Status;
  198. //
  199. // If ACC enabled, then override C1E to be enabled
  200. //
  201. if (SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomousCstateEnable) {
  202. SetupData.SocketConfig.PowerManagementConfig.ProcessorC1eEnable = TRUE;
  203. }
  204. //
  205. // Verify that the value being set is within the valid range 0 to MAX_SOCKET - 1
  206. //
  207. if (SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection > MAX_SOCKET)
  208. SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection= 0xFF;
  209. Status = PcdSet8S (PcdSbspSelection, SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection);
  210. ASSERT_EFI_ERROR (Status);
  211. if (EFI_ERROR(Status)) return Status;
  212. //
  213. // Map CPU setup options to PcdCpuProcessorFeatureUserConfiguration
  214. //
  215. CpuPolicy = (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorHyperThreadingDisable ? 0 : PCD_CPU_HT_BIT) |
  216. (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable ? PCD_CPU_EIST_BIT : 0) |
  217. (SetupData.SocketConfig.PowerManagementConfig.ProcessorC1eEnable ? PCD_CPU_C1E_BIT : 0) |
  218. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorVmxEnable ? PCD_CPU_VT_BIT : 0) |
  219. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorSmxEnable ? PCD_CPU_LT_BIT : 0) |
  220. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.FastStringEnable ? PCD_CPU_FAST_STRING_BIT : 0) |
  221. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.CpuidMaxValue ? PCD_CPU_MAX_CPUID_VALUE_LIMIT_BIT : 0) |
  222. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ExecuteDisableBit ? PCD_CPU_EXECUTE_DISABLE_BIT : 0) |
  223. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.MachineCheckEnable ? PCD_CPU_MACHINE_CHECK_BIT : 0) |
  224. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.DCUStreamerPrefetcherEnable ? PCD_CPU_DCU_PREFETCHER_BIT : 0) |
  225. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.DCUIPPrefetcherEnable ? PCD_CPU_IP_PREFETCHER_BIT : 0) |
  226. PCD_CPU_MONITOR_MWAIT_BIT | //never disable Mwait
  227. (SetupData.SocketConfig.PowerManagementConfig.TurboMode ? PCD_CPU_TURBO_MODE_BIT : 0) |
  228. (SetupData.SocketConfig.PowerManagementConfig.EnableThermalMonitor ? PCD_CPU_THERMAL_MANAGEMENT_BIT : 0);
  229. if (SetupData.SocketConfig.PowerManagementConfig.TStateEnable && (SetupData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) {
  230. CpuPolicy |= (SetupData.SocketConfig.PowerManagementConfig.TStateEnable ? PCD_CPU_TSTATE_BIT : 0);
  231. }
  232. CpuPolicyEx1 = (SetupData.SocketConfig.SocketProcessorCoreConfiguration.MlcStreamerPrefetcherEnable ? PCD_CPU_MLC_STREAMER_PREFETCHER_BIT : 0) |
  233. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.MlcSpatialPrefetcherEnable ? PCD_CPU_MLC_SPATIAL_PREFETCHER_BIT : 0) |
  234. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ThreeStrikeTimer ? PCD_CPU_THREE_STRIKE_COUNTER_BIT : 0) |
  235. PCD_CPU_ENERGY_PERFORMANCE_BIAS_BIT |
  236. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorX2apic ? PCD_CPU_X2APIC_BIT : 0) |
  237. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.AesEnable ? PCD_CPU_AES_BIT : 0) |
  238. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.PCIeDownStreamPECIWrite ? PCD_CPU_PECI_DOWNSTREAM_WRITE_BIT : 0) |
  239. PCD_CPU_C_STATE_BIT;
  240. PCPSOptions = (SetupData.SocketConfig.PowerManagementConfig.ProcessorSinglePCTLEn ? PCD_CPU_PCPS_SINGLEPCTL : 0) |
  241. (SetupData.SocketConfig.PowerManagementConfig.ProcessorSPD ? PCD_CPU_PCPS_SPD : 0) |
  242. (SetupData.SocketConfig.PowerManagementConfig.PStateDomain ? PCD_CPU_PCPS_PSTATEDOMAIN : 0) |
  243. (UINT8) SetupData.SocketConfig.PowerManagementConfig.ProcessorEistPsdFunc;
  244. ppm->Pst.PcpsCtrl = PCPSOptions;
  245. ppm->OverclockingLock = SetupData.SocketConfig.PowerManagementConfig.OverclockingLock;
  246. ppm->FastRaplDutyCycle = SetupData.SocketConfig.PowerManagementConfig.FastRaplDutyCycle;
  247. if(mIioUds->PlatformData.EVMode)
  248. CpuPolicy &= ~PCD_CPU_LT_BIT;
  249. if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable) {
  250. Status = PcdSetBoolS (PcdCpuHwCoordination, SetupData.SocketConfig.PowerManagementConfig.ProcessorEistPsdFunc ? FALSE : TRUE);
  251. ASSERT_EFI_ERROR (Status);
  252. if (EFI_ERROR(Status)) return Status;
  253. }
  254. Status = PcdSet16S (PcdCpuAcpiLvl2Addr, PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_ACPI_LV2);
  255. ASSERT_EFI_ERROR (Status);
  256. if (EFI_ERROR(Status)) return Status;
  257. Status = PcdSet8S (PcdCpuPackageCStateLimit, PackageCStateSetting);
  258. ASSERT_EFI_ERROR (Status);
  259. if (EFI_ERROR(Status)) return Status;
  260. if ((SetupData.SocketConfig.PowerManagementConfig.TStateEnable) && (SetupData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) {
  261. Status = PcdSet8S (PcdCpuClockModulationDutyCycle, SetupData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling);
  262. ASSERT_EFI_ERROR (Status);
  263. if (EFI_ERROR(Status)) return Status;
  264. ppm->TCCActivationOffset = SetupData.SocketConfig.PowerManagementConfig.TCCActivationOffset;
  265. }
  266. Status = PcdSet8S (PcdCpuDcuMode, SetupData.SocketConfig.SocketProcessorCoreConfiguration.DCUModeSelection);
  267. ASSERT_EFI_ERROR (Status);
  268. if (EFI_ERROR(Status)) return Status;
  269. if((CpuFamilyModelStepping >> 4) == CPU_FAMILY_SKX) {
  270. Status = PcdSetBoolS (PcdCpuSmmRuntimeCtlHooks, TRUE);
  271. ASSERT_EFI_ERROR (Status);
  272. if (EFI_ERROR(Status)) return Status;
  273. } else {
  274. Status = PcdSetBoolS (PcdCpuSmmRuntimeCtlHooks, FALSE);
  275. ASSERT_EFI_ERROR (Status);
  276. if (EFI_ERROR(Status)) return Status;
  277. }
  278. DEBUG ((EFI_D_INFO, ":: PcdCpuSmmRuntimeCtlHooks= %x\n", PcdGetBool(PcdCpuSmmRuntimeCtlHooks)));
  279. if(mIioUds->PlatformData.EVMode || SetupData.SystemConfig.LmceEn) {
  280. Status = PcdSet8S (PcdCpuProcessorMsrLockCtrl, 0);
  281. ASSERT_EFI_ERROR (Status);
  282. if (EFI_ERROR(Status)) return Status;
  283. } else {
  284. Status = PcdSet8S (PcdCpuProcessorMsrLockCtrl, SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorMsrLockControl);
  285. ASSERT_EFI_ERROR (Status);
  286. if (EFI_ERROR(Status)) return Status;
  287. }
  288. Status = PcdSet64S(PcdCpuIioLlcWaysBitMask, SetupData.SocketConfig.SocketProcessorCoreConfiguration.IioLlcWaysMask);
  289. ASSERT_EFI_ERROR (Status);
  290. if (EFI_ERROR(Status)) return Status;
  291. Status = PcdSet64S(PcdCpuExpandedIioLlcWaysBitMask, SetupData.SocketConfig.SocketProcessorCoreConfiguration.ExpandedIioLlcWaysMask);
  292. ASSERT_EFI_ERROR (Status);
  293. if (EFI_ERROR(Status)) return Status;
  294. Status = PcdSet64S(PcdCpuRemoteWaysBitMask, SetupData.SocketConfig.SocketProcessorCoreConfiguration.RemoteWaysMask);
  295. ASSERT_EFI_ERROR (Status);
  296. if (EFI_ERROR(Status)) return Status;
  297. Status = PcdSet8S(PcdPchTraceHubEn, SetupData.SocketConfig.SocketProcessorCoreConfiguration.PchTraceHubEn);
  298. ASSERT_EFI_ERROR (Status);
  299. if (EFI_ERROR(Status)) return Status;
  300. Status = PcdSet64S(PcdCpuQlruCfgBitMask, ((UINT64) SetupData.SocketConfig.SocketProcessorCoreConfiguration.QlruCfgMask_Hi << 32) | (UINT64)SetupData.SocketConfig.SocketProcessorCoreConfiguration.QlruCfgMask_Lo );
  301. ASSERT_EFI_ERROR (Status);
  302. if (EFI_ERROR(Status)) return Status;
  303. Status = PcdSet64S(PcdCpuRRQCountThreshold, mIioUds->PlatformData.RemoteRequestThreshold);
  304. ASSERT_EFI_ERROR (Status);
  305. if (EFI_ERROR(Status)) return Status;
  306. //CSR SAPM CTL
  307. CsrSapmCtl = 0;
  308. for( socket = 0; socket < MAX_SOCKET; socket++) {
  309. CsrSapmCtl = (( SetupData.SocketConfig.PowerManagementConfig.Iio0PkgcClkGateDis[socket] << IIO012_PKGC_CLK_GATE_DISABLE_SHIFT) |
  310. ( SetupData.SocketConfig.PowerManagementConfig.Iio1PkgcClkGateDis[socket] << (IIO012_PKGC_CLK_GATE_DISABLE_SHIFT + 1)) |
  311. ( SetupData.SocketConfig.PowerManagementConfig.Iio2PkgcClkGateDis[socket] << (IIO012_PKGC_CLK_GATE_DISABLE_SHIFT + 2)) );
  312. CsrSapmCtl |= (( SetupData.SocketConfig.PowerManagementConfig.Kti23PkgcClkGateDis[socket] << KTI23_PKGC_CLK_GATE_DISABLE_SHIFT ) |
  313. ( SetupData.SocketConfig.PowerManagementConfig.Kti01PkgcClkGateDis[socket] << KTI01_PKGC_CLK_GATE_DISABLE_SHIFT ) |
  314. ( SetupData.SocketConfig.PowerManagementConfig.Kti01pllOffEna[socket] << KTI_PLL_OFF_EN_SHIFT) |
  315. ( SetupData.SocketConfig.PowerManagementConfig.Kti23pllOffEna[socket] << (KTI_PLL_OFF_EN_SHIFT + 1) ) );
  316. CsrSapmCtl |= (( SetupData.SocketConfig.PowerManagementConfig.Mc1PkgcClkGateDis[socket] << MC1_PKGC_CLK_GATE_DISABLE_SHIFT ) |
  317. ( SetupData.SocketConfig.PowerManagementConfig.Mc0PkgcClkGateDis[socket] << MC0_PKGC_CLK_GATE_DISABLE_SHIFT ) |
  318. ( SetupData.SocketConfig.PowerManagementConfig.Mc0pllOffEna[socket] << MEM_PLL_OFF_EN_SHIFT) |
  319. ( SetupData.SocketConfig.PowerManagementConfig.Mc1pllOffEna[socket] << (MEM_PLL_OFF_EN_SHIFT + 1) ));
  320. if (SetupData.SocketConfig.MemoryConfig.OppSrefEn == 1) {
  321. CsrSapmCtl |= ((1 << MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) | (1 << MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) |
  322. (1 << MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT) | (1 << MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT)) ;
  323. }
  324. CsrSapmCtl |= (( SetupData.SocketConfig.PowerManagementConfig.P0pllOffEna[socket] << IIO_PLL_OFF_EN_SHIFT) |
  325. ( SetupData.SocketConfig.PowerManagementConfig.P1pllOffEna[socket] << (IIO_PLL_OFF_EN_SHIFT + 1) ) |
  326. ( SetupData.SocketConfig.PowerManagementConfig.P2pllOffEna[socket] << (IIO_PLL_OFF_EN_SHIFT + 2) ) |
  327. ( SetupData.SocketConfig.PowerManagementConfig.SetvidDecayDisable[socket] << SETVID_DECAY_DISABLE_SHIFT ) |
  328. ( SetupData.SocketConfig.PowerManagementConfig.SapmCtlLock[socket] << SAPMCTL_LOCK_SHIFT) );
  329. ppm->SapmCtl[socket] = CsrSapmCtl;
  330. }
  331. ppm->PmaxConfig = (SetupData.SocketConfig.PowerManagementConfig.UsePmaxOffsetTable ? USER_PMAX_USE_OFFSET_TABLE : 0 ) |
  332. SetupData.SocketConfig.PowerManagementConfig.PmaxOffset |
  333. (SetupData.SocketConfig.PowerManagementConfig.PmaxSign ? USER_PMAX_NEGATIVE_BIT : 0);
  334. CsrPerfPlimitCtl = ( SetupData.SocketConfig.PowerManagementConfig.PerfPLmtThshld << PERF_PLIMIT_THRESHOLD_SHIFT ) |
  335. ( SetupData.SocketConfig.PowerManagementConfig.PerfPLimitClipC << PERF_PLIMIT_CLIP_SHIFT ) |
  336. ( SetupData.SocketConfig.PowerManagementConfig.PerfPlimitDifferential << PERF_PLIMIT_DIFFERENTIAL_SHIFT ) |
  337. ( SetupData.SocketConfig.PowerManagementConfig.PerfPLimitEn << REPERF_PLIMIT_EN_SHIFT );
  338. ppm->PerPLimitCtl = CsrPerfPlimitCtl;
  339. //
  340. // IssConfigTdpLevelInfo Bit[23:16]: the currently active Config TDP Level
  341. //
  342. ppm->Pst.ConfigTdpLevel = (UINT8) ((mIioUds->SystemStatus.IssConfigTdpLevelInfo >> 16) & 0xFF);
  343. ppm->Pst.CurrentPackageTdp = (mIioUds->SystemStatus.IssConfigTdpTdpInfo[0][ppm->Pst.ConfigTdpLevel] & 0x7FFF);
  344. for( socket = 0; socket < MAX_SOCKET; socket++) {
  345. UpiInPkgCEntry[socket] = (SetupData.SocketConfig.PowerManagementConfig.Kti0In[socket] |
  346. (SetupData.SocketConfig.PowerManagementConfig.Kti1In[socket] << 1) |
  347. (SetupData.SocketConfig.PowerManagementConfig.Kti2In[socket] << 2) );
  348. if (SetupData.SocketConfig.PowerManagementConfig.PcieIio0In[socket]) {
  349. PcieInPkgCEntry[socket] |= SET_PCIEx_MASK;
  350. }
  351. if (SetupData.SocketConfig.PowerManagementConfig.PcieIio1In[socket]) {
  352. PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 4);
  353. }
  354. if (SetupData.SocketConfig.PowerManagementConfig.PcieIio2In[socket]) {
  355. PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 8);
  356. }
  357. if (SetupData.SocketConfig.PowerManagementConfig.PcieIio3In[socket]) {
  358. PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 12);
  359. }
  360. if (SetupData.SocketConfig.PowerManagementConfig.PcieIio4In[socket]) {
  361. PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 16);
  362. }
  363. if (SetupData.SocketConfig.PowerManagementConfig.PcieIio5In[socket]) {
  364. PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 20);
  365. }
  366. }
  367. AdvPwrMgtCtl = (SetupData.SocketConfig.PowerManagementConfig.SapmctlValCtl? PCD_CPU_SAPM_CTL_VAL_CTL : 0) |
  368. (SetupData.SocketConfig.PowerManagementConfig.CurrentConfig? PCD_CPU_CURRENT_CONFIG : 0) |
  369. (SetupData.SocketConfig.PowerManagementConfig.BootPState? PCU_CPU_EFFICIENT_BOOT : 0) |
  370. (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorMsrLockControl? CPU_MSR_LOCK : 0) |
  371. (SetupData.SocketConfig.PowerManagementConfig.TurboPowerLimitCsrLock? TURBO_LIMIT_CSR_LOCK : 0);
  372. AdvPwrMgtCtl |= SetupData.SocketConfig.PowerManagementConfig.PkgCstEntryValCtl; //PCD_CPU_PKG_CST_ENTRY_VAL_CTL
  373. if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable == 0) {
  374. AdvPwrMgtCtl |= PCU_CPU_EFFICIENT_BOOT;
  375. }
  376. if (((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) && SetupData.SocketConfig.PowerManagementConfig.PriPlnCurCfgValCtl) {
  377. AdvPwrMgtCtl |= PCD_CPU_PRI_PLN_CURR_CFG_CTL;
  378. }
  379. if ((PackageCStateSetting > 0) && SetupData.SocketConfig.PowerManagementConfig.DynamicL1) {
  380. AdvPwrMgtCtl |= DYNAMIC_L1_DISABLE;
  381. }
  382. if (SetupData.SocketConfig.PowerManagementConfig.SPTWorkaround) {
  383. AdvPwrMgtCtl |= SPT_PCH_WORKAROUND;
  384. }
  385. if (SetupData.SocketConfig.PowerManagementConfig.VccSAandVccIOdisable) {
  386. AdvPwrMgtCtl |= VCCSA_VCCIO_DISABLE;
  387. }
  388. ppm->AdvPwrMgtCtlFlags = AdvPwrMgtCtl;
  389. // MSR_POWER_CTL 0x1FC
  390. MsrPowerCtlLow = ( SetupData.SocketConfig.PowerManagementConfig.PkgCLatNeg << PCH_NEG_DISABLE_SHIFT ) |
  391. ( SetupData.SocketConfig.PowerManagementConfig.LTRSwInput << LTR_SW_DISABLE_SHIFT ) |
  392. ( SetupData.SocketConfig.PowerManagementConfig.PwrPerfTuning << PWR_PERF_TUNING_CFG_MODE_SHIFT ) |
  393. ( SetupData.SocketConfig.PowerManagementConfig.PwrPerfSwitch << PWR_PERF_TUNING_ENABLE_DYN_SHIFT ) |
  394. ( SetupData.SocketConfig.PowerManagementConfig.SAPMControl << PWR_PERF_TUNING_DISABLE_SAPM_SHIFT ) |
  395. ( SetupData.SocketConfig.PowerManagementConfig.EETurboDisable << EE_TURBO_DISABLE_SHIFT ) |
  396. ( SetupData.SocketConfig.PowerManagementConfig.ProchotLock << PROCHOT_LOCK_SHIFT ) |
  397. ( SetupData.SocketConfig.PowerManagementConfig.ProcessorC1eEnable << C1E_ENABLE_SHIFT ) |
  398. ( (SetupData.SocketConfig.PowerManagementConfig.EnableProcHot & 0x1) << DIS_PROCHOT_OUT_SHIFT ) |
  399. ( (SetupData.SocketConfig.PowerManagementConfig.EnableProcHot & 0x2) >> 1 );
  400. // 5332865 BIOS needs to set bit 25 in MSR 0x1FC when enabling HWP autonomous out of band mode
  401. if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 2) { //if HWPM = OOB Mode
  402. MsrPowerCtlLow |= ( 1 << PWR_PERF_TUNING_CFG_MODE_SHIFT );
  403. }
  404. ppm->PowerCtl.Dwords.Low = MsrPowerCtlLow;
  405. ppm->ProchotRatio = SetupData.SocketConfig.PowerManagementConfig.ProchotResponseRatio;
  406. if ((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) {
  407. // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601
  408. MsrPriPlaneCurrentCfgCtlHigh = ( SetupData.SocketConfig.PowerManagementConfig.Psi3Code << PSI3_CODE_SHIFT ) |
  409. ( SetupData.SocketConfig.PowerManagementConfig.Psi3Thshld << PSI3_THSHLD_SHIFT ) |
  410. ( SetupData.SocketConfig.PowerManagementConfig.Psi2Code << PSI2_CODE_SHIFT ) |
  411. ( SetupData.SocketConfig.PowerManagementConfig.Psi2Thshld << PSI2_THSHLD_SHIFT ) |
  412. ( SetupData.SocketConfig.PowerManagementConfig.Psi1Code << PSI1_CODE_SHIFT ) |
  413. ( SetupData.SocketConfig.PowerManagementConfig.Psi1Thshld << PSI1_THSHLD_SHIFT );
  414. }
  415. MsrPriPlaneCurrentCfgCtlLow = ( SetupData.SocketConfig.PowerManagementConfig.PpcccLock << PPCCC_LOCK_SHIFT ) |
  416. ( SetupData.SocketConfig.PowerManagementConfig.CurrentLimit << CURRENT_LIMIT_SHIFT );
  417. ppm->PP0CurrentCfg.Dwords.High = MsrPriPlaneCurrentCfgCtlHigh;
  418. ppm->PP0CurrentCfg.Dwords.Low = MsrPriPlaneCurrentCfgCtlLow;
  419. // MSR_TURBO_POWER_LIMIT 0x610
  420. // CSR_TURBO_POWER_LIMIT 1:30:0:0xe8
  421. MsrTurboPowerLimitHigh = ( SetupData.SocketConfig.PowerManagementConfig.TurboPowerLimitLock << POWER_LIMIT_LOCK_SHIFT ) |
  422. ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2En << POWER_LIMIT_ENABLE_SHIFT ) |
  423. ( SetupData.SocketConfig.PowerManagementConfig.PkgClmpLim2 << PKG_CLMP_LIM_SHIFT ) |
  424. ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2Power );
  425. MsrTurboPowerLimitLow = ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1Time << POWER_LIMIT_1_TIME_SHIFT ) |
  426. ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1En << POWER_LIMIT_ENABLE_SHIFT ) |
  427. ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1Power );
  428. if ((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) {
  429. MsrTurboPowerLimitLow |= ( SetupData.SocketConfig.PowerManagementConfig.PkgClmpLim1 << PKG_CLMP_LIM_SHIFT );
  430. MsrTurboPowerLimitHigh |= ( SetupData.SocketConfig.PowerManagementConfig.PkgClmpLim2 << PKG_CLMP_LIM_SHIFT );
  431. }
  432. if ((CpuFamilyModelStepping >> 4) == CPU_FAMILY_SKX) {
  433. MsrTurboPowerLimitHigh |= ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2Time << POWER_LIMIT_1_TIME_SHIFT );
  434. }
  435. ppm->TurboPowerLimit.Dwords.Low = MsrTurboPowerLimitLow;
  436. ppm->TurboPowerLimit.Dwords.High = MsrTurboPowerLimitHigh;
  437. // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64)
  438. CsrDynamicPerfPowerCtl = ( SetupData.SocketConfig.PowerManagementConfig.UncrPerfPlmtOvrdEn << UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT ) |
  439. ( SetupData.SocketConfig.PowerManagementConfig.EetOverrideEn << EET_OVERRIDE_ENABLE_SHIFT ) |
  440. ( SetupData.SocketConfig.PowerManagementConfig.IoBwPlmtOvrdEn << IO_BW_PLIMIT_OVERRIDE_ENABLE_SHIFT ) |
  441. //( SetupData.SocketConfig.PowerManagementConfig.ImcApmOvrdEn << IMC_APM_OVERRIDE_ENABLE_SHIFT ) |
  442. ( SetupData.SocketConfig.PowerManagementConfig.IomApmOvrdEn << IOM_APM_OVERRIDE_ENABLE_SHIFT ) |
  443. ( SetupData.SocketConfig.PowerManagementConfig.QpiApmOvrdEn << QPI_APM_OVERRIDE_ENABLE_SHIFT ); //4986218: Remove both changes from 4168487
  444. if((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) {
  445. CsrDynamicPerfPowerCtl |= (( SetupData.SocketConfig.PowerManagementConfig.EepLOverride << EEP_L_OVERRIDE_SHIFT ) |
  446. ( SetupData.SocketConfig.PowerManagementConfig.EepLOverrideEn << EEP_L_OVERRIDE_ENABLE_SHIFT ) |
  447. ( SetupData.SocketConfig.PowerManagementConfig.ITurboOvrdEn << I_TURBO_OVERRIDE_ENABLE_SHIFT ) |
  448. ( SetupData.SocketConfig.PowerManagementConfig.CstDemotOvrdEN << CST_DEMOTION_OVERRIDE_ENABLE_SHIFT ) |
  449. ( SetupData.SocketConfig.PowerManagementConfig.TrboDemotOvrdEn << TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT ));
  450. }
  451. ppm->DynamicPerPowerCtl = CsrDynamicPerfPowerCtl;
  452. // CSR_PCIE_ILTR_OVRD (CSR 1:30:1:78)
  453. // SW_LTR_OVRD (MSR 0xa02) -- not used
  454. CsrPcieIltrOvrd = ( SetupData.SocketConfig.PowerManagementConfig.SnpLatVld << SNOOP_LATENCY_VLD_SHIFT ) |
  455. ( SetupData.SocketConfig.PowerManagementConfig.SnpLatOvrd << FORCE_SNOOP_OVRD_SHIFT ) |
  456. ( SetupData.SocketConfig.PowerManagementConfig.SnpLatMult << SNOOP_LATENCY_MUL_SHIFT ) |
  457. ( SetupData.SocketConfig.PowerManagementConfig.SnpLatVal << SNOOP_LATENCY_Value_SHIFT ) |
  458. ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatVld << NON_SNOOP_LATENCY_VLD_SHIFT ) |
  459. ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatOvrd << FORCE_NON_SNOOP_OVRD_SHIFT ) |
  460. ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatMult << NON_SNOOP_LATENCY_MUL_SHIFT ) |
  461. ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatVal << NON_SNOOP_LATENCY_Value_SHIFT );
  462. ppm-> PcieIltrOvrd = CsrPcieIltrOvrd;
  463. if((CpuFamilyModelStepping >> 4) == CPU_FAMILY_SKX) { //Need to check if programming needs to be limited only if Turbo mode is enabled.
  464. for(i = 0; i < 8; i++) {
  465. TurboRatioLimitRatioCores->RatioLimitRatio[i] = SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitRatio[i];
  466. TurboRatioLimitRatioCores->RatioLimitRatioMask[i] = 0xFF;
  467. if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitRatio[i] > 0) {
  468. TurboRatioLimitRatioCores->RatioLimitRatioMask[i] = 0;
  469. }
  470. TurboRatioLimitRatioCores->RatioLimitCoresMask[i] = 0xFF;
  471. TurboRatioLimitRatioCores->RatioLimitCores[i] = 0;
  472. if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitCores[i] != 0xFF) {
  473. TurboRatioLimitRatioCores->RatioLimitCoresMask[i] = 0;
  474. TurboRatioLimitRatioCores->RatioLimitCores[i] = SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitCores[i];
  475. }
  476. }
  477. }
  478. MsrPerfBiasConfig = ( SetupData.SocketConfig.PowerManagementConfig.EngAvgTimeWdw1 << AVG_TIME_Window_SHIFT ) |
  479. ( SetupData.SocketConfig.PowerManagementConfig.P0TtlTimeLow1 << PO_TOTAL_TIME_THSHLD_LOW_SHIFT ) |
  480. ( SetupData.SocketConfig.PowerManagementConfig.P0TtlTimeHigh1 << PO_TOTAL_TIME_THSHLD_HIGH_SHIFT ) |
  481. ( SetupData.SocketConfig.PowerManagementConfig.AltEngPerfBIAS << ALT_ENERGY_PERF_BIAS_SHIFT) |
  482. ( SetupData.SocketConfig.PowerManagementConfig.WorkLdConfig << WORKLD_CONFIG_SHIFT );
  483. ppm->PerfBiasConfig.Dwords.Low = MsrPerfBiasConfig;
  484. //
  485. //ProcessorHWPM-init as disabled.
  486. //
  487. ppm->Hwpm.HWPMNative = 0;
  488. ppm->Hwpm.HWPMOOB = 0;
  489. ppm->Hwpm.HWPMEnable = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable;
  490. ppm->Hwpm.AutoCState = SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomousCstateEnable;
  491. ppm->Hwpm.HWPMInterrupt = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMInterrupt;
  492. ppm->Hwpm.EPPEnable = SetupData.SocketConfig.PowerManagementConfig.ProcessorEPPEnable;
  493. ppm->Hwpm.EPPProfile = SetupData.SocketConfig.PowerManagementConfig.ProcessorEppProfile;
  494. if ((SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 1) ||
  495. (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 3)) {
  496. ppm->Hwpm.HWPMNative = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable;
  497. }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 2){
  498. ppm->Hwpm.HWPMOOB = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable;
  499. ppm->Hwpm.HWPMInterrupt = 0;
  500. }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 0){
  501. ppm->Hwpm.HWPMNative = 0;
  502. ppm->Hwpm.HWPMOOB = 0;
  503. ppm->Hwpm.HWPMInterrupt = 0;
  504. ppm->Hwpm.EPPEnable = 0;
  505. }
  506. ppm->Hwpm.APSrocketing = SetupData.SocketConfig.PowerManagementConfig.ProcessorAPSrocketing;
  507. ppm->Hwpm.Scalability = SetupData.SocketConfig.PowerManagementConfig.ProcessorScalability;
  508. ppm->Hwpm.OutofBandAlternateEPB = SetupData.SocketConfig.PowerManagementConfig.ProcessorOutofBandAlternateEPB;
  509. if(SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorX2apic && SetupData.SocketConfig.SocketProcessorCoreConfiguration.ForceX2ApicIds &&
  510. (CpuPolicyEx1 & PCD_CPU_X2APIC_BIT)) { //if user want to reprogram > 8bit ApicId (must be X2Apic too)
  511. CheckAndReAssignSocketId();
  512. }
  513. for(i = 0; i < NUM_CST_LAT_MSR; i++) { //3 CStateLatencyCtrl CSRs
  514. ppm->Cst.LatencyCtrl[i].Dwords.Low = ( SetupData.SocketConfig.PowerManagementConfig.CStateLatencyCtrlValid[i] << VALID_SHIFT ) |
  515. ( SetupData.SocketConfig.PowerManagementConfig.CStateLatencyCtrlMultiplier[i] << MULTIPLIER_SHIFT ) |
  516. ( SetupData.SocketConfig.PowerManagementConfig.CStateLatencyCtrlValue[i] << VALUE_SHIFT );
  517. }
  518. if(SetupData.SocketConfig.PowerManagementConfig.C2C3TT) { //if option is not AUTO
  519. ppm->C2C3TT = (UINT32)SetupData.SocketConfig.PowerManagementConfig.C2C3TT;
  520. } else {
  521. ppm->C2C3TT = 0x10;
  522. }
  523. } //end - else
  524. CpuPolicy |= PCD_CPU_L3_CACHE_BIT;
  525. Status = PcdSet32S (PcdCpuProcessorFeatureUserConfiguration, CpuPolicy);
  526. ASSERT_EFI_ERROR (Status);
  527. if (EFI_ERROR(Status)) return Status;
  528. Status = PcdSet32S (PcdCpuProcessorFeatureUserConfigurationEx1, CpuPolicyEx1);
  529. ASSERT_EFI_ERROR (Status);
  530. if (EFI_ERROR(Status)) return Status;
  531. if (SetupData.SystemConfig.McBankWarmBootClearError == 1) {
  532. Status = PcdSetBoolS (PcdIsPowerOnReset, TRUE);
  533. ASSERT_EFI_ERROR (Status);
  534. if (EFI_ERROR(Status)) return Status;
  535. } else {
  536. Status = PcdSetBoolS (PcdIsPowerOnReset, FALSE);
  537. ASSERT_EFI_ERROR (Status);
  538. if (EFI_ERROR(Status)) return Status;
  539. }
  540. //
  541. // Cpu Driver could be dispatched after this protocol installed.
  542. //
  543. Handle = NULL;
  544. Status = gBS->InstallProtocolInterface (
  545. &Handle,
  546. &gIntelCpuPcdsSetDoneProtocolGuid,
  547. EFI_NATIVE_INTERFACE,
  548. NULL
  549. );
  550. ASSERT_EFI_ERROR (Status);
  551. return Status;
  552. }