OpenBoardPkg.fdf 23 KB

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  1. ## @file
  2. # FDF file for the TiogaPass board.
  3. #
  4. # Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  5. # Copyright (c) 2021, American Megatrends International LLC.<BR>
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. [Defines]
  10. # Note: FlashNv PCD naming conventions are as follows:
  11. # Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
  12. # Others should be examined with an effort to work toward this guideline.
  13. # PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
  14. # PcdFlash*Size is a hex count of the length of the FD or FV
  15. # All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
  16. #
  17. # Also all values will have a PCD assigned so that they can be used in the system, and
  18. # the FlashMap edit tool can be used to change the values here, without effecting the code.
  19. # This requires all code to only use the PCD tokens to recover the values.
  20. !if gPlatformTokenSpaceGuid.PcdLinuxBootEnable == TRUE
  21. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
  22. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00200000
  23. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00200000
  24. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x000F0000
  25. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x002F0000
  26. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00100000
  27. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset = 0x003F0000
  28. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize = 0x00100000
  29. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x004F0000
  30. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00710000
  31. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00C00000
  32. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0007C000
  33. !else
  34. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
  35. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00500000
  36. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00500000
  37. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00100000
  38. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00600000
  39. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00100000
  40. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset = 0x00700000
  41. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize = 0x00200000
  42. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x00900000
  43. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00300000
  44. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00C00000
  45. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0007C000
  46. !endif
  47. [FD.Platform]
  48. BaseAddress = 0xFF000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress
  49. Size = 0x01000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaSize
  50. ErasePolarity = 1
  51. BlockSize = 0x10000
  52. NumBlocks = 0x100
  53. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  54. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  55. FV = FvAdvanced
  56. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  57. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  58. FV = FvSecurity
  59. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  60. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  61. FV = FvOsBoot
  62. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize
  63. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize
  64. FV = FvLateSiliconCompressed
  65. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  66. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  67. FV = FvUefiBoot
  68. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  69. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  70. #NV_VARIABLE_STORE
  71. DATA = {
  72. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  73. # ZeroVector []
  74. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  75. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  76. # FileSystemGuid: gEfiSystemNvDataFvGuid =
  77. # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
  78. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  79. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  80. # FvLength: 0x100000
  81. 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
  82. #Signature "_FVH" #Attributes
  83. 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
  84. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  85. 0x48, 0x00, 0x1A, 0x09, 0x00, 0x00, 0x00, 0x02,
  86. #Blockmap[0]: 16 Blocks * 0x10000 Bytes / Block
  87. 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  88. #Blockmap[1]: End
  89. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  90. ## This is the VARIABLE_STORE_HEADER
  91. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  92. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } }
  93. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  94. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  95. !else
  96. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  97. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  98. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  99. !endif
  100. #Size: 0x7c000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x7BFFB8
  101. # This can speed up the Variable Dispatch a bit.
  102. 0xB8, 0xBF, 0x07, 0x00,
  103. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  104. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  105. }
  106. 0x00C7C000|0x00002000
  107. #NV_EVENT_LOG
  108. 0x00C7E000|0x00002000
  109. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  110. #NV_FTW_WORKING
  111. DATA = {
  112. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  113. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  114. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  115. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  116. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  117. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  118. # WriteQueueSize: UINT64
  119. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  120. }
  121. 0x00C80000|0x00080000
  122. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  123. #NV_FTW_SPARE
  124. 0x00D00000|0x00030000
  125. gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
  126. FV = MICROCODE_FV
  127. 0x00D30000|0x00010000
  128. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  129. FV = FvPostMemory
  130. 0x00D40000|0x00020000
  131. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  132. FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.Fv
  133. 0x00D60000|0x00050000
  134. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  135. FV = FvPreMemory
  136. 0x00DB0000|0x00230000
  137. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  138. FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.Fv
  139. 0x00FE0000|0x00020000
  140. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  141. FILE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.Fv
  142. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
  143. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
  144. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
  145. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
  146. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
  147. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
  148. SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60
  149. SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60
  150. ################################################################################
  151. #
  152. # FV Section
  153. #
  154. # [FV] section is used to define what components or modules are placed within a flash
  155. # device file. This section also defines order the components and modules are positioned
  156. # within the image. The [FV] section consists of define statements, set statements and
  157. # module statements.
  158. #
  159. ################################################################################
  160. [FV.FvLateSiliconCompressed]
  161. FvAlignment = 16
  162. ERASE_POLARITY = 1
  163. MEMORY_MAPPED = TRUE
  164. STICKY_WRITE = TRUE
  165. LOCK_CAP = TRUE
  166. LOCK_STATUS = TRUE
  167. WRITE_DISABLED_CAP = TRUE
  168. WRITE_ENABLED_CAP = TRUE
  169. WRITE_STATUS = TRUE
  170. WRITE_LOCK_CAP = TRUE
  171. WRITE_LOCK_STATUS = TRUE
  172. READ_DISABLED_CAP = TRUE
  173. READ_ENABLED_CAP = TRUE
  174. READ_STATUS = TRUE
  175. READ_LOCK_CAP = TRUE
  176. READ_LOCK_STATUS = TRUE
  177. FvNameGuid = BA793112-EA2E-47C4-9AFE-A8FCFE603D6D
  178. FILE FV_IMAGE = A626BB34-2455-4FCA-8DFB-FEE96DB0DC5F {
  179. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  180. SECTION FV_IMAGE = $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.Fv
  181. }
  182. }
  183. [FV.MICROCODE_FV]
  184. FvAlignment = 16
  185. ERASE_POLARITY = 1
  186. MEMORY_MAPPED = TRUE
  187. STICKY_WRITE = TRUE
  188. LOCK_CAP = TRUE
  189. LOCK_STATUS = FALSE
  190. WRITE_DISABLED_CAP = TRUE
  191. WRITE_ENABLED_CAP = TRUE
  192. WRITE_STATUS = TRUE
  193. WRITE_LOCK_CAP = TRUE
  194. WRITE_LOCK_STATUS = TRUE
  195. READ_DISABLED_CAP = TRUE
  196. READ_ENABLED_CAP = TRUE
  197. READ_STATUS = TRUE
  198. READ_LOCK_CAP = TRUE
  199. READ_LOCK_STATUS = TRUE
  200. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microcode.inf
  201. [FV.FvPreMemory]
  202. FvAlignment = 16
  203. FvForceRebase = TRUE
  204. ERASE_POLARITY = 1
  205. MEMORY_MAPPED = TRUE
  206. STICKY_WRITE = TRUE
  207. LOCK_CAP = TRUE
  208. LOCK_STATUS = TRUE
  209. WRITE_DISABLED_CAP = TRUE
  210. WRITE_ENABLED_CAP = TRUE
  211. WRITE_STATUS = TRUE
  212. WRITE_LOCK_CAP = TRUE
  213. WRITE_LOCK_STATUS = TRUE
  214. READ_DISABLED_CAP = TRUE
  215. READ_ENABLED_CAP = TRUE
  216. READ_STATUS = TRUE
  217. READ_LOCK_CAP = TRUE
  218. READ_LOCK_STATUS = TRUE
  219. FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
  220. ##
  221. # PEI Apriori file example, more PEIM module added later.
  222. ##
  223. INF MdeModulePkg/Core/Pei/PeiMain.inf
  224. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  225. INF $(PLATFORM_BOARD_PACKAGE)/Policy/SystemBoard/SystemBoardPei.inf
  226. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  227. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  228. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  229. [FV.FvPostMemory]
  230. FvAlignment = 16
  231. ERASE_POLARITY = 1
  232. MEMORY_MAPPED = TRUE
  233. STICKY_WRITE = TRUE
  234. LOCK_CAP = TRUE
  235. LOCK_STATUS = TRUE
  236. WRITE_DISABLED_CAP = TRUE
  237. WRITE_ENABLED_CAP = TRUE
  238. WRITE_STATUS = TRUE
  239. WRITE_LOCK_CAP = TRUE
  240. WRITE_LOCK_STATUS = TRUE
  241. READ_DISABLED_CAP = TRUE
  242. READ_ENABLED_CAP = TRUE
  243. READ_STATUS = TRUE
  244. READ_LOCK_CAP = TRUE
  245. READ_LOCK_STATUS = TRUE
  246. FvNameGuid = C54E3E8D-9FF5-4D52-AF03-58018EB55F63
  247. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  248. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  249. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  250. [FV.FvUefiBootUncompact]
  251. BlockSize = 0x10000
  252. FvAlignment = 16
  253. ERASE_POLARITY = 1
  254. MEMORY_MAPPED = TRUE
  255. STICKY_WRITE = TRUE
  256. LOCK_CAP = TRUE
  257. LOCK_STATUS = TRUE
  258. WRITE_DISABLED_CAP = TRUE
  259. WRITE_ENABLED_CAP = TRUE
  260. WRITE_STATUS = TRUE
  261. WRITE_LOCK_CAP = TRUE
  262. WRITE_LOCK_STATUS = TRUE
  263. READ_DISABLED_CAP = TRUE
  264. READ_ENABLED_CAP = TRUE
  265. READ_STATUS = TRUE
  266. READ_LOCK_CAP = TRUE
  267. READ_LOCK_STATUS = TRUE
  268. FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
  269. ##
  270. # DXE Phase modules
  271. ##
  272. ##
  273. # DXE Apriori file example, more DXE module added later.
  274. ##
  275. #TiogaPass Override START : Added Board Specific changes in core drivers
  276. #!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  277. !include CoreUefiBootInclude.fdf
  278. #TiogaPass Override END
  279. INF PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf
  280. INF $(PLATFORM_BOARD_PACKAGE)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf
  281. INF $(PLATFORM_BOARD_PACKAGE)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf
  282. INF $(PLATFORM_BOARD_PACKAGE)/Pci/PciPlatform/PciPlatform.inf
  283. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  284. INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
  285. INF ShellPkg/Application/Shell/Shell.inf
  286. FILE DRIVER = db90bb7e-e4ba-4f07-96d6-b7076713bd2c {
  287. SECTION PE32 = edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi
  288. }
  289. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  290. !if gPlatformTokenSpaceGuid.PcdLinuxBootEnable == TRUE
  291. FILE DRIVER = 81339b04-fa8c-4be0-9ca7-916fc5319eb5 {
  292. SECTION DXE_DEPEX_EXP = {FALSE}
  293. SECTION PE32 = $(PLATFORM_BOARD_PACKAGE)/Features/LinuxBoot/LinuxBinaries/linux.efi
  294. }
  295. !endif
  296. [FV.FvUefiBoot]
  297. FvAlignment = 16
  298. ERASE_POLARITY = 1
  299. MEMORY_MAPPED = TRUE
  300. STICKY_WRITE = TRUE
  301. LOCK_CAP = TRUE
  302. LOCK_STATUS = TRUE
  303. WRITE_DISABLED_CAP = TRUE
  304. WRITE_ENABLED_CAP = TRUE
  305. WRITE_STATUS = TRUE
  306. WRITE_LOCK_CAP = TRUE
  307. WRITE_LOCK_STATUS = TRUE
  308. READ_DISABLED_CAP = TRUE
  309. READ_ENABLED_CAP = TRUE
  310. READ_STATUS = TRUE
  311. READ_LOCK_CAP = TRUE
  312. READ_LOCK_STATUS = TRUE
  313. FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
  314. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  315. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  316. SECTION FV_IMAGE = FvUefiBootUncompact
  317. }
  318. }
  319. [FV.FvOsBootUncompact]
  320. FvAlignment = 16
  321. ERASE_POLARITY = 1
  322. MEMORY_MAPPED = TRUE
  323. STICKY_WRITE = TRUE
  324. LOCK_CAP = TRUE
  325. LOCK_STATUS = TRUE
  326. WRITE_DISABLED_CAP = TRUE
  327. WRITE_ENABLED_CAP = TRUE
  328. WRITE_STATUS = TRUE
  329. WRITE_LOCK_CAP = TRUE
  330. WRITE_LOCK_STATUS = TRUE
  331. READ_DISABLED_CAP = TRUE
  332. READ_ENABLED_CAP = TRUE
  333. READ_STATUS = TRUE
  334. READ_LOCK_CAP = TRUE
  335. READ_LOCK_STATUS = TRUE
  336. FvNameGuid = 5AB52883-85DF-445B-99F7-E0C1D517A905
  337. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  338. INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  339. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  340. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  341. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  342. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  343. [FV.FvOsBoot]
  344. FvAlignment = 16
  345. ERASE_POLARITY = 1
  346. MEMORY_MAPPED = TRUE
  347. STICKY_WRITE = TRUE
  348. LOCK_CAP = TRUE
  349. LOCK_STATUS = TRUE
  350. WRITE_DISABLED_CAP = TRUE
  351. WRITE_ENABLED_CAP = TRUE
  352. WRITE_STATUS = TRUE
  353. WRITE_LOCK_CAP = TRUE
  354. WRITE_LOCK_STATUS = TRUE
  355. READ_DISABLED_CAP = TRUE
  356. READ_ENABLED_CAP = TRUE
  357. READ_STATUS = TRUE
  358. READ_LOCK_CAP = TRUE
  359. READ_LOCK_STATUS = TRUE
  360. FvNameGuid = 5e2363c4-3e9e-4203-b873-bb40df46c8e6
  361. FILE FV_IMAGE = AC09A11F-BD9F-4C87-B656-F4868EEA89B8 {
  362. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  363. SECTION FV_IMAGE = FvOsBootUncompact
  364. }
  365. }
  366. [FV.FvSecurityPreMem]
  367. FvAlignment = 16
  368. ERASE_POLARITY = 1
  369. MEMORY_MAPPED = TRUE
  370. STICKY_WRITE = TRUE
  371. LOCK_CAP = TRUE
  372. LOCK_STATUS = TRUE
  373. WRITE_DISABLED_CAP = TRUE
  374. WRITE_ENABLED_CAP = TRUE
  375. WRITE_STATUS = TRUE
  376. WRITE_LOCK_CAP = TRUE
  377. WRITE_LOCK_STATUS = TRUE
  378. READ_DISABLED_CAP = TRUE
  379. READ_ENABLED_CAP = TRUE
  380. READ_STATUS = TRUE
  381. READ_LOCK_CAP = TRUE
  382. READ_LOCK_STATUS = TRUE
  383. FvNameGuid = A91F91A0-0CCD-4E1C-9FD8-4DAE39F348FA
  384. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  385. [FV.FvSecurityPostMem]
  386. FvAlignment = 16
  387. ERASE_POLARITY = 1
  388. MEMORY_MAPPED = TRUE
  389. STICKY_WRITE = TRUE
  390. LOCK_CAP = TRUE
  391. LOCK_STATUS = TRUE
  392. WRITE_DISABLED_CAP = TRUE
  393. WRITE_ENABLED_CAP = TRUE
  394. WRITE_STATUS = TRUE
  395. WRITE_LOCK_CAP = TRUE
  396. WRITE_LOCK_STATUS = TRUE
  397. READ_DISABLED_CAP = TRUE
  398. READ_ENABLED_CAP = TRUE
  399. READ_STATUS = TRUE
  400. READ_LOCK_CAP = TRUE
  401. READ_LOCK_STATUS = TRUE
  402. FvNameGuid = 04B00029-2391-44C1-97BA-3FA8A42E9D3A
  403. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  404. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  405. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  406. !endif
  407. [FV.FvSecurityLate]
  408. FvAlignment = 16
  409. ERASE_POLARITY = 1
  410. MEMORY_MAPPED = TRUE
  411. STICKY_WRITE = TRUE
  412. LOCK_CAP = TRUE
  413. LOCK_STATUS = TRUE
  414. WRITE_DISABLED_CAP = TRUE
  415. WRITE_ENABLED_CAP = TRUE
  416. WRITE_STATUS = TRUE
  417. WRITE_LOCK_CAP = TRUE
  418. WRITE_LOCK_STATUS = TRUE
  419. READ_DISABLED_CAP = TRUE
  420. READ_ENABLED_CAP = TRUE
  421. READ_STATUS = TRUE
  422. READ_LOCK_CAP = TRUE
  423. READ_LOCK_STATUS = TRUE
  424. FvNameGuid = CCBC50ED-0902-413E-BC2C-409C906F4A80
  425. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  426. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  427. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  428. !endif
  429. [FV.FvSecurity]
  430. FvAlignment = 16
  431. ERASE_POLARITY = 1
  432. MEMORY_MAPPED = TRUE
  433. STICKY_WRITE = TRUE
  434. LOCK_CAP = TRUE
  435. LOCK_STATUS = TRUE
  436. WRITE_DISABLED_CAP = TRUE
  437. WRITE_ENABLED_CAP = TRUE
  438. WRITE_STATUS = TRUE
  439. WRITE_LOCK_CAP = TRUE
  440. WRITE_LOCK_STATUS = TRUE
  441. READ_DISABLED_CAP = TRUE
  442. READ_ENABLED_CAP = TRUE
  443. READ_STATUS = TRUE
  444. READ_LOCK_CAP = TRUE
  445. READ_LOCK_STATUS = TRUE
  446. FvNameGuid = 8CBBA80C-FE21-4749-B015-6EDFC34B6BE7
  447. FILE FV_IMAGE = A63B2BBF-7A02-4862-BF22-A1BA5258DD68 {
  448. SECTION FV_IMAGE = FvSecurityPreMem
  449. }
  450. FILE FV_IMAGE = 47B40638-0087-4938-97CF-B56983A1A07B {
  451. SECTION FV_IMAGE = FvSecurityPostMem
  452. }
  453. FILE FV_IMAGE = 605CBDF4-61DB-4B77-BAED-65232B8EC6D6 {
  454. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  455. SECTION FV_IMAGE = FvSecurityLate
  456. }
  457. }
  458. [FV.FvAdvancedPreMem]
  459. FvAlignment = 16
  460. ERASE_POLARITY = 1
  461. MEMORY_MAPPED = TRUE
  462. STICKY_WRITE = TRUE
  463. LOCK_CAP = TRUE
  464. LOCK_STATUS = TRUE
  465. WRITE_DISABLED_CAP = TRUE
  466. WRITE_ENABLED_CAP = TRUE
  467. WRITE_STATUS = TRUE
  468. WRITE_LOCK_CAP = TRUE
  469. WRITE_LOCK_STATUS = TRUE
  470. READ_DISABLED_CAP = TRUE
  471. READ_ENABLED_CAP = TRUE
  472. READ_STATUS = TRUE
  473. READ_LOCK_CAP = TRUE
  474. READ_LOCK_STATUS = TRUE
  475. FvNameGuid = EBC45843-B180-44D3-A485-0031A75DB16D
  476. !include AdvancedFeaturePkg/Include/PreMemory.fdf
  477. [FV.FvAdvancedUncompact]
  478. FvAlignment = 16
  479. ERASE_POLARITY = 1
  480. MEMORY_MAPPED = TRUE
  481. STICKY_WRITE = TRUE
  482. LOCK_CAP = TRUE
  483. LOCK_STATUS = TRUE
  484. WRITE_DISABLED_CAP = TRUE
  485. WRITE_ENABLED_CAP = TRUE
  486. WRITE_STATUS = TRUE
  487. WRITE_LOCK_CAP = TRUE
  488. WRITE_LOCK_STATUS = TRUE
  489. READ_DISABLED_CAP = TRUE
  490. READ_ENABLED_CAP = TRUE
  491. READ_STATUS = TRUE
  492. READ_LOCK_CAP = TRUE
  493. READ_LOCK_STATUS = TRUE
  494. FvNameGuid = 05411CAD-6C35-4675-B6CA-8748032144B4
  495. !include AdvancedFeaturePkg/Include/PostMemory.fdf
  496. !if gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable == TRUE
  497. INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
  498. !endif
  499. [FV.FvAdvanced]
  500. FvAlignment = 16
  501. ERASE_POLARITY = 1
  502. MEMORY_MAPPED = TRUE
  503. STICKY_WRITE = TRUE
  504. LOCK_CAP = TRUE
  505. LOCK_STATUS = TRUE
  506. WRITE_DISABLED_CAP = TRUE
  507. WRITE_ENABLED_CAP = TRUE
  508. WRITE_STATUS = TRUE
  509. WRITE_LOCK_CAP = TRUE
  510. WRITE_LOCK_STATUS = TRUE
  511. READ_DISABLED_CAP = TRUE
  512. READ_ENABLED_CAP = TRUE
  513. READ_STATUS = TRUE
  514. READ_LOCK_CAP = TRUE
  515. READ_LOCK_STATUS = TRUE
  516. FvNameGuid = 59584CB6-0740-4EE6-A335-A46B370A101A
  517. FILE FV_IMAGE = 0112F63C-E0EA-4CA7-BFAA-9574DB03B230 {
  518. SECTION FV_IMAGE = FvAdvancedPreMem
  519. }
  520. FILE FV_IMAGE = 07FC4960-5322-4DDC-A6A4-A17DE492DFE3 {
  521. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  522. SECTION FV_IMAGE = FvAdvancedUncompact
  523. }
  524. }
  525. [FV.FvDummy]
  526. FvAlignment = 16
  527. FvForceRebase = FALSE
  528. ERASE_POLARITY = 1
  529. MEMORY_MAPPED = TRUE
  530. STICKY_WRITE = TRUE
  531. LOCK_CAP = TRUE
  532. LOCK_STATUS = TRUE
  533. WRITE_DISABLED_CAP = TRUE
  534. WRITE_ENABLED_CAP = TRUE
  535. WRITE_STATUS = TRUE
  536. WRITE_LOCK_CAP = TRUE
  537. WRITE_LOCK_STATUS = TRUE
  538. READ_DISABLED_CAP = TRUE
  539. READ_ENABLED_CAP = TRUE
  540. READ_STATUS = TRUE
  541. READ_LOCK_CAP = TRUE
  542. READ_LOCK_STATUS = TRUE
  543. # Add dummy FV here to build the PCD in FV into PCD database.
  544. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.inf
  545. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.inf
  546. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.inf
  547. INF RuleOverride = BIN_FV $(PLATFORM_SI_BIN_PACKAGE)/FV/FvLateSilicon/$(TARGET)/FvLateSilicon.inf
  548. ################################################################################
  549. #
  550. # Rules are use with the [FV] section's module INF type to define
  551. # how an FFS file is created for a given INF file. The following Rule are the default
  552. # rules for the different module type. User can add the customized rules to define the
  553. # content of the FFS file.
  554. #
  555. ################################################################################
  556. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf