OpenBoardPkg.fdf 27 KB

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  1. ## @file
  2. # FDF file of Platform.
  3. #
  4. # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. [Defines]
  10. !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
  11. ################################################################################
  12. #
  13. # FD Section
  14. # The [FD] Section is made up of the definition statements and a
  15. # description of what goes into the Flash Device Image. Each FD section
  16. # defines one flash "device" image. A flash device image may be one of
  17. # the following: Removable media bootable image (like a boot floppy
  18. # image,) an Option ROM image (that would be "flashed" into an add-in
  19. # card,) a System "Flash" image (that would be burned into a system's
  20. # flash) or an Update ("Capsule") image that will be used to update and
  21. # existing system flash.
  22. #
  23. ################################################################################
  24. [FD.KabylakeRvp3]
  25. #
  26. # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
  27. # assigned with PCD values. Instead, it uses the definitions for its variety, which
  28. # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
  29. #
  30. BaseAddress = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the FLASH Device.
  31. Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize #The size in bytes of the FLASH Device
  32. ErasePolarity = 1
  33. BlockSize = $(FLASH_BLOCK_SIZE)
  34. NumBlocks = $(FLASH_NUM_BLOCKS)
  35. DEFINE SIPKG_DXE_SMM_BIN = INF
  36. DEFINE SIPKG_PEI_BIN = INF
  37. # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
  38. # So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
  39. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
  40. SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  41. SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  42. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
  43. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
  44. SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  45. SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  46. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
  47. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
  48. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  49. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
  50. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
  51. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
  52. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
  53. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
  54. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
  55. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
  56. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
  57. ################################################################################
  58. #
  59. # Following are lists of FD Region layout which correspond to the locations of different
  60. # images within the flash device.
  61. #
  62. # Regions must be defined in ascending order and may not overlap.
  63. #
  64. # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
  65. # the pipe "|" character, followed by the size of the region, also in hex with the leading
  66. # "0x" characters. Like:
  67. # Offset|Size
  68. # PcdOffsetCName|PcdSizeCName
  69. # RegionType <FV, DATA, or FILE>
  70. # Fv Size can be adjusted
  71. #
  72. ################################################################################
  73. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  74. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  75. #NV_VARIABLE_STORE
  76. DATA = {
  77. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  78. # ZeroVector []
  79. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  80. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  81. # FileSystemGuid
  82. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  83. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  84. # FvLength: 0x40000
  85. 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  86. #Signature "_FVH" #Attributes
  87. 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
  88. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  89. #
  90. # Be careful on CheckSum field.
  91. #
  92. 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
  93. #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
  94. 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  95. #Blockmap[1]: End
  96. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  97. ## This is the VARIABLE_STORE_HEADER
  98. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  99. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
  100. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  101. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  102. !else
  103. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  104. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  105. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  106. !endif
  107. #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
  108. # This can speed up the Variable Dispatch a bit.
  109. 0xB8, 0xDF, 0x01, 0x00,
  110. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  111. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  112. }
  113. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  114. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  115. #NV_FTW_WORKING
  116. DATA = {
  117. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  118. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  119. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  120. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  121. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  122. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  123. # WriteQueueSize: UINT64
  124. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  125. }
  126. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  127. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  128. #NV_FTW_SPARE
  129. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  130. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  131. FV = FvAdvanced
  132. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  133. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  134. FV = FvSecurity
  135. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  136. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  137. FV = FvOsBoot
  138. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  139. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  140. FV = FvUefiBoot
  141. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  142. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  143. FV = FvPostMemory
  144. gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  145. gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  146. #Microcode
  147. FV = FvMicrocode
  148. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  149. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  150. # FSP_S Section
  151. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
  152. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  153. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  154. # FSP_M Section
  155. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
  156. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  157. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  158. # FSP_T Section
  159. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
  160. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  161. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  162. FV = FvPreMemory
  163. ################################################################################
  164. #
  165. # FV Section
  166. #
  167. # [FV] section is used to define what components or modules are placed within a flash
  168. # device file. This section also defines order the components and modules are positioned
  169. # within the image. The [FV] section consists of define statements, set statements and
  170. # module statements.
  171. #
  172. ################################################################################
  173. [FV.FvMicrocode]
  174. BlockSize = $(FLASH_BLOCK_SIZE)
  175. FvAlignment = 16
  176. ERASE_POLARITY = 1
  177. MEMORY_MAPPED = TRUE
  178. STICKY_WRITE = TRUE
  179. LOCK_CAP = TRUE
  180. LOCK_STATUS = FALSE
  181. WRITE_DISABLED_CAP = TRUE
  182. WRITE_ENABLED_CAP = TRUE
  183. WRITE_STATUS = TRUE
  184. WRITE_LOCK_CAP = TRUE
  185. WRITE_LOCK_STATUS = TRUE
  186. READ_DISABLED_CAP = TRUE
  187. READ_ENABLED_CAP = TRUE
  188. READ_STATUS = FALSE
  189. READ_LOCK_CAP = TRUE
  190. READ_LOCK_STATUS = TRUE
  191. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
  192. [FV.FvPreMemory]
  193. BlockSize = $(FLASH_BLOCK_SIZE)
  194. FvAlignment = 16
  195. ERASE_POLARITY = 1
  196. MEMORY_MAPPED = TRUE
  197. STICKY_WRITE = TRUE
  198. LOCK_CAP = TRUE
  199. LOCK_STATUS = TRUE
  200. WRITE_DISABLED_CAP = TRUE
  201. WRITE_ENABLED_CAP = TRUE
  202. WRITE_STATUS = TRUE
  203. WRITE_LOCK_CAP = TRUE
  204. WRITE_LOCK_STATUS = TRUE
  205. READ_DISABLED_CAP = TRUE
  206. READ_ENABLED_CAP = TRUE
  207. READ_STATUS = TRUE
  208. READ_LOCK_CAP = TRUE
  209. READ_LOCK_STATUS = TRUE
  210. FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
  211. INF UefiCpuPkg/SecCore/SecCore.inf
  212. !if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
  213. #
  214. # PeiMain is needed only for FSP API mode or EDK2 build,
  215. # in FSP dispatch mode the one inside FSP Binary is launched.
  216. #
  217. INF MdeModulePkg/Core/Pei/PeiMain.inf
  218. !endif
  219. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  220. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  221. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  222. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  223. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  224. INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
  225. [FV.FvPostMemoryUncompact]
  226. BlockSize = $(FLASH_BLOCK_SIZE)
  227. FvAlignment = 16
  228. ERASE_POLARITY = 1
  229. MEMORY_MAPPED = TRUE
  230. STICKY_WRITE = TRUE
  231. LOCK_CAP = TRUE
  232. LOCK_STATUS = TRUE
  233. WRITE_DISABLED_CAP = TRUE
  234. WRITE_ENABLED_CAP = TRUE
  235. WRITE_STATUS = TRUE
  236. WRITE_LOCK_CAP = TRUE
  237. WRITE_LOCK_STATUS = TRUE
  238. READ_DISABLED_CAP = TRUE
  239. READ_ENABLED_CAP = TRUE
  240. READ_STATUS = TRUE
  241. READ_LOCK_CAP = TRUE
  242. READ_LOCK_STATUS = TRUE
  243. FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
  244. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  245. # Init Board Config PCD
  246. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  247. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  248. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  249. !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
  250. FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
  251. SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
  252. SECTION UI = "Vbt"
  253. }
  254. FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
  255. SECTION RAW = MdeModulePkg/Logo/Logo.bmp
  256. }
  257. !endif # PcdPeiDisplayEnable
  258. [FV.FvPostMemory]
  259. BlockSize = $(FLASH_BLOCK_SIZE)
  260. FvAlignment = 16
  261. ERASE_POLARITY = 1
  262. MEMORY_MAPPED = TRUE
  263. STICKY_WRITE = TRUE
  264. LOCK_CAP = TRUE
  265. LOCK_STATUS = TRUE
  266. WRITE_DISABLED_CAP = TRUE
  267. WRITE_ENABLED_CAP = TRUE
  268. WRITE_STATUS = TRUE
  269. WRITE_LOCK_CAP = TRUE
  270. WRITE_LOCK_STATUS = TRUE
  271. READ_DISABLED_CAP = TRUE
  272. READ_ENABLED_CAP = TRUE
  273. READ_STATUS = TRUE
  274. READ_LOCK_CAP = TRUE
  275. READ_LOCK_STATUS = TRUE
  276. FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
  277. FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
  278. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  279. SECTION FV_IMAGE = FvPostMemoryUncompact
  280. }
  281. }
  282. [FV.FvUefiBootUncompact]
  283. BlockSize = $(FLASH_BLOCK_SIZE)
  284. FvAlignment = 16
  285. ERASE_POLARITY = 1
  286. MEMORY_MAPPED = TRUE
  287. STICKY_WRITE = TRUE
  288. LOCK_CAP = TRUE
  289. LOCK_STATUS = TRUE
  290. WRITE_DISABLED_CAP = TRUE
  291. WRITE_ENABLED_CAP = TRUE
  292. WRITE_STATUS = TRUE
  293. WRITE_LOCK_CAP = TRUE
  294. WRITE_LOCK_STATUS = TRUE
  295. READ_DISABLED_CAP = TRUE
  296. READ_ENABLED_CAP = TRUE
  297. READ_STATUS = TRUE
  298. READ_LOCK_CAP = TRUE
  299. READ_LOCK_STATUS = TRUE
  300. FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
  301. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  302. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  303. INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
  304. INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
  305. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  306. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  307. INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
  308. INF ShellPkg/Application/Shell/Shell.inf
  309. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  310. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  311. #
  312. # Below module is used by FSP API mode
  313. #
  314. INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
  315. !endif
  316. INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
  317. [FV.FvUefiBoot]
  318. BlockSize = $(FLASH_BLOCK_SIZE)
  319. FvAlignment = 16
  320. ERASE_POLARITY = 1
  321. MEMORY_MAPPED = TRUE
  322. STICKY_WRITE = TRUE
  323. LOCK_CAP = TRUE
  324. LOCK_STATUS = TRUE
  325. WRITE_DISABLED_CAP = TRUE
  326. WRITE_ENABLED_CAP = TRUE
  327. WRITE_STATUS = TRUE
  328. WRITE_LOCK_CAP = TRUE
  329. WRITE_LOCK_STATUS = TRUE
  330. READ_DISABLED_CAP = TRUE
  331. READ_ENABLED_CAP = TRUE
  332. READ_STATUS = TRUE
  333. READ_LOCK_CAP = TRUE
  334. READ_LOCK_STATUS = TRUE
  335. FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
  336. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  337. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  338. SECTION FV_IMAGE = FvUefiBootUncompact
  339. }
  340. }
  341. [FV.FvOsBootUncompact]
  342. BlockSize = $(FLASH_BLOCK_SIZE)
  343. FvAlignment = 16
  344. ERASE_POLARITY = 1
  345. MEMORY_MAPPED = TRUE
  346. STICKY_WRITE = TRUE
  347. LOCK_CAP = TRUE
  348. LOCK_STATUS = TRUE
  349. WRITE_DISABLED_CAP = TRUE
  350. WRITE_ENABLED_CAP = TRUE
  351. WRITE_STATUS = TRUE
  352. WRITE_LOCK_CAP = TRUE
  353. WRITE_LOCK_STATUS = TRUE
  354. READ_DISABLED_CAP = TRUE
  355. READ_ENABLED_CAP = TRUE
  356. READ_STATUS = TRUE
  357. READ_LOCK_CAP = TRUE
  358. READ_LOCK_STATUS = TRUE
  359. FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
  360. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  361. INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
  362. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  363. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
  364. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  365. INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  366. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  367. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  368. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  369. INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  370. !endif
  371. [FV.FvLateSilicon]
  372. BlockSize = $(FLASH_BLOCK_SIZE)
  373. FvAlignment = 16
  374. ERASE_POLARITY = 1
  375. MEMORY_MAPPED = TRUE
  376. STICKY_WRITE = TRUE
  377. LOCK_CAP = TRUE
  378. LOCK_STATUS = TRUE
  379. WRITE_DISABLED_CAP = TRUE
  380. WRITE_ENABLED_CAP = TRUE
  381. WRITE_STATUS = TRUE
  382. WRITE_LOCK_CAP = TRUE
  383. WRITE_LOCK_STATUS = TRUE
  384. READ_DISABLED_CAP = TRUE
  385. READ_ENABLED_CAP = TRUE
  386. READ_STATUS = TRUE
  387. READ_LOCK_CAP = TRUE
  388. READ_LOCK_STATUS = TRUE
  389. FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
  390. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  391. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf
  392. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
  393. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
  394. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
  395. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
  396. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
  397. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
  398. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
  399. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
  400. !endif
  401. [FV.FvOsBoot]
  402. BlockSize = $(FLASH_BLOCK_SIZE)
  403. FvAlignment = 16
  404. ERASE_POLARITY = 1
  405. MEMORY_MAPPED = TRUE
  406. STICKY_WRITE = TRUE
  407. LOCK_CAP = TRUE
  408. LOCK_STATUS = TRUE
  409. WRITE_DISABLED_CAP = TRUE
  410. WRITE_ENABLED_CAP = TRUE
  411. WRITE_STATUS = TRUE
  412. WRITE_LOCK_CAP = TRUE
  413. WRITE_LOCK_STATUS = TRUE
  414. READ_DISABLED_CAP = TRUE
  415. READ_ENABLED_CAP = TRUE
  416. READ_STATUS = TRUE
  417. READ_LOCK_CAP = TRUE
  418. READ_LOCK_STATUS = TRUE
  419. FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
  420. FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
  421. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  422. SECTION FV_IMAGE = FvOsBootUncompact
  423. }
  424. }
  425. FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
  426. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  427. SECTION FV_IMAGE = FvLateSilicon
  428. }
  429. }
  430. [FV.FvSecurityPreMemory]
  431. BlockSize = $(FLASH_BLOCK_SIZE)
  432. FvAlignment = 16 #FV alignment and FV attributes setting.
  433. ERASE_POLARITY = 1
  434. MEMORY_MAPPED = TRUE
  435. STICKY_WRITE = TRUE
  436. LOCK_CAP = TRUE
  437. LOCK_STATUS = TRUE
  438. WRITE_DISABLED_CAP = TRUE
  439. WRITE_ENABLED_CAP = TRUE
  440. WRITE_STATUS = TRUE
  441. WRITE_LOCK_CAP = TRUE
  442. WRITE_LOCK_STATUS = TRUE
  443. READ_DISABLED_CAP = TRUE
  444. READ_ENABLED_CAP = TRUE
  445. READ_STATUS = TRUE
  446. READ_LOCK_CAP = TRUE
  447. READ_LOCK_STATUS = TRUE
  448. FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
  449. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  450. INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  451. INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
  452. [FV.FvSecurityPostMemory]
  453. BlockSize = $(FLASH_BLOCK_SIZE)
  454. FvAlignment = 16 #FV alignment and FV attributes setting.
  455. ERASE_POLARITY = 1
  456. MEMORY_MAPPED = TRUE
  457. STICKY_WRITE = TRUE
  458. LOCK_CAP = TRUE
  459. LOCK_STATUS = TRUE
  460. WRITE_DISABLED_CAP = TRUE
  461. WRITE_ENABLED_CAP = TRUE
  462. WRITE_STATUS = TRUE
  463. WRITE_LOCK_CAP = TRUE
  464. WRITE_LOCK_STATUS = TRUE
  465. READ_DISABLED_CAP = TRUE
  466. READ_ENABLED_CAP = TRUE
  467. READ_STATUS = TRUE
  468. READ_LOCK_CAP = TRUE
  469. READ_LOCK_STATUS = TRUE
  470. FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
  471. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  472. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  473. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  474. !endif
  475. [FV.FvSecurityLate]
  476. BlockSize = $(FLASH_BLOCK_SIZE)
  477. FvAlignment = 16
  478. ERASE_POLARITY = 1
  479. MEMORY_MAPPED = TRUE
  480. STICKY_WRITE = TRUE
  481. LOCK_CAP = TRUE
  482. LOCK_STATUS = TRUE
  483. WRITE_DISABLED_CAP = TRUE
  484. WRITE_ENABLED_CAP = TRUE
  485. WRITE_STATUS = TRUE
  486. WRITE_LOCK_CAP = TRUE
  487. WRITE_LOCK_STATUS = TRUE
  488. READ_DISABLED_CAP = TRUE
  489. READ_ENABLED_CAP = TRUE
  490. READ_STATUS = TRUE
  491. READ_LOCK_CAP = TRUE
  492. READ_LOCK_STATUS = TRUE
  493. FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
  494. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  495. INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
  496. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  497. INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf
  498. !endif
  499. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  500. INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
  501. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  502. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  503. !endif
  504. !endif
  505. [FV.FvSecurity]
  506. BlockSize = $(FLASH_BLOCK_SIZE)
  507. FvAlignment = 16
  508. ERASE_POLARITY = 1
  509. MEMORY_MAPPED = TRUE
  510. STICKY_WRITE = TRUE
  511. LOCK_CAP = TRUE
  512. LOCK_STATUS = TRUE
  513. WRITE_DISABLED_CAP = TRUE
  514. WRITE_ENABLED_CAP = TRUE
  515. WRITE_STATUS = TRUE
  516. WRITE_LOCK_CAP = TRUE
  517. WRITE_LOCK_STATUS = TRUE
  518. READ_DISABLED_CAP = TRUE
  519. READ_ENABLED_CAP = TRUE
  520. READ_STATUS = TRUE
  521. READ_LOCK_CAP = TRUE
  522. READ_LOCK_STATUS = TRUE
  523. FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
  524. FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
  525. SECTION FV_IMAGE = FvSecurityPreMemory
  526. }
  527. FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
  528. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  529. SECTION FV_IMAGE = FvSecurityPostMemory
  530. }
  531. }
  532. FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
  533. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  534. SECTION FV_IMAGE = FvSecurityLate
  535. }
  536. }
  537. [FV.FvAdvancedPreMem]
  538. FvAlignment = 16
  539. ERASE_POLARITY = 1
  540. MEMORY_MAPPED = TRUE
  541. STICKY_WRITE = TRUE
  542. LOCK_CAP = TRUE
  543. LOCK_STATUS = TRUE
  544. WRITE_DISABLED_CAP = TRUE
  545. WRITE_ENABLED_CAP = TRUE
  546. WRITE_STATUS = TRUE
  547. WRITE_LOCK_CAP = TRUE
  548. WRITE_LOCK_STATUS = TRUE
  549. READ_DISABLED_CAP = TRUE
  550. READ_ENABLED_CAP = TRUE
  551. READ_STATUS = TRUE
  552. READ_LOCK_CAP = TRUE
  553. READ_LOCK_STATUS = TRUE
  554. FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
  555. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  556. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
  557. !endif
  558. [FV.FvAdvancedPostMem]
  559. FvAlignment = 16
  560. ERASE_POLARITY = 1
  561. MEMORY_MAPPED = TRUE
  562. STICKY_WRITE = TRUE
  563. LOCK_CAP = TRUE
  564. LOCK_STATUS = TRUE
  565. WRITE_DISABLED_CAP = TRUE
  566. WRITE_ENABLED_CAP = TRUE
  567. WRITE_STATUS = TRUE
  568. WRITE_LOCK_CAP = TRUE
  569. WRITE_LOCK_STATUS = TRUE
  570. READ_DISABLED_CAP = TRUE
  571. READ_ENABLED_CAP = TRUE
  572. READ_STATUS = TRUE
  573. READ_LOCK_CAP = TRUE
  574. READ_LOCK_STATUS = TRUE
  575. FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
  576. [FV.FvAdvancedLate]
  577. FvAlignment = 16
  578. ERASE_POLARITY = 1
  579. MEMORY_MAPPED = TRUE
  580. STICKY_WRITE = TRUE
  581. LOCK_CAP = TRUE
  582. LOCK_STATUS = TRUE
  583. WRITE_DISABLED_CAP = TRUE
  584. WRITE_ENABLED_CAP = TRUE
  585. WRITE_STATUS = TRUE
  586. WRITE_LOCK_CAP = TRUE
  587. WRITE_LOCK_STATUS = TRUE
  588. READ_DISABLED_CAP = TRUE
  589. READ_ENABLED_CAP = TRUE
  590. READ_STATUS = TRUE
  591. READ_LOCK_CAP = TRUE
  592. READ_LOCK_STATUS = TRUE
  593. FvNameGuid = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D
  594. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  595. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
  596. INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
  597. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  598. !endif
  599. [FV.FvAdvanced]
  600. BlockSize = $(FLASH_BLOCK_SIZE)
  601. FvAlignment = 16
  602. ERASE_POLARITY = 1
  603. MEMORY_MAPPED = TRUE
  604. STICKY_WRITE = TRUE
  605. LOCK_CAP = TRUE
  606. LOCK_STATUS = TRUE
  607. WRITE_DISABLED_CAP = TRUE
  608. WRITE_ENABLED_CAP = TRUE
  609. WRITE_STATUS = TRUE
  610. WRITE_LOCK_CAP = TRUE
  611. WRITE_LOCK_STATUS = TRUE
  612. READ_DISABLED_CAP = TRUE
  613. READ_ENABLED_CAP = TRUE
  614. READ_STATUS = TRUE
  615. READ_LOCK_CAP = TRUE
  616. READ_LOCK_STATUS = TRUE
  617. FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
  618. FILE FV_IMAGE = 35E7406A-5842-4F2B-BC62-19022C12AF74 {
  619. SECTION FV_IMAGE = FvAdvancedPreMem
  620. }
  621. FILE FV_IMAGE = F5DCB34F-27EA-48AC-9406-C894F6D587CA {
  622. SECTION FV_IMAGE = FvAdvancedPostMem
  623. }
  624. FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
  625. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  626. SECTION FV_IMAGE = FvAdvancedLate
  627. }
  628. }
  629. ################################################################################
  630. #
  631. # Rules are use with the [FV] section's module INF type to define
  632. # how an FFS file is created for a given INF file. The following Rule are the default
  633. # rules for the different module type. User can add the customized rules to define the
  634. # content of the FFS file.
  635. #
  636. ################################################################################
  637. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf