OpenBoardPkg.fdf 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717
  1. ## @file
  2. # System 76 GalagoPro3 board flash file.
  3. #
  4. # Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. [Defines]
  10. !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
  11. ################################################################################
  12. #
  13. # FD Section
  14. # The [FD] Section is made up of the definition statements and a
  15. # description of what goes into the Flash Device Image. Each FD section
  16. # defines one flash "device" image. A flash device image may be one of
  17. # the following: Removable media bootable image (like a boot floppy
  18. # image,) an Option ROM image (that would be "flashed" into an add-in
  19. # card,) a System "Flash" image (that would be burned into a system's
  20. # flash) or an Update ("Capsule") image that will be used to update and
  21. # existing system flash.
  22. #
  23. ################################################################################
  24. [FD.GalagoPro3]
  25. #
  26. # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
  27. # assigned with PCD values. Instead, it uses the definitions for its variety, which
  28. # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
  29. #
  30. BaseAddress = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the FLASH Device.
  31. Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize #The size in bytes of the FLASH Device
  32. ErasePolarity = 1
  33. BlockSize = $(FLASH_BLOCK_SIZE)
  34. NumBlocks = $(FLASH_NUM_BLOCKS)
  35. DEFINE SIPKG_DXE_SMM_BIN = INF
  36. DEFINE SIPKG_PEI_BIN = INF
  37. # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
  38. # So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
  39. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
  40. SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  41. SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  42. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
  43. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
  44. SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  45. SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  46. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
  47. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
  48. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  49. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
  50. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
  51. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
  52. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
  53. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
  54. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
  55. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
  56. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
  57. ################################################################################
  58. #
  59. # Following are lists of FD Region layout which correspond to the locations of different
  60. # images within the flash device.
  61. #
  62. # Regions must be defined in ascending order and may not overlap.
  63. #
  64. # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
  65. # the pipe "|" character, followed by the size of the region, also in hex with the leading
  66. # "0x" characters. Like:
  67. # Offset|Size
  68. # PcdOffsetCName|PcdSizeCName
  69. # RegionType <FV, DATA, or FILE>
  70. # Fv Size can be adjusted
  71. #
  72. ################################################################################
  73. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  74. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  75. #NV_VARIABLE_STORE
  76. DATA = {
  77. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  78. # ZeroVector []
  79. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  80. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  81. # FileSystemGuid
  82. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  83. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  84. # FvLength: 0x40000
  85. 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  86. #Signature "_FVH" #Attributes
  87. 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
  88. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  89. #
  90. # Be careful on CheckSum field.
  91. #
  92. 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
  93. #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
  94. 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  95. #Blockmap[1]: End
  96. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  97. ## This is the VARIABLE_STORE_HEADER
  98. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  99. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
  100. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  101. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  102. !else
  103. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  104. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  105. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  106. !endif
  107. #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
  108. # This can speed up the Variable Dispatch a bit.
  109. 0xB8, 0xDF, 0x01, 0x00,
  110. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  111. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  112. }
  113. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  114. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  115. #NV_FTW_WORKING
  116. DATA = {
  117. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  118. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  119. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  120. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  121. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  122. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  123. # WriteQueueSize: UINT64
  124. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  125. }
  126. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  127. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  128. #NV_FTW_SPARE
  129. gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
  130. gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase|gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize
  131. #DEBUG_MESSAGE_AREA
  132. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  133. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  134. FV = FvAdvanced
  135. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  136. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  137. FV = FvSecurity
  138. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  139. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  140. FV = FvOsBoot
  141. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  142. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  143. FV = FvUefiBoot
  144. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  145. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  146. FV = FvPostMemory
  147. gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  148. gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  149. #Microcode
  150. FV = FvMicrocode
  151. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  152. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  153. # FSP_S Section
  154. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
  155. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  156. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  157. # FSP_M Section
  158. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
  159. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  160. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  161. # FSP_T Section
  162. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
  163. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  164. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  165. FV = FvPreMemory
  166. ################################################################################
  167. #
  168. # FV Section
  169. #
  170. # [FV] section is used to define what components or modules are placed within a flash
  171. # device file. This section also defines order the components and modules are positioned
  172. # within the image. The [FV] section consists of define statements, set statements and
  173. # module statements.
  174. #
  175. ################################################################################
  176. [FV.FvMicrocode]
  177. BlockSize = $(FLASH_BLOCK_SIZE)
  178. FvAlignment = 16
  179. ERASE_POLARITY = 1
  180. MEMORY_MAPPED = TRUE
  181. STICKY_WRITE = TRUE
  182. LOCK_CAP = TRUE
  183. LOCK_STATUS = FALSE
  184. WRITE_DISABLED_CAP = TRUE
  185. WRITE_ENABLED_CAP = TRUE
  186. WRITE_STATUS = TRUE
  187. WRITE_LOCK_CAP = TRUE
  188. WRITE_LOCK_STATUS = TRUE
  189. READ_DISABLED_CAP = TRUE
  190. READ_ENABLED_CAP = TRUE
  191. READ_STATUS = FALSE
  192. READ_LOCK_CAP = TRUE
  193. READ_LOCK_STATUS = TRUE
  194. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
  195. [FV.FvPreMemory]
  196. BlockSize = $(FLASH_BLOCK_SIZE)
  197. FvAlignment = 16
  198. ERASE_POLARITY = 1
  199. MEMORY_MAPPED = TRUE
  200. STICKY_WRITE = TRUE
  201. LOCK_CAP = TRUE
  202. LOCK_STATUS = TRUE
  203. WRITE_DISABLED_CAP = TRUE
  204. WRITE_ENABLED_CAP = TRUE
  205. WRITE_STATUS = TRUE
  206. WRITE_LOCK_CAP = TRUE
  207. WRITE_LOCK_STATUS = TRUE
  208. READ_DISABLED_CAP = TRUE
  209. READ_ENABLED_CAP = TRUE
  210. READ_STATUS = TRUE
  211. READ_LOCK_CAP = TRUE
  212. READ_LOCK_STATUS = TRUE
  213. FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
  214. INF UefiCpuPkg/SecCore/SecCore.inf
  215. INF MdeModulePkg/Core/Pei/PeiMain.inf
  216. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  217. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  218. INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  219. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  220. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  221. INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
  222. [FV.FvPostMemoryUncompact]
  223. BlockSize = $(FLASH_BLOCK_SIZE)
  224. FvAlignment = 16
  225. ERASE_POLARITY = 1
  226. MEMORY_MAPPED = TRUE
  227. STICKY_WRITE = TRUE
  228. LOCK_CAP = TRUE
  229. LOCK_STATUS = TRUE
  230. WRITE_DISABLED_CAP = TRUE
  231. WRITE_ENABLED_CAP = TRUE
  232. WRITE_STATUS = TRUE
  233. WRITE_LOCK_CAP = TRUE
  234. WRITE_LOCK_STATUS = TRUE
  235. READ_DISABLED_CAP = TRUE
  236. READ_ENABLED_CAP = TRUE
  237. READ_STATUS = TRUE
  238. READ_LOCK_CAP = TRUE
  239. READ_LOCK_STATUS = TRUE
  240. FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
  241. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  242. # Init Board Config PCD
  243. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  244. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  245. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  246. !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
  247. FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
  248. SECTION RAW = GalagoPro3/Gop/Vbt.bin
  249. SECTION UI = "Vbt"
  250. }
  251. FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
  252. SECTION RAW = MdeModulePkg/Logo/Logo.bmp
  253. }
  254. !endif # PcdPeiDisplayEnable
  255. [FV.FvPostMemory]
  256. BlockSize = $(FLASH_BLOCK_SIZE)
  257. FvAlignment = 16
  258. ERASE_POLARITY = 1
  259. MEMORY_MAPPED = TRUE
  260. STICKY_WRITE = TRUE
  261. LOCK_CAP = TRUE
  262. LOCK_STATUS = TRUE
  263. WRITE_DISABLED_CAP = TRUE
  264. WRITE_ENABLED_CAP = TRUE
  265. WRITE_STATUS = TRUE
  266. WRITE_LOCK_CAP = TRUE
  267. WRITE_LOCK_STATUS = TRUE
  268. READ_DISABLED_CAP = TRUE
  269. READ_ENABLED_CAP = TRUE
  270. READ_STATUS = TRUE
  271. READ_LOCK_CAP = TRUE
  272. READ_LOCK_STATUS = TRUE
  273. FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
  274. FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
  275. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  276. SECTION FV_IMAGE = FvPostMemoryUncompact
  277. }
  278. }
  279. [FV.FvUefiBootUncompact]
  280. BlockSize = $(FLASH_BLOCK_SIZE)
  281. FvAlignment = 16
  282. ERASE_POLARITY = 1
  283. MEMORY_MAPPED = TRUE
  284. STICKY_WRITE = TRUE
  285. LOCK_CAP = TRUE
  286. LOCK_STATUS = TRUE
  287. WRITE_DISABLED_CAP = TRUE
  288. WRITE_ENABLED_CAP = TRUE
  289. WRITE_STATUS = TRUE
  290. WRITE_LOCK_CAP = TRUE
  291. WRITE_LOCK_STATUS = TRUE
  292. READ_DISABLED_CAP = TRUE
  293. READ_ENABLED_CAP = TRUE
  294. READ_STATUS = TRUE
  295. READ_LOCK_CAP = TRUE
  296. READ_LOCK_STATUS = TRUE
  297. FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
  298. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  299. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  300. INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
  301. INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
  302. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  303. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  304. INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
  305. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  306. INF ShellPkg/Application/Shell/Shell.inf
  307. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  308. INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
  309. INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
  310. [FV.FvUefiBoot]
  311. BlockSize = $(FLASH_BLOCK_SIZE)
  312. FvAlignment = 16
  313. ERASE_POLARITY = 1
  314. MEMORY_MAPPED = TRUE
  315. STICKY_WRITE = TRUE
  316. LOCK_CAP = TRUE
  317. LOCK_STATUS = TRUE
  318. WRITE_DISABLED_CAP = TRUE
  319. WRITE_ENABLED_CAP = TRUE
  320. WRITE_STATUS = TRUE
  321. WRITE_LOCK_CAP = TRUE
  322. WRITE_LOCK_STATUS = TRUE
  323. READ_DISABLED_CAP = TRUE
  324. READ_ENABLED_CAP = TRUE
  325. READ_STATUS = TRUE
  326. READ_LOCK_CAP = TRUE
  327. READ_LOCK_STATUS = TRUE
  328. FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
  329. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  330. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  331. SECTION FV_IMAGE = FvUefiBootUncompact
  332. }
  333. }
  334. [FV.FvOsBootUncompact]
  335. BlockSize = $(FLASH_BLOCK_SIZE)
  336. FvAlignment = 16
  337. ERASE_POLARITY = 1
  338. MEMORY_MAPPED = TRUE
  339. STICKY_WRITE = TRUE
  340. LOCK_CAP = TRUE
  341. LOCK_STATUS = TRUE
  342. WRITE_DISABLED_CAP = TRUE
  343. WRITE_ENABLED_CAP = TRUE
  344. WRITE_STATUS = TRUE
  345. WRITE_LOCK_CAP = TRUE
  346. WRITE_LOCK_STATUS = TRUE
  347. READ_DISABLED_CAP = TRUE
  348. READ_ENABLED_CAP = TRUE
  349. READ_STATUS = TRUE
  350. READ_LOCK_CAP = TRUE
  351. READ_LOCK_STATUS = TRUE
  352. FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
  353. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  354. INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
  355. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  356. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
  357. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  358. INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  359. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  360. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  361. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  362. INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  363. !endif
  364. [FV.FvLateSilicon]
  365. BlockSize = $(FLASH_BLOCK_SIZE)
  366. FvAlignment = 16
  367. ERASE_POLARITY = 1
  368. MEMORY_MAPPED = TRUE
  369. STICKY_WRITE = TRUE
  370. LOCK_CAP = TRUE
  371. LOCK_STATUS = TRUE
  372. WRITE_DISABLED_CAP = TRUE
  373. WRITE_ENABLED_CAP = TRUE
  374. WRITE_STATUS = TRUE
  375. WRITE_LOCK_CAP = TRUE
  376. WRITE_LOCK_STATUS = TRUE
  377. READ_DISABLED_CAP = TRUE
  378. READ_ENABLED_CAP = TRUE
  379. READ_STATUS = TRUE
  380. READ_LOCK_CAP = TRUE
  381. READ_LOCK_STATUS = TRUE
  382. FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
  383. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  384. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf
  385. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
  386. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
  387. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
  388. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
  389. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
  390. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
  391. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
  392. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
  393. !endif
  394. [FV.FvOsBoot]
  395. BlockSize = $(FLASH_BLOCK_SIZE)
  396. FvAlignment = 16
  397. ERASE_POLARITY = 1
  398. MEMORY_MAPPED = TRUE
  399. STICKY_WRITE = TRUE
  400. LOCK_CAP = TRUE
  401. LOCK_STATUS = TRUE
  402. WRITE_DISABLED_CAP = TRUE
  403. WRITE_ENABLED_CAP = TRUE
  404. WRITE_STATUS = TRUE
  405. WRITE_LOCK_CAP = TRUE
  406. WRITE_LOCK_STATUS = TRUE
  407. READ_DISABLED_CAP = TRUE
  408. READ_ENABLED_CAP = TRUE
  409. READ_STATUS = TRUE
  410. READ_LOCK_CAP = TRUE
  411. READ_LOCK_STATUS = TRUE
  412. FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
  413. FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
  414. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  415. SECTION FV_IMAGE = FvOsBootUncompact
  416. }
  417. }
  418. FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
  419. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  420. SECTION FV_IMAGE = FvLateSilicon
  421. }
  422. }
  423. [FV.FvSecurityPreMemory]
  424. BlockSize = $(FLASH_BLOCK_SIZE)
  425. FvAlignment = 16 #FV alignment and FV attributes setting.
  426. ERASE_POLARITY = 1
  427. MEMORY_MAPPED = TRUE
  428. STICKY_WRITE = TRUE
  429. LOCK_CAP = TRUE
  430. LOCK_STATUS = TRUE
  431. WRITE_DISABLED_CAP = TRUE
  432. WRITE_ENABLED_CAP = TRUE
  433. WRITE_STATUS = TRUE
  434. WRITE_LOCK_CAP = TRUE
  435. WRITE_LOCK_STATUS = TRUE
  436. READ_DISABLED_CAP = TRUE
  437. READ_ENABLED_CAP = TRUE
  438. READ_STATUS = TRUE
  439. READ_LOCK_CAP = TRUE
  440. READ_LOCK_STATUS = TRUE
  441. FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
  442. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  443. INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  444. INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
  445. [FV.FvSecurityPostMemory]
  446. BlockSize = $(FLASH_BLOCK_SIZE)
  447. FvAlignment = 16 #FV alignment and FV attributes setting.
  448. ERASE_POLARITY = 1
  449. MEMORY_MAPPED = TRUE
  450. STICKY_WRITE = TRUE
  451. LOCK_CAP = TRUE
  452. LOCK_STATUS = TRUE
  453. WRITE_DISABLED_CAP = TRUE
  454. WRITE_ENABLED_CAP = TRUE
  455. WRITE_STATUS = TRUE
  456. WRITE_LOCK_CAP = TRUE
  457. WRITE_LOCK_STATUS = TRUE
  458. READ_DISABLED_CAP = TRUE
  459. READ_ENABLED_CAP = TRUE
  460. READ_STATUS = TRUE
  461. READ_LOCK_CAP = TRUE
  462. READ_LOCK_STATUS = TRUE
  463. FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
  464. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  465. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  466. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  467. !endif
  468. [FV.FvSecurityLate]
  469. BlockSize = $(FLASH_BLOCK_SIZE)
  470. FvAlignment = 16
  471. ERASE_POLARITY = 1
  472. MEMORY_MAPPED = TRUE
  473. STICKY_WRITE = TRUE
  474. LOCK_CAP = TRUE
  475. LOCK_STATUS = TRUE
  476. WRITE_DISABLED_CAP = TRUE
  477. WRITE_ENABLED_CAP = TRUE
  478. WRITE_STATUS = TRUE
  479. WRITE_LOCK_CAP = TRUE
  480. WRITE_LOCK_STATUS = TRUE
  481. READ_DISABLED_CAP = TRUE
  482. READ_ENABLED_CAP = TRUE
  483. READ_STATUS = TRUE
  484. READ_LOCK_CAP = TRUE
  485. READ_LOCK_STATUS = TRUE
  486. FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
  487. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  488. INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
  489. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  490. INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf
  491. !endif
  492. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  493. INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
  494. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  495. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  496. !endif
  497. !endif
  498. [FV.FvSecurity]
  499. BlockSize = $(FLASH_BLOCK_SIZE)
  500. FvAlignment = 16
  501. ERASE_POLARITY = 1
  502. MEMORY_MAPPED = TRUE
  503. STICKY_WRITE = TRUE
  504. LOCK_CAP = TRUE
  505. LOCK_STATUS = TRUE
  506. WRITE_DISABLED_CAP = TRUE
  507. WRITE_ENABLED_CAP = TRUE
  508. WRITE_STATUS = TRUE
  509. WRITE_LOCK_CAP = TRUE
  510. WRITE_LOCK_STATUS = TRUE
  511. READ_DISABLED_CAP = TRUE
  512. READ_ENABLED_CAP = TRUE
  513. READ_STATUS = TRUE
  514. READ_LOCK_CAP = TRUE
  515. READ_LOCK_STATUS = TRUE
  516. FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
  517. FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
  518. SECTION FV_IMAGE = FvSecurityPreMemory
  519. }
  520. FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
  521. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  522. SECTION FV_IMAGE = FvSecurityPostMemory
  523. }
  524. }
  525. FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
  526. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  527. SECTION FV_IMAGE = FvSecurityLate
  528. }
  529. }
  530. [FV.FvAdvancedPreMem]
  531. FvAlignment = 16
  532. ERASE_POLARITY = 1
  533. MEMORY_MAPPED = TRUE
  534. STICKY_WRITE = TRUE
  535. LOCK_CAP = TRUE
  536. LOCK_STATUS = TRUE
  537. WRITE_DISABLED_CAP = TRUE
  538. WRITE_ENABLED_CAP = TRUE
  539. WRITE_STATUS = TRUE
  540. WRITE_LOCK_CAP = TRUE
  541. WRITE_LOCK_STATUS = TRUE
  542. READ_DISABLED_CAP = TRUE
  543. READ_ENABLED_CAP = TRUE
  544. READ_STATUS = TRUE
  545. READ_LOCK_CAP = TRUE
  546. READ_LOCK_STATUS = TRUE
  547. FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
  548. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  549. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
  550. !endif
  551. [FV.FvAdvancedPostMem]
  552. FvAlignment = 16
  553. ERASE_POLARITY = 1
  554. MEMORY_MAPPED = TRUE
  555. STICKY_WRITE = TRUE
  556. LOCK_CAP = TRUE
  557. LOCK_STATUS = TRUE
  558. WRITE_DISABLED_CAP = TRUE
  559. WRITE_ENABLED_CAP = TRUE
  560. WRITE_STATUS = TRUE
  561. WRITE_LOCK_CAP = TRUE
  562. WRITE_LOCK_STATUS = TRUE
  563. READ_DISABLED_CAP = TRUE
  564. READ_ENABLED_CAP = TRUE
  565. READ_STATUS = TRUE
  566. READ_LOCK_CAP = TRUE
  567. READ_LOCK_STATUS = TRUE
  568. FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
  569. [FV.FvAdvancedLate]
  570. FvAlignment = 16
  571. ERASE_POLARITY = 1
  572. MEMORY_MAPPED = TRUE
  573. STICKY_WRITE = TRUE
  574. LOCK_CAP = TRUE
  575. LOCK_STATUS = TRUE
  576. WRITE_DISABLED_CAP = TRUE
  577. WRITE_ENABLED_CAP = TRUE
  578. WRITE_STATUS = TRUE
  579. WRITE_LOCK_CAP = TRUE
  580. WRITE_LOCK_STATUS = TRUE
  581. READ_DISABLED_CAP = TRUE
  582. READ_ENABLED_CAP = TRUE
  583. READ_STATUS = TRUE
  584. READ_LOCK_CAP = TRUE
  585. READ_LOCK_STATUS = TRUE
  586. FvNameGuid = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D
  587. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  588. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
  589. INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
  590. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  591. !endif
  592. [FV.FvAdvanced]
  593. BlockSize = $(FLASH_BLOCK_SIZE)
  594. FvAlignment = 16
  595. ERASE_POLARITY = 1
  596. MEMORY_MAPPED = TRUE
  597. STICKY_WRITE = TRUE
  598. LOCK_CAP = TRUE
  599. LOCK_STATUS = TRUE
  600. WRITE_DISABLED_CAP = TRUE
  601. WRITE_ENABLED_CAP = TRUE
  602. WRITE_STATUS = TRUE
  603. WRITE_LOCK_CAP = TRUE
  604. WRITE_LOCK_STATUS = TRUE
  605. READ_DISABLED_CAP = TRUE
  606. READ_ENABLED_CAP = TRUE
  607. READ_STATUS = TRUE
  608. READ_LOCK_CAP = TRUE
  609. READ_LOCK_STATUS = TRUE
  610. FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
  611. FILE FV_IMAGE = 35E7406A-5842-4F2B-BC62-19022C12AF74 {
  612. SECTION FV_IMAGE = FvAdvancedPreMem
  613. }
  614. FILE FV_IMAGE = F5DCB34F-27EA-48AC-9406-C894F6D587CA {
  615. SECTION FV_IMAGE = FvAdvancedPostMem
  616. }
  617. FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
  618. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  619. SECTION FV_IMAGE = FvAdvancedLate
  620. }
  621. }
  622. ################################################################################
  623. #
  624. # Rules are use with the [FV] section's module INF type to define
  625. # how an FFS file is created for a given INF file. The following Rule are the default
  626. # rules for the different module type. User can add the customized rules to define the
  627. # content of the FFS file.
  628. #
  629. ################################################################################
  630. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf