RTSMHelper.asm 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112
  1. //
  2. // Copyright (c) 2011-2013, ARM Limited. All rights reserved.
  3. //
  4. // SPDX-License-Identifier: BSD-2-Clause-Patent
  5. //
  6. //
  7. #include <Base.h>
  8. #include <Library/ArmLib.h>
  9. #include <Library/PcdLib.h>
  10. #include <Chipset/ArmCortexA9.h>
  11. #include <AutoGen.h>
  12. INCLUDE AsmMacroIoLib.inc
  13. EXPORT ArmPlatformPeiBootAction
  14. EXPORT ArmGetCpuCountPerCluster
  15. EXPORT ArmPlatformIsPrimaryCore
  16. EXPORT ArmPlatformGetPrimaryCoreMpId
  17. EXPORT ArmPlatformGetCorePosition
  18. AREA RTSMHelper, CODE, READONLY
  19. ArmPlatformPeiBootAction FUNCTION
  20. bx lr
  21. ENDFUNC
  22. // IN None
  23. // OUT r0 = SCU Base Address
  24. ArmGetScuBaseAddress FUNCTION
  25. // Read Configuration Base Address Register. ArmCBar cannot be called to get
  26. // the Configuration BAR as a stack is not necessary setup. The SCU is at the
  27. // offset 0x0000 from the Private Memory Region.
  28. mrc p15, 4, r0, c15, c0, 0
  29. bx lr
  30. ENDFUNC
  31. //UINTN
  32. //ArmPlatformGetPrimaryCoreMpId (
  33. // VOID
  34. // );
  35. ArmPlatformGetPrimaryCoreMpId FUNCTION
  36. mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)
  37. bx lr
  38. ENDFUNC
  39. // IN None
  40. // OUT r0 = number of cores present in the system
  41. ArmGetCpuCountPerCluster FUNCTION
  42. stmfd SP!, {r1-r2}
  43. // Read CP15 MIDR
  44. mrc p15, 0, r1, c0, c0, 0
  45. // Check if the CPU is A15
  46. mov r1, r1, LSR #4
  47. mov r0, #ARM_CPU_TYPE_MASK
  48. and r1, r1, r0
  49. mov r0, #ARM_CPU_TYPE_A15
  50. cmp r1, r0
  51. beq _Read_cp15_reg
  52. _CPU_is_not_A15
  53. mov r2, lr ; Save link register
  54. bl ArmGetScuBaseAddress ; Read SCU Base Address
  55. mov lr, r2 ; Restore link register val
  56. ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count
  57. b _Return
  58. _Read_cp15_reg
  59. mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count
  60. lsr r0, #24
  61. _Return
  62. and r0, r0, #3
  63. // Add '1' to the number of CPU on the Cluster
  64. add r0, r0, #1
  65. ldmfd SP!, {r1-r2}
  66. bx lr
  67. ENDFUNC
  68. //UINTN
  69. //ArmPlatformIsPrimaryCore (
  70. // IN UINTN MpId
  71. // );
  72. ArmPlatformIsPrimaryCore FUNCTION
  73. mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask)
  74. and r0, r0, r1
  75. mov32 r1, FixedPcdGet32(PcdArmPrimaryCore)
  76. ldr r1, [r1]
  77. cmp r0, r1
  78. moveq r0, #1
  79. movne r0, #0
  80. bx lr
  81. ENDFUNC
  82. //UINTN
  83. //ArmPlatformGetCorePosition (
  84. // IN UINTN MpId
  85. // );
  86. ArmPlatformGetCorePosition FUNCTION
  87. and r1, r0, #ARM_CORE_MASK
  88. and r0, r0, #ARM_CLUSTER_MASK
  89. add r0, r1, r0, LSR #7
  90. bx lr
  91. ENDFUNC
  92. END