GlobalNvs.asl 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115
  1. /** @file
  2. ACPI DSDT table
  3. Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. // Define a Global region of ACPI NVS Region that may be used for any
  7. // type of implementation. The starting offset and size will be fixed
  8. // up by the System BIOS during POST. Note that the Size must be a word
  9. // in size to be fixed up correctly.
  10. OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
  11. Field(GNVS,AnyAcc,Lock,Preserve)
  12. {
  13. //
  14. // Miscellaneous Dynamic Registers:
  15. //
  16. Offset(0), OSYS, 16, // Offset(0), Operating System
  17. Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SMI via I/O Trap)
  18. Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value
  19. Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode = 1)
  20. //
  21. // Thermal Policy Registers:
  22. //
  23. Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable
  24. Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call
  25. //
  26. // CPU Identification Registers:
  27. //
  28. Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC Enabled = 1)
  29. Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads
  30. //
  31. // PCIe Hot Plug
  32. //
  33. Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control
  34. Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value
  35. //
  36. // Global Variables
  37. //
  38. Offset(14), DSEN, 8, // Offset(14), _DOS Display Support Flag.
  39. Offset(15), GPIC, 8, // Offset(15), Global IOAPIC/8259 Interrupt Mode Flag.
  40. Offset(16), L01C, 8, // Offset(16), Global L01 Counter.
  41. Offset(17), LTR1, 8, // Offset(17), Latency Tolerance Reporting Enable
  42. Offset(18), LTR2, 8, // Offset(18), Latency Tolerance Reporting Enable
  43. Offset(19), LTR3, 8, // Offset(19), Latency Tolerance Reporting Enable
  44. Offset(20), LTR4, 8, // Offset(20), Latency Tolerance Reporting Enable
  45. Offset(21), LTR5, 8, // Offset(21), Latency Tolerance Reporting Enable
  46. Offset(22), LTR6, 8, // Offset(22), Latency Tolerance Reporting Enable
  47. Offset(23), LTR7, 8, // Offset(23), Latency Tolerance Reporting Enable
  48. Offset(24), LTR8, 8, // Offset(24), Latency Tolerance Reporting Enable
  49. Offset(25), LTR9, 8, // Offset(25), Latency Tolerance Reporting Enable
  50. Offset(26), LTRA, 8, // Offset(26), Latency Tolerance Reporting Enable
  51. Offset(27), LTRB, 8, // Offset(27), Latency Tolerance Reporting Enable
  52. Offset(28), LTRC, 8, // Offset(28), Latency Tolerance Reporting Enable
  53. Offset(29), LTRD, 8, // Offset(29), Latency Tolerance Reporting Enable
  54. Offset(30), LTRE, 8, // Offset(30), Latency Tolerance Reporting Enable
  55. Offset(31), LTRF, 8, // Offset(31), Latency Tolerance Reporting Enable
  56. Offset(32), LTRG, 8, // Offset(32), Latency Tolerance Reporting Enable
  57. Offset(33), LTRH, 8, // Offset(33), Latency Tolerance Reporting Enable
  58. Offset(34), LTRI, 8, // Offset(34), Latency Tolerance Reporting Enable
  59. Offset(35), LTRJ, 8, // Offset(35), Latency Tolerance Reporting Enable
  60. Offset(36), LTRK, 8, // Offset(36), Latency Tolerance Reporting Enable
  61. Offset(37), LTRL, 8, // Offset(37), Latency Tolerance Reporting Enable
  62. Offset(38), LTRM, 8, // Offset(38), Latency Tolerance Reporting Enable
  63. Offset(39), LTRN, 8, // Offset(39), Latency Tolerance Reporting Enable
  64. Offset(40), LTRO, 8, // Offset(40), Latency Tolerance Reporting Enable
  65. Offset(41), OBF1, 8, // Offset(41), Optimized Buffer Flush and Fill
  66. Offset(42), OBF2, 8, // Offset(42), Optimized Buffer Flush and Fill
  67. Offset(43), OBF3, 8, // Offset(43), Optimized Buffer Flush and Fill
  68. Offset(44), OBF4, 8, // Offset(44), Optimized Buffer Flush and Fill
  69. Offset(45), OBF5, 8, // Offset(45), Optimized Buffer Flush and Fill
  70. Offset(46), OBF6, 8, // Offset(46), Optimized Buffer Flush and Fill
  71. Offset(47), OBF7, 8, // Offset(47), Optimized Buffer Flush and Fill
  72. Offset(48), OBF8, 8, // Offset(48), Optimized Buffer Flush and Fill
  73. Offset(49), OBF9, 8, // Offset(49), Optimized Buffer Flush and Fill
  74. Offset(50), OBFA, 8, // Offset(50), Optimized Buffer Flush and Fill
  75. Offset(51), OBFB, 8, // Offset(51), Optimized Buffer Flush and Fill
  76. Offset(52), OBFC, 8, // Offset(52), Optimized Buffer Flush and Fill
  77. Offset(53), OBFD, 8, // Offset(53), Optimized Buffer Flush and Fill
  78. Offset(54), OBFE, 8, // Offset(54), Optimized Buffer Flush and Fill
  79. Offset(55), OBFF, 8, // Offset(55), Optimized Buffer Flush and Fill
  80. Offset(56), OBFG, 8, // Offset(56), Optimized Buffer Flush and Fill
  81. Offset(57), OBFH, 8, // Offset(57), Optimized Buffer Flush and Fill
  82. Offset(58), OBFI, 8, // Offset(58), Optimized Buffer Flush and Fill
  83. Offset(59), OBFJ, 8, // Offset(59), Optimized Buffer Flush and Fill
  84. Offset(60), OBFK, 8, // Offset(60), Optimized Buffer Flush and Fill
  85. Offset(61), OBFL, 8, // Offset(61), Optimized Buffer Flush and Fill
  86. Offset(62), OBFM, 8, // Offset(62), Optimized Buffer Flush and Fill
  87. Offset(63), OBFN, 8, // Offset(63), Optimized Buffer Flush and Fill
  88. Offset(64), OBFO, 8, // Offset(64), Optimized Buffer Flush and Fill
  89. Offset(65), RTD3, 8, // Offset(65), Runtime D3 support.
  90. Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable
  91. Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify Sleep State Change
  92. Offset(68), PSCP, 8, // Offset(68), P-state Capping
  93. Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable
  94. Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse Enable
  95. //
  96. // Driver Mode
  97. //
  98. Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ
  99. Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering CS
  100. Offset(76), PLVL, 16, // Offset(76), PL1 limit value
  101. Offset(78), PB1E, 8, // Offset(78), 10sec Power button support
  102. Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr
  103. Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support
  104. Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug
  105. Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port selector
  106. Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port selector
  107. Offset(84), BDID, 8, // Offset(84), Board ID
  108. }