MiscProcessorCacheFunction.c 4.9 KB

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  1. /*++
  2. Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. MiscProcessorCacheFunction.c
  6. Abstract:
  7. BIOS processor cache details.
  8. Misc. subclass type 7.
  9. SMBIOS type 7.
  10. --*/
  11. #include "CommonHeader.h"
  12. #include "MiscSubclassDriver.h"
  13. #include <Register/Cpuid.h>
  14. MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache)
  15. {
  16. EFI_SMBIOS_HANDLE SmbiosHandle;
  17. SMBIOS_TABLE_TYPE7 *SmbiosRecord;
  18. EFI_CACHE_SRAM_TYPE_DATA CacheSramType;
  19. CHAR16 *SocketDesignation;
  20. CHAR8 *OptionalStrStart;
  21. UINTN SocketStrLen;
  22. STRING_REF TokenToGet;
  23. UINT32 SubIndex;
  24. CPUID_CACHE_PARAMS_EAX CacheParamsEax;
  25. CPUID_CACHE_PARAMS_EBX CacheParamsEbx;
  26. UINT32 RegisterEcx;
  27. CPUID_CACHE_PARAMS_EDX CacheParamsEdx;
  28. UINT8 SystemCacheType;
  29. UINTN Size;
  30. //
  31. // Memory Device Locator
  32. //
  33. TokenToGet = STRING_TOKEN (STR_SOCKET_DESIGNATION);
  34. SocketDesignation = SmbiosMiscGetString (TokenToGet);
  35. SocketStrLen = StrLen(SocketDesignation);
  36. if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {
  37. return EFI_UNSUPPORTED;
  38. }
  39. //
  40. // Retrieve cache level information using CPUID
  41. //
  42. for (SubIndex = 0; ; SubIndex++) {
  43. AsmCpuidEx (
  44. CPUID_CACHE_PARAMS,
  45. SubIndex,
  46. &CacheParamsEax.Uint32,
  47. &CacheParamsEbx.Uint32,
  48. &RegisterEcx,
  49. &CacheParamsEdx.Uint32
  50. );
  51. //
  52. // Terminate loop when CacheType is CPUID_CACHE_PARAMS_CACHE_TYPE_NULL
  53. //
  54. if (CacheParamsEax.Bits.CacheType == CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
  55. break;
  56. }
  57. //
  58. // Allocate and zero SMBIOS TYPE 7 Record
  59. //
  60. SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);
  61. ASSERT (SmbiosRecord != NULL);
  62. //
  63. // Compute cache size in bytes
  64. //
  65. Size = (CacheParamsEbx.Bits.Ways + 1) *
  66. (CacheParamsEbx.Bits.LinePartitions + 1) *
  67. (CacheParamsEbx.Bits.LineSize + 1) *
  68. (RegisterEcx + 1);
  69. DEBUG ((DEBUG_INFO, "MiscProcessorCache(): Cache Type = %d Cache Level = %d Size = %x\n", CacheParamsEax.Bits.CacheType, CacheParamsEax.Bits.CacheLevel, Size));
  70. //
  71. // Determine SMBIOS SystemCacheType
  72. //
  73. switch (CacheParamsEax.Bits.CacheType) {
  74. case 1:
  75. SystemCacheType = CacheTypeData;
  76. break;
  77. case 2:
  78. SystemCacheType = CacheTypeInstruction;
  79. break;
  80. case 3:
  81. SystemCacheType = CacheTypeUnified;
  82. break;
  83. default:
  84. SystemCacheType = CacheTypeUnknown;
  85. }
  86. //
  87. // Update cache sizes in KB
  88. //
  89. switch (CacheParamsEax.Bits.CacheLevel) {
  90. case 1:
  91. SmbiosRecord->InstalledSize = (UINT16)(Size >> 10);
  92. SmbiosRecord->MaximumCacheSize = SmbiosRecord->InstalledSize;
  93. SmbiosRecord->SystemCacheType = SystemCacheType;
  94. SmbiosRecord->Associativity = CacheAssociativity8Way;
  95. SmbiosRecord->CacheConfiguration = 0x0180;
  96. break;
  97. case 2:
  98. SmbiosRecord->InstalledSize = (UINT16)(Size >> 10);
  99. SmbiosRecord->MaximumCacheSize = SmbiosRecord->InstalledSize;
  100. SmbiosRecord->SystemCacheType = SystemCacheType;
  101. SmbiosRecord->Associativity = CacheAssociativity16Way;
  102. SmbiosRecord->CacheConfiguration = 0x0281;
  103. //
  104. //VLV2 incorporates two SLM modules (quad cores) in the SoC.
  105. // 2 cores share BIU/L2 cache
  106. //
  107. SmbiosRecord->InstalledSize = SmbiosRecord->InstalledSize / 2;
  108. SmbiosRecord->MaximumCacheSize = SmbiosRecord->InstalledSize;
  109. break;
  110. default:
  111. DEBUG ((DEBUG_ERROR, "MiscProcessorCache(): Unexpected cache level %d\n", CacheParamsEax.Bits.CacheLevel));
  112. break;
  113. }
  114. //
  115. //Filling SMBIOS type 7 information for different cache levels.
  116. //
  117. SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
  118. SmbiosRecord->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);
  119. SmbiosRecord->Hdr.Handle = 0;
  120. SmbiosRecord->SocketDesignation = 0x01;
  121. SmbiosRecord->CacheSpeed = 0;
  122. ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));
  123. CacheSramType.Synchronous = 1;
  124. CopyMem(&SmbiosRecord->SupportedSRAMType, &CacheSramType, 2);
  125. CopyMem(&SmbiosRecord->CurrentSRAMType, &CacheSramType, 2);
  126. SmbiosRecord->ErrorCorrectionType = EfiCacheErrorSingleBit;
  127. //
  128. // Adding SMBIOS type 7 records to SMBIOS table.
  129. //
  130. SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
  131. OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
  132. UnicodeStrToAsciiStrS (SocketDesignation, OptionalStrStart, + 7 + 1 + 1);
  133. Smbios->Add(
  134. Smbios,
  135. NULL,
  136. &SmbiosHandle,
  137. (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
  138. );
  139. }
  140. return EFI_SUCCESS;
  141. }