PcieCore.h 18 KB

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  1. /** @file
  2. Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef AC01_PCIE_CORE_H_
  6. #define AC01_PCIE_CORE_H_
  7. #define BUS_SHIFT 20
  8. #define DEV_SHIFT 15
  9. #define GET_LOW_8_BITS(x) ((x) & 0xFF)
  10. #define GET_HIGH_8_BITS(x) (((x) >> 8) & 0xFF)
  11. #define GET_LOW_16_BITS(x) ((x) & 0xFFFF)
  12. #define GET_HIGH_16_BITS(x) (((x) >> 16) & 0xFFFF)
  13. #define GET_CAPABILITY_PTR(x) (GET_LOW_16_BITS (x) >> 8)
  14. #define GET_EXT_CAPABILITY_PTR(x) (GET_HIGH_16_BITS (x) >> 4)
  15. #define WORD_ALIGN_MASK 0x3
  16. #define MAX_REINIT 3 // Number of soft reset retry
  17. #define SLOT_POWER_LIMIT_75W 75 // Watt
  18. #define LINK_CHECK_SUCCESS 0
  19. #define LINK_CHECK_FAILED -1
  20. #define LINK_CHECK_WRONG_PARAMETER 1
  21. #define AMPERE_PCIE_VENDOR_ID 0x1DEF
  22. #define AC01_HOST_BRIDGE_DEVICE_ID_RCA 0xE100
  23. #define AC01_HOST_BRIDGE_DEVICE_ID_RCB 0xE110
  24. #define AC01_PCIE_BRIDGE_DEVICE_ID_RCA 0xE101
  25. #define AC01_PCIE_BRIDGE_DEVICE_ID_RCB 0xE111
  26. #define MEMRDY_TIMEOUT 10 // 10 us
  27. #define PIPE_CLOCK_TIMEOUT 20000 // 20,000 us
  28. #define LTSSM_TRANSITION_TIMEOUT 100000 // 100 ms in total
  29. #define EP_LINKUP_TIMEOUT (10 * 1000) // 10ms
  30. #define EP_LINKUP_EXTRA_TIMEOUT (500 * 1000) // 500ms
  31. #define LINK_WAIT_INTERVAL_US 50
  32. #define PFA_MODE_ENABLE 0
  33. #define PFA_MODE_CLEAR 1
  34. #define PFA_MODE_READ 2
  35. //
  36. // Host Bridge registers
  37. //
  38. #define AC01_HOST_BRIDGE_RCA_DEV_MAP_REG 0x0
  39. #define AC01_HOST_BRIDGE_RCB_DEV_MAP_REG 0x4
  40. #define AC01_HOST_BRIDGE_VENDOR_DEVICE_ID_REG 0x10
  41. // AC01_HOST_BRIDGE_RCA_DEV_MAP_REG
  42. #define RCA_DEV_MAP_SET(dst, src) (((dst) & ~0x7) | (((UINT32) (src)) & 0x7))
  43. #define RCA_DEV_MAP_GET(val) ((val) & 0x7)
  44. // AC01_HOST_BRIDGE_RCB_DEV_MAP_REG
  45. #define RCB_DEV_MAP_LOW_SET(dst, src) (((dst) & ~0x7) | (((UINT32) (src)) & 0x7))
  46. #define RCB_DEV_MAP_LOW_GET(val) ((val) & 0x7)
  47. #define RCB_DEV_MAP_HIGH_SET(dst, src) (((dst) & ~0x70) | (((UINT32) (src) << 4) & 0x70))
  48. #define RCB_DEV_MAP_HIGH_GET(val) (((val) & 0x7) >> 4)
  49. // AC01_HOST_BRIDGE_VENDOR_DEVICE_ID_REG
  50. #define VENDOR_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
  51. #define VENDOR_ID_GET(val) ((val) & 0xFFFF)
  52. #define DEVICE_ID_SET(dst, src) (((dst) & ~0xFFFF0000) | (((UINT32) (src) << 16) & 0xFFFF0000))
  53. #define DEVICE_ID_GET(val) (((val) & 0xFFFF0000) >> 16)
  54. //
  55. // PCIe core registers
  56. //
  57. #define AC01_PCIE_CORE_LINK_CTRL_REG 0x0
  58. #define AC01_PCIE_CORE_LINK_STAT_REG 0x4
  59. #define AC01_PCIE_CORE_IRQ_SEL_REG 0xC
  60. #define AC01_PCIE_CORE_HOT_PLUG_STAT_REG 0x28
  61. #define AC01_PCIE_CORE_IRQ_ENABLE_REG 0x30
  62. #define AC01_PCIE_CORE_IRQ_EVENT_STAT_REG 0x38
  63. #define AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG 0x3C
  64. #define AC01_PCIE_CORE_BUS_CONTROL_REG 0x40
  65. #define AC01_PCIE_CORE_RESET_REG 0xC000
  66. #define AC01_PCIE_CORE_CLOCK_REG 0xC004
  67. #define AC01_PCIE_CORE_MEM_READY_REG 0xC104
  68. #define AC01_PCIE_CORE_RAM_SHUTDOWN_REG 0xC10C
  69. // AC01_PCIE_CORE_LINK_CTRL_REG
  70. #define LTSSMENB_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  71. #define LTSSMENB_GET(dst) ((dst) & (BIT0))
  72. #define HOLD_LINK_TRAINING 0
  73. #define START_LINK_TRAINING 1
  74. #define DEVICETYPE_SET(dst, src) (((dst) & ~0xF0) | (((UINT32) (src) << 4) & 0xF0))
  75. #define DEVICETYPE_GET(val) (((val) & 0xF0) >> 4)
  76. // AC01_PCIE_CORE_LINK_STAT_REG
  77. #define PHY_STATUS_MASK (1 << 2)
  78. #define SMLH_LTSSM_STATE_MASK 0x3F00
  79. #define SMLH_LTSSM_STATE_GET(val) ((val & SMLH_LTSSM_STATE_MASK) >> 8)
  80. #define LTSSM_STATE_L0 0x11
  81. #define RDLH_SMLH_LINKUP_STATUS_GET(val) (val & 0x3)
  82. #define PHY_STATUS_MASK_BIT 0x04
  83. #define SMLH_LINK_UP_MASK_BIT 0x02
  84. #define RDLH_LINK_UP_MASK_BIT 0x01
  85. // AC01_PCIE_CORE_IRQ_SEL_REG
  86. #define AER_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  87. #define PME_SET(dst, src) (((dst) & ~0x2) | (((UINT32) (src) << 1) & 0x2))
  88. #define LINKAUTOBW_SET(dst, src) (((dst) & ~0x4) | (((UINT32) (src) << 2) & 0x4))
  89. #define BWMGMT_SET(dst, src) (((dst) & ~0x8) | (((UINT32) (src) << 3) & 0x8))
  90. #define EQRQST_SET(dst, src) (((dst) & ~0x10) | (((UINT32) (src) << 4) & 0x10))
  91. #define INTPIN_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
  92. #define IRQ_INT_A 0x01
  93. // AC01_PCIE_CORE_HOT_PLUG_STAT_REG
  94. #define PWR_IND_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  95. #define ATTEN_IND_SET(dst, src) (((dst) & ~0x2) | (((UINT32) (src) << 1) & 0x2))
  96. #define PWR_CTRL_SET(dst, src) (((dst) & ~0x4) | (((UINT32) (src) << 2) & 0x4))
  97. #define EML_CTRL_SET(dst, src) (((dst) & ~0x8) | (((UINT32) (src) << 3) & 0x8))
  98. // AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG
  99. #define LINKUP_MASK 0x1
  100. // AC01_PCIE_CORE_BUS_CONTROL_REG
  101. #define BUS_CTL_CFG_UR_MASK 0x8
  102. // AC01_PCIE_CORE_RESET_REG
  103. #define DWC_PCIE_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  104. #define RESET_MASK 0x1
  105. #define ASSERT_RESET 0x1
  106. // AC01_PCIE_CORE_CLOCK_REG
  107. #define AXIPIPE_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  108. // AC01_PCIE_CORE_MEM_READY_REG
  109. #define MEMORY_READY 0x1
  110. // AC01_PCIE_CORE_RAM_SHUTDOWN_REG
  111. #define SD_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  112. //
  113. // AC01 PCIe Type 1 configuration registers
  114. //
  115. #define TYPE1_DEV_ID_VEND_ID_REG 0
  116. #define TYPE1_CLASS_CODE_REV_ID_REG 0x8
  117. #define TYPE1_CAP_PTR_REG 0x34
  118. #define SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG 0x18
  119. #define BRIDGE_CTRL_INT_PIN_INT_LINE_REG 0x3C
  120. #define PCIE_CAPABILITY_BASE 0x70
  121. #define EXT_CAPABILITY_START_BASE 0x100
  122. #define AER_CAPABILITY_BASE 0x100
  123. // TYPE1_DEV_ID_VEND_ID_REG
  124. #define VENDOR_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
  125. #define DEVICE_ID_SET(dst, src) (((dst) & ~0xFFFF0000) | (((UINT32) (src) << 16) & 0xFFFF0000))
  126. // TYPE1_CLASS_CODE_REV_ID_REG
  127. #define BASE_CLASS_CODE_SET(dst, src) (((dst) & ~0xFF000000) | (((UINT32) (src) << 24) & 0xFF000000))
  128. #define DEFAULT_BASE_CLASS_CODE 6
  129. #define SUB_CLASS_CODE_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
  130. #define DEFAULT_SUB_CLASS_CODE 4
  131. #define PROGRAM_INTERFACE_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
  132. #define REVISION_ID_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
  133. #define DEFAULT_REVISION_ID 4
  134. // SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG
  135. #define SUB_BUS_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
  136. #define DEFAULT_SUB_BUS 0xFF
  137. #define SEC_BUS_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
  138. #define PRIM_BUS_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
  139. #define DEFAULT_PRIM_BUS 0x00
  140. // BRIDGE_CTRL_INT_PIN_INT_LINE_REG
  141. #define INT_PIN_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
  142. //
  143. // PCI Express Capability
  144. //
  145. #define PCIE_CAPABILITY_ID 0x10
  146. #define LINK_CAPABILITIES_REG 0xC
  147. #define LINK_CONTROL_LINK_STATUS_REG 0x10
  148. #define SLOT_CAPABILITIES_REG 0x14
  149. #define DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x28
  150. #define LINK_CAPABILITIES2_REG 0x2C
  151. #define LINK_CONTROL2_LINK_STATUS2_REG 0x30
  152. // LINK_CAPABILITIES_REG
  153. #define CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SET(dst, src) (((dst) & ~0xC00) | (((UINT32)(src) << 10) & 0xC00))
  154. #define NO_ASPM_SUPPORTED 0x0
  155. #define L0S_SUPPORTED 0x1
  156. #define L1_SUPPORTED 0x2
  157. #define L0S_L1_SUPPORTED 0x3
  158. #define CAP_MAX_LINK_WIDTH_GET(val) ((val & 0x3F0) >> 4)
  159. #define CAP_MAX_LINK_WIDTH_SET(dst, src) (((dst) & ~0x3F0) | (((UINT32) (src) << 4) & 0x3F0))
  160. #define CAP_MAX_LINK_WIDTH_X1 0x1
  161. #define CAP_MAX_LINK_WIDTH_X2 0x2
  162. #define CAP_MAX_LINK_WIDTH_X4 0x4
  163. #define CAP_MAX_LINK_WIDTH_X8 0x8
  164. #define CAP_MAX_LINK_WIDTH_X16 0x10
  165. #define CAP_MAX_LINK_SPEED_GET(val) ((val & 0xF))
  166. #define CAP_MAX_LINK_SPEED_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
  167. #define MAX_LINK_SPEED_25 0x1
  168. #define MAX_LINK_SPEED_50 0x2
  169. #define MAX_LINK_SPEED_80 0x3
  170. #define MAX_LINK_SPEED_160 0x4
  171. #define MAX_LINK_SPEED_320 0x5
  172. // LINK_CONTROL_LINK_STATUS_REG
  173. #define CAP_DLL_ACTIVE_GET(val) ((val & 0x20000000) >> 29)
  174. #define CAP_SLOT_CLK_CONFIG_SET(dst, src) (((dst) & ~0x10000000) | (((UINT32) (src) << 28) & 0x10000000))
  175. #define CAP_NEGO_LINK_WIDTH_GET(val) ((val & 0x3F00000) >> 20)
  176. #define CAP_LINK_SPEED_GET(val) ((val & 0xF0000) >> 16)
  177. #define CAP_LINK_SPEED_SET(dst, src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
  178. #define CAP_LINK_SPEED_TO_VECTOR(val) (1 << ((val) - 1))
  179. #define CAP_EN_CLK_POWER_MAN_GET(val) ((val & 0x100) >> 8)
  180. #define CAP_EN_CLK_POWER_MAN_SET(dst, src) (((dst) & ~0x100) | (((UINT32) (src) << 8) & 0x100))
  181. #define CAP_COMMON_CLK_SET(dst, src) (((dst) & ~0x40) | (((UINT32) (src) << 6) & 0x40))
  182. #define CAP_RETRAIN_LINK_SET(dst, src) (((dst) & ~0x20) | (((UINT32) (src) << 5) & 0x20))
  183. #define CAP_LINK_TRAINING_GET(val) ((val & 0x8000000) >> 27)
  184. #define CAP_LINK_DISABLE_SET(dst, src) (((dst) & ~0x10) | (((UINT32)(src) << 4) & 0x10))
  185. // SLOT_CAPABILITIES_REG
  186. #define SLOT_HPC_SET(dst, src) (((dst) & ~0x40) | (((UINT32) (src) << 6) & 0x40))
  187. #define SLOT_CAP_SLOT_POWER_LIMIT_VALUE_SET(dst, src) \
  188. (((dst) & ~0x7F80) | (((UINT32)(src) << 7) & 0x7F80))
  189. // DEVICE_CONTROL2_DEVICE_STATUS2_REG
  190. #define CAP_CPL_TIMEOUT_VALUE_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
  191. // LINK_CONTROL2_LINK_STATUS2_REG
  192. #define CAP_TARGET_LINK_SPEED_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
  193. //
  194. // Advanced Error Reporting Capability
  195. //
  196. #define AER_CAPABILITY_ID 0x0001
  197. #define UNCORR_ERR_STATUS_OFF 0x04
  198. #define UNCORR_ERR_MASK_OFF 0x08
  199. // UNCORR_ERR_MASK_OFF
  200. #define CMPLT_TIMEOUT_ERR_MASK_SET(dst, src) (((dst) & ~0x4000) | (((UINT32) (src) << 14) & 0x4000))
  201. #define SDES_ERR_MASK_SET(dst, src) (((dst) & ~0x20) | (((UINT32)(src) << 5) & 0x20))
  202. //
  203. // Vendor specific RAS D.E.S Capability
  204. //
  205. #define RAS_DES_CAPABILITY_ID 0x000B
  206. #define EVENT_COUNTER_CONTROL_REG 0x08
  207. #define EVENT_COUNTER_DATA_REG 0x0C
  208. // EVENT_COUNTER_CONTROL_REG
  209. #define ECCR_GROUP_EVENT_SEL_SET(dst, src) (((dst) & ~0xFFF0000) | (((UINT32)(src) << 16) & 0xFFF0000))
  210. #define ECCR_GROUP_SEL_SET(dst, src) (((dst) & ~0xF000000) | (((UINT32)(src) << 24) & 0xF000000))
  211. #define ECCR_EVENT_SEL_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32)(src) << 16) & 0xFF0000))
  212. #define ECCR_LANE_SEL_SET(dst, src) (((dst) & ~0xF00) | (((UINT32)(src) << 8) & 0xF00))
  213. #define ECCR_EVENT_COUNTER_ENABLE_SET(dst, src) (((dst) & ~0x1C) | (((UINT32)(src) << 2) & 0x1C))
  214. #define EVENT_COUNTER_ENABLE_NO_CHANGE 0x00
  215. #define EVENT_COUNTER_ENABLE_ALL_ON 0x07
  216. #define ECCR_EVENT_COUNTER_CLEAR_SET(dst, src) (((dst) & ~0x3) | (((UINT32)(src)) & 0x3))
  217. #define EVENT_COUNTER_CLEAR_NO_CHANGE 0x00
  218. #define EVENT_COUNTER_CLEAR_ALL_CLEAR 0x03
  219. //
  220. // Secondary PCI Express Capability
  221. //
  222. #define SPCIE_CAPABILITY_ID 0x0019
  223. #define SPCIE_CAP_OFF_0C_REG 0x0C
  224. // SPCIE_CAP_OFF_0C_REG
  225. #define DSP_TX_PRESET0_SET(dst,src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
  226. #define DSP_TX_PRESET1_SET(dst,src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
  227. #define DEFAULT_GEN3_PRESET 0x05
  228. //
  229. // Physical Layer 16.0 GT/s Extended Capability
  230. //
  231. #define PL16G_CAPABILITY_ID 0x0026
  232. #define PL16G_STATUS_REG 0x0C
  233. #define PL16G_CAP_OFF_20H_REG 0x20
  234. // PL16G_STATUS_REG
  235. #define PL16G_STATUS_EQ_CPL_GET(val) (val & 0x1)
  236. #define PL16G_STATUS_EQ_CPL_P1_GET(val) ((val & 0x2) >> 1)
  237. #define PL16G_STATUS_EQ_CPL_P2_GET(val) ((val & 0x4) >> 2)
  238. #define PL16G_STATUS_EQ_CPL_P3_GET(val) ((val & 0x8) >> 3)
  239. // PL16G_CAP_OFF_20H_REG
  240. #define DSP_16G_TX_PRESET0_SET(dst,src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
  241. #define DSP_16G_TX_PRESET1_SET(dst,src) (((dst) & ~0xF00) | (((UINT32) (src) << 8) & 0xF00))
  242. #define DSP_16G_TX_PRESET2_SET(dst,src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
  243. #define DSP_16G_TX_PRESET3_SET(dst,src) (((dst) & ~0xF000000) | (((UINT32) (src) << 24) & 0xF000000))
  244. #define DSP_16G_RXTX_PRESET0_SET(dst,src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
  245. #define DSP_16G_RXTX_PRESET1_SET(dst,src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
  246. #define DSP_16G_RXTX_PRESET2_SET(dst,src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
  247. #define DSP_16G_RXTX_PRESET3_SET(dst,src) (((dst) & ~0xFF000000) | (((UINT32) (src) << 24) & 0xFF000000))
  248. #define DEFAULT_GEN4_PRESET 0x57
  249. //
  250. // Port Logic
  251. //
  252. #define PORT_LINK_CTRL_OFF 0x710
  253. #define FILTER_MASK_2_OFF 0x720
  254. #define GEN2_CTRL_OFF 0x80C
  255. #define GEN3_RELATED_OFF 0x890
  256. #define GEN3_EQ_CONTROL_OFF 0x8A8
  257. #define MISC_CONTROL_1_OFF 0x8BC
  258. #define AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x8D0
  259. #define AMBA_LINK_TIMEOUT_OFF 0x8D4
  260. #define AMBA_ORDERING_CTRL_OFF 0x8D8
  261. #define DTIM_CTRL0_OFF 0xAB0
  262. #define AUX_CLK_FREQ_OFF 0xB40
  263. #define CCIX_CTRL_OFF 0xC20
  264. // PORT_LINK_CTRL_OFF
  265. #define LINK_CAPABLE_SET(dst, src) (((dst) & ~0x3F0000) | (((UINT32) (src) << 16) & 0x3F0000))
  266. #define LINK_CAPABLE_X1 0x1
  267. #define LINK_CAPABLE_X2 0x3
  268. #define LINK_CAPABLE_X4 0x7
  269. #define LINK_CAPABLE_X8 0xF
  270. #define LINK_CAPABLE_X16 0x1F
  271. #define LINK_CAPABLE_X32 0x3F
  272. #define FAST_LINK_MODE_SET(dst, src) (((dst) & ~0x80) | (((UINT32) (src) << 7) & 0x80))
  273. // FILTER_MASK_2_OFF
  274. #define CX_FLT_MASK_VENMSG0_DROP_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  275. #define CX_FLT_MASK_VENMSG1_DROP_SET(dst, src) (((dst) & ~0x2) | (((UINT32) (src) << 1) & 0x2))
  276. #define CX_FLT_MASK_DABORT_4UCPL_SET(dst, src) (((dst) & ~0x4) | (((UINT32) (src) << 2) & 0x4))
  277. // GEN2_CTRL_OFF
  278. #define NUM_OF_LANES_SET(dst, src) (((dst) & ~0x1F00) | (((UINT32) (src) << 8) & 0x1F00))
  279. #define NUM_OF_LANES_X2 0x2
  280. #define NUM_OF_LANES_X4 0x4
  281. #define NUM_OF_LANES_X8 0x8
  282. #define NUM_OF_LANES_X16 0x10
  283. // GEN3_RELATED_OFF
  284. #define RATE_SHADOW_SEL_SET(dst, src) (((dst) & ~0x3000000) | (((UINT32) (src) << 24) & 0x3000000))
  285. #define GEN3_DATA_RATE 0x00
  286. #define GEN4_DATA_RATE 0x01
  287. #define EQ_PHASE_2_3_SET(dst, src) (((dst) & ~0x200) | (((UINT32) (src) << 9) & 0x200))
  288. #define ENABLE_EQ_PHASE_2_3 0x00
  289. #define DISABLE_EQ_PHASE_2_3 0x01
  290. #define RXEQ_REGRDLESS_SET(dst, src) (((dst) & ~0x2000) | (((UINT32) (src) << 13) & 0x2000))
  291. #define ASSERT_RXEQ 0x01
  292. // GEN3_EQ_CONTROL_OFF
  293. #define GEN3_EQ_FB_MODE(dst, src) (((dst) & ~0xF) | ((UINT32) (src) & 0xF))
  294. #define FOM_METHOD 0x01
  295. #define GEN3_EQ_PRESET_VEC(dst, src) (((dst) & 0xFF0000FF) | (((UINT32) (src) << 8) & 0xFFFF00))
  296. #define EQ_DEFAULT_PRESET_VECTOR 0x370
  297. #define GEN3_EQ_INIT_EVAL(dst,src) (((dst) & ~0x1000000) | (((UINT32) (src) << 24) & 0x1000000))
  298. #define INCLUDE_INIT_FOM 0x01
  299. // MISC_CONTROL_1_OFF
  300. #define DBI_RO_WR_EN_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  301. #define ENABLE_WR 0x01
  302. #define DISABLE_WR 0x00
  303. // AMBA_ERROR_RESPONSE_DEFAULT_OFF
  304. #define AMBA_ERROR_RESPONSE_CRS_SET(dst, src) (((dst) & ~0x18) | (((UINT32) (src) << 3) & 0x18))
  305. #define AMBA_ERROR_RESPONSE_GLOBAL_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
  306. // AMBA_LINK_TIMEOUT_OFF
  307. #define LINK_TIMEOUT_PERIOD_DEFAULT_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
  308. // AMBA_ORDERING_CTRL_OFF
  309. #define AX_MSTR_ZEROLREAD_FW_SET(dst, src) (((dst) & ~0x80) | (((UINT32) (src) << 7) & 0x80))
  310. // DTIM_CTRL0_OFF
  311. #define DTIM_CTRL0_ROOT_PORT_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
  312. // AUX_CLK_FREQ_OFF
  313. #define AUX_CLK_FREQ_SET(dst, src) (((dst) & ~0x1FF) | (((UINT32) (src)) & 0x1FF))
  314. #define AUX_CLK_500MHZ 500
  315. #endif /* AC01_PCIE_CORE_H_ */