OpenBoardPkg.fdf 27 KB

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  1. ## @file
  2. # FDF file of Platform.
  3. #
  4. # Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. [Defines]
  10. !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
  11. ################################################################################
  12. #
  13. # FD Section
  14. # The [FD] Section is made up of the definition statements and a
  15. # description of what goes into the Flash Device Image. Each FD section
  16. # defines one flash "device" image. A flash device image may be one of
  17. # the following: Removable media bootable image (like a boot floppy
  18. # image,) an Option ROM image (that would be "flashed" into an add-in
  19. # card,) a System "Flash" image (that would be burned into a system's
  20. # flash) or an Update ("Capsule") image that will be used to update and
  21. # existing system flash.
  22. #
  23. ################################################################################
  24. [FD.KabylakeRvp3]
  25. #
  26. # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
  27. # assigned with PCD values. Instead, it uses the definitions for its variety, which
  28. # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
  29. #
  30. BaseAddress = $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the FLASH Device.
  31. Size = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize #The size in bytes of the FLASH Device
  32. ErasePolarity = 1
  33. BlockSize = $(FLASH_BLOCK_SIZE)
  34. NumBlocks = $(FLASH_NUM_BLOCKS)
  35. DEFINE SIPKG_DXE_SMM_BIN = INF
  36. DEFINE SIPKG_PEI_BIN = INF
  37. # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
  38. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
  39. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
  40. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  41. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  42. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
  43. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
  44. SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
  45. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
  46. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  47. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
  48. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  49. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
  50. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
  51. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
  52. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
  53. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  54. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
  55. ################################################################################
  56. #
  57. # Following are lists of FD Region layout which correspond to the locations of different
  58. # images within the flash device.
  59. #
  60. # Regions must be defined in ascending order and may not overlap.
  61. #
  62. # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
  63. # the pipe "|" character, followed by the size of the region, also in hex with the leading
  64. # "0x" characters. Like:
  65. # Offset|Size
  66. # PcdOffsetCName|PcdSizeCName
  67. # RegionType <FV, DATA, or FILE>
  68. # Fv Size can be adjusted
  69. #
  70. ################################################################################
  71. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  72. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  73. #NV_VARIABLE_STORE
  74. DATA = {
  75. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  76. # ZeroVector []
  77. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  78. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  79. # FileSystemGuid
  80. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  81. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  82. # FvLength: 0x40000
  83. 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  84. #Signature "_FVH" #Attributes
  85. 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
  86. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  87. #
  88. # Be careful on CheckSum field.
  89. #
  90. 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
  91. #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
  92. 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  93. #Blockmap[1]: End
  94. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  95. ## This is the VARIABLE_STORE_HEADER
  96. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  97. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
  98. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  99. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  100. !else
  101. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  102. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  103. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  104. !endif
  105. #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
  106. # This can speed up the Variable Dispatch a bit.
  107. 0xB8, 0xDF, 0x01, 0x00,
  108. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  109. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  110. }
  111. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  112. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  113. #NV_FTW_WORKING
  114. DATA = {
  115. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  116. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  117. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  118. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  119. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  120. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  121. # WriteQueueSize: UINT64
  122. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  123. }
  124. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  125. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  126. #NV_FTW_SPARE
  127. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  128. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  129. FV = FvAdvanced
  130. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  131. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  132. FV = FvSecurity
  133. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  134. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  135. FV = FvOsBoot
  136. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  137. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  138. FV = FvUefiBoot
  139. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  140. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  141. FV = FvPostMemory
  142. gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  143. gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  144. #Microcode
  145. FV = FvMicrocode
  146. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  147. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  148. # FSP_S Section
  149. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
  150. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  151. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  152. # FSP_M Section
  153. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
  154. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  155. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  156. # FSP_T Section
  157. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
  158. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
  159. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
  160. FV = FvAdvancedPreMemory
  161. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  162. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  163. FV = FvPreMemory
  164. ################################################################################
  165. #
  166. # FV Section
  167. #
  168. # [FV] section is used to define what components or modules are placed within a flash
  169. # device file. This section also defines order the components and modules are positioned
  170. # within the image. The [FV] section consists of define statements, set statements and
  171. # module statements.
  172. #
  173. ################################################################################
  174. [FV.FvMicrocode]
  175. BlockSize = $(FLASH_BLOCK_SIZE)
  176. FvAlignment = 16
  177. ERASE_POLARITY = 1
  178. MEMORY_MAPPED = TRUE
  179. STICKY_WRITE = TRUE
  180. LOCK_CAP = TRUE
  181. LOCK_STATUS = FALSE
  182. WRITE_DISABLED_CAP = TRUE
  183. WRITE_ENABLED_CAP = TRUE
  184. WRITE_STATUS = TRUE
  185. WRITE_LOCK_CAP = TRUE
  186. WRITE_LOCK_STATUS = TRUE
  187. READ_DISABLED_CAP = TRUE
  188. READ_ENABLED_CAP = TRUE
  189. READ_STATUS = FALSE
  190. READ_LOCK_CAP = TRUE
  191. READ_LOCK_STATUS = TRUE
  192. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
  193. [FV.FvPreMemory]
  194. BlockSize = $(FLASH_BLOCK_SIZE)
  195. FvAlignment = 16
  196. ERASE_POLARITY = 1
  197. MEMORY_MAPPED = TRUE
  198. STICKY_WRITE = TRUE
  199. LOCK_CAP = TRUE
  200. LOCK_STATUS = TRUE
  201. WRITE_DISABLED_CAP = TRUE
  202. WRITE_ENABLED_CAP = TRUE
  203. WRITE_STATUS = TRUE
  204. WRITE_LOCK_CAP = TRUE
  205. WRITE_LOCK_STATUS = TRUE
  206. READ_DISABLED_CAP = TRUE
  207. READ_ENABLED_CAP = TRUE
  208. READ_STATUS = TRUE
  209. READ_LOCK_CAP = TRUE
  210. READ_LOCK_STATUS = TRUE
  211. FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
  212. INF UefiCpuPkg/SecCore/SecCore.inf
  213. !if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
  214. #
  215. # PeiMain is needed only for FSP API mode or EDK2 build,
  216. # in FSP dispatch mode the one inside FSP Binary is launched
  217. # unless requested otherwise (PcdFspDispatchModeUseFspPeiMain == FALSE).
  218. #
  219. INF MdeModulePkg/Core/Pei/PeiMain.inf
  220. !endif
  221. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  222. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  223. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  224. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  225. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  226. INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
  227. [FV.FvPostMemoryUncompact]
  228. BlockSize = $(FLASH_BLOCK_SIZE)
  229. FvAlignment = 16
  230. ERASE_POLARITY = 1
  231. MEMORY_MAPPED = TRUE
  232. STICKY_WRITE = TRUE
  233. LOCK_CAP = TRUE
  234. LOCK_STATUS = TRUE
  235. WRITE_DISABLED_CAP = TRUE
  236. WRITE_ENABLED_CAP = TRUE
  237. WRITE_STATUS = TRUE
  238. WRITE_LOCK_CAP = TRUE
  239. WRITE_LOCK_STATUS = TRUE
  240. READ_DISABLED_CAP = TRUE
  241. READ_ENABLED_CAP = TRUE
  242. READ_STATUS = TRUE
  243. READ_LOCK_CAP = TRUE
  244. READ_LOCK_STATUS = TRUE
  245. FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
  246. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  247. # Init Board Config PCD
  248. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  249. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  250. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  251. !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
  252. FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
  253. SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
  254. SECTION UI = "Vbt"
  255. }
  256. FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
  257. SECTION RAW = MdeModulePkg/Logo/Logo.bmp
  258. }
  259. !endif # PcdPeiDisplayEnable
  260. [FV.FvPostMemory]
  261. BlockSize = $(FLASH_BLOCK_SIZE)
  262. FvAlignment = 16
  263. ERASE_POLARITY = 1
  264. MEMORY_MAPPED = TRUE
  265. STICKY_WRITE = TRUE
  266. LOCK_CAP = TRUE
  267. LOCK_STATUS = TRUE
  268. WRITE_DISABLED_CAP = TRUE
  269. WRITE_ENABLED_CAP = TRUE
  270. WRITE_STATUS = TRUE
  271. WRITE_LOCK_CAP = TRUE
  272. WRITE_LOCK_STATUS = TRUE
  273. READ_DISABLED_CAP = TRUE
  274. READ_ENABLED_CAP = TRUE
  275. READ_STATUS = TRUE
  276. READ_LOCK_CAP = TRUE
  277. READ_LOCK_STATUS = TRUE
  278. FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
  279. FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
  280. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  281. SECTION FV_IMAGE = FvPostMemoryUncompact
  282. }
  283. }
  284. [FV.FvUefiBootUncompact]
  285. BlockSize = $(FLASH_BLOCK_SIZE)
  286. FvAlignment = 16
  287. ERASE_POLARITY = 1
  288. MEMORY_MAPPED = TRUE
  289. STICKY_WRITE = TRUE
  290. LOCK_CAP = TRUE
  291. LOCK_STATUS = TRUE
  292. WRITE_DISABLED_CAP = TRUE
  293. WRITE_ENABLED_CAP = TRUE
  294. WRITE_STATUS = TRUE
  295. WRITE_LOCK_CAP = TRUE
  296. WRITE_LOCK_STATUS = TRUE
  297. READ_DISABLED_CAP = TRUE
  298. READ_ENABLED_CAP = TRUE
  299. READ_STATUS = TRUE
  300. READ_LOCK_CAP = TRUE
  301. READ_LOCK_STATUS = TRUE
  302. FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
  303. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  304. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  305. INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
  306. INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
  307. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  308. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  309. INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
  310. INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
  311. INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
  312. INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
  313. INF ShellPkg/Application/Shell/Shell.inf
  314. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  315. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  316. #
  317. # Below module is used by FSP API mode
  318. #
  319. INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
  320. !endif
  321. INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
  322. [FV.FvUefiBoot]
  323. BlockSize = $(FLASH_BLOCK_SIZE)
  324. FvAlignment = 16
  325. ERASE_POLARITY = 1
  326. MEMORY_MAPPED = TRUE
  327. STICKY_WRITE = TRUE
  328. LOCK_CAP = TRUE
  329. LOCK_STATUS = TRUE
  330. WRITE_DISABLED_CAP = TRUE
  331. WRITE_ENABLED_CAP = TRUE
  332. WRITE_STATUS = TRUE
  333. WRITE_LOCK_CAP = TRUE
  334. WRITE_LOCK_STATUS = TRUE
  335. READ_DISABLED_CAP = TRUE
  336. READ_ENABLED_CAP = TRUE
  337. READ_STATUS = TRUE
  338. READ_LOCK_CAP = TRUE
  339. READ_LOCK_STATUS = TRUE
  340. FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
  341. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  342. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  343. SECTION FV_IMAGE = FvUefiBootUncompact
  344. }
  345. }
  346. [FV.FvOsBootUncompact]
  347. BlockSize = $(FLASH_BLOCK_SIZE)
  348. FvAlignment = 16
  349. ERASE_POLARITY = 1
  350. MEMORY_MAPPED = TRUE
  351. STICKY_WRITE = TRUE
  352. LOCK_CAP = TRUE
  353. LOCK_STATUS = TRUE
  354. WRITE_DISABLED_CAP = TRUE
  355. WRITE_ENABLED_CAP = TRUE
  356. WRITE_STATUS = TRUE
  357. WRITE_LOCK_CAP = TRUE
  358. WRITE_LOCK_STATUS = TRUE
  359. READ_DISABLED_CAP = TRUE
  360. READ_ENABLED_CAP = TRUE
  361. READ_STATUS = TRUE
  362. READ_LOCK_CAP = TRUE
  363. READ_LOCK_STATUS = TRUE
  364. FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
  365. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  366. INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
  367. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  368. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
  369. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  370. INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  371. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  372. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  373. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  374. INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  375. !endif
  376. [FV.FvLateSilicon]
  377. BlockSize = $(FLASH_BLOCK_SIZE)
  378. FvAlignment = 16
  379. ERASE_POLARITY = 1
  380. MEMORY_MAPPED = TRUE
  381. STICKY_WRITE = TRUE
  382. LOCK_CAP = TRUE
  383. LOCK_STATUS = TRUE
  384. WRITE_DISABLED_CAP = TRUE
  385. WRITE_ENABLED_CAP = TRUE
  386. WRITE_STATUS = TRUE
  387. WRITE_LOCK_CAP = TRUE
  388. WRITE_LOCK_STATUS = TRUE
  389. READ_DISABLED_CAP = TRUE
  390. READ_ENABLED_CAP = TRUE
  391. READ_STATUS = TRUE
  392. READ_LOCK_CAP = TRUE
  393. READ_LOCK_STATUS = TRUE
  394. FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
  395. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  396. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf
  397. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
  398. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
  399. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
  400. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
  401. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
  402. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
  403. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
  404. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
  405. !endif
  406. [FV.FvOsBoot]
  407. BlockSize = $(FLASH_BLOCK_SIZE)
  408. FvAlignment = 16
  409. ERASE_POLARITY = 1
  410. MEMORY_MAPPED = TRUE
  411. STICKY_WRITE = TRUE
  412. LOCK_CAP = TRUE
  413. LOCK_STATUS = TRUE
  414. WRITE_DISABLED_CAP = TRUE
  415. WRITE_ENABLED_CAP = TRUE
  416. WRITE_STATUS = TRUE
  417. WRITE_LOCK_CAP = TRUE
  418. WRITE_LOCK_STATUS = TRUE
  419. READ_DISABLED_CAP = TRUE
  420. READ_ENABLED_CAP = TRUE
  421. READ_STATUS = TRUE
  422. READ_LOCK_CAP = TRUE
  423. READ_LOCK_STATUS = TRUE
  424. FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
  425. FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
  426. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  427. SECTION FV_IMAGE = FvOsBootUncompact
  428. }
  429. }
  430. FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
  431. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  432. SECTION FV_IMAGE = FvLateSilicon
  433. }
  434. }
  435. [FV.FvSecurityPreMemory]
  436. BlockSize = $(FLASH_BLOCK_SIZE)
  437. FvAlignment = 16 #FV alignment and FV attributes setting.
  438. ERASE_POLARITY = 1
  439. MEMORY_MAPPED = TRUE
  440. STICKY_WRITE = TRUE
  441. LOCK_CAP = TRUE
  442. LOCK_STATUS = TRUE
  443. WRITE_DISABLED_CAP = TRUE
  444. WRITE_ENABLED_CAP = TRUE
  445. WRITE_STATUS = TRUE
  446. WRITE_LOCK_CAP = TRUE
  447. WRITE_LOCK_STATUS = TRUE
  448. READ_DISABLED_CAP = TRUE
  449. READ_ENABLED_CAP = TRUE
  450. READ_STATUS = TRUE
  451. READ_LOCK_CAP = TRUE
  452. READ_LOCK_STATUS = TRUE
  453. FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
  454. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  455. INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  456. INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
  457. [FV.FvSecurityPostMemory]
  458. BlockSize = $(FLASH_BLOCK_SIZE)
  459. FvAlignment = 16 #FV alignment and FV attributes setting.
  460. ERASE_POLARITY = 1
  461. MEMORY_MAPPED = TRUE
  462. STICKY_WRITE = TRUE
  463. LOCK_CAP = TRUE
  464. LOCK_STATUS = TRUE
  465. WRITE_DISABLED_CAP = TRUE
  466. WRITE_ENABLED_CAP = TRUE
  467. WRITE_STATUS = TRUE
  468. WRITE_LOCK_CAP = TRUE
  469. WRITE_LOCK_STATUS = TRUE
  470. READ_DISABLED_CAP = TRUE
  471. READ_ENABLED_CAP = TRUE
  472. READ_STATUS = TRUE
  473. READ_LOCK_CAP = TRUE
  474. READ_LOCK_STATUS = TRUE
  475. FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
  476. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  477. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  478. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  479. !endif
  480. [FV.FvSecurityLate]
  481. BlockSize = $(FLASH_BLOCK_SIZE)
  482. FvAlignment = 16
  483. ERASE_POLARITY = 1
  484. MEMORY_MAPPED = TRUE
  485. STICKY_WRITE = TRUE
  486. LOCK_CAP = TRUE
  487. LOCK_STATUS = TRUE
  488. WRITE_DISABLED_CAP = TRUE
  489. WRITE_ENABLED_CAP = TRUE
  490. WRITE_STATUS = TRUE
  491. WRITE_LOCK_CAP = TRUE
  492. WRITE_LOCK_STATUS = TRUE
  493. READ_DISABLED_CAP = TRUE
  494. READ_ENABLED_CAP = TRUE
  495. READ_STATUS = TRUE
  496. READ_LOCK_CAP = TRUE
  497. READ_LOCK_STATUS = TRUE
  498. FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
  499. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  500. INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
  501. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  502. INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf
  503. !endif
  504. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  505. INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
  506. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  507. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  508. !endif
  509. !endif
  510. [FV.FvSecurity]
  511. BlockSize = $(FLASH_BLOCK_SIZE)
  512. FvAlignment = 16
  513. ERASE_POLARITY = 1
  514. MEMORY_MAPPED = TRUE
  515. STICKY_WRITE = TRUE
  516. LOCK_CAP = TRUE
  517. LOCK_STATUS = TRUE
  518. WRITE_DISABLED_CAP = TRUE
  519. WRITE_ENABLED_CAP = TRUE
  520. WRITE_STATUS = TRUE
  521. WRITE_LOCK_CAP = TRUE
  522. WRITE_LOCK_STATUS = TRUE
  523. READ_DISABLED_CAP = TRUE
  524. READ_ENABLED_CAP = TRUE
  525. READ_STATUS = TRUE
  526. READ_LOCK_CAP = TRUE
  527. READ_LOCK_STATUS = TRUE
  528. FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
  529. FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
  530. SECTION FV_IMAGE = FvSecurityPreMemory
  531. }
  532. FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
  533. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  534. SECTION FV_IMAGE = FvSecurityPostMemory
  535. }
  536. }
  537. FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
  538. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  539. SECTION FV_IMAGE = FvSecurityLate
  540. }
  541. }
  542. #
  543. # Pre-memory Advanced Features
  544. #
  545. [FV.FvAdvancedPreMemory]
  546. FvAlignment = 16
  547. ERASE_POLARITY = 1
  548. MEMORY_MAPPED = TRUE
  549. STICKY_WRITE = TRUE
  550. LOCK_CAP = TRUE
  551. LOCK_STATUS = TRUE
  552. WRITE_DISABLED_CAP = TRUE
  553. WRITE_ENABLED_CAP = TRUE
  554. WRITE_STATUS = TRUE
  555. WRITE_LOCK_CAP = TRUE
  556. WRITE_LOCK_STATUS = TRUE
  557. READ_DISABLED_CAP = TRUE
  558. READ_ENABLED_CAP = TRUE
  559. READ_STATUS = TRUE
  560. READ_LOCK_CAP = TRUE
  561. READ_LOCK_STATUS = TRUE
  562. FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
  563. !include AdvancedFeaturePkg/Include/PreMemory.fdf
  564. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  565. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
  566. !endif
  567. #
  568. # Post-Memory Advanced Features
  569. #
  570. [FV.FvAdvancedUncompact]
  571. FvAlignment = 16
  572. ERASE_POLARITY = 1
  573. MEMORY_MAPPED = TRUE
  574. STICKY_WRITE = TRUE
  575. LOCK_CAP = TRUE
  576. LOCK_STATUS = TRUE
  577. WRITE_DISABLED_CAP = TRUE
  578. WRITE_ENABLED_CAP = TRUE
  579. WRITE_STATUS = TRUE
  580. WRITE_LOCK_CAP = TRUE
  581. WRITE_LOCK_STATUS = TRUE
  582. READ_DISABLED_CAP = TRUE
  583. READ_ENABLED_CAP = TRUE
  584. READ_STATUS = TRUE
  585. READ_LOCK_CAP = TRUE
  586. READ_LOCK_STATUS = TRUE
  587. FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
  588. !include AdvancedFeaturePkg/Include/PostMemory.fdf
  589. !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  590. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
  591. INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
  592. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  593. !endif
  594. #
  595. # Compressed FV with Post-Memory Advanced Features
  596. #
  597. [FV.FvAdvanced]
  598. BlockSize = $(FLASH_BLOCK_SIZE)
  599. FvAlignment = 16
  600. ERASE_POLARITY = 1
  601. MEMORY_MAPPED = TRUE
  602. STICKY_WRITE = TRUE
  603. LOCK_CAP = TRUE
  604. LOCK_STATUS = TRUE
  605. WRITE_DISABLED_CAP = TRUE
  606. WRITE_ENABLED_CAP = TRUE
  607. WRITE_STATUS = TRUE
  608. WRITE_LOCK_CAP = TRUE
  609. WRITE_LOCK_STATUS = TRUE
  610. READ_DISABLED_CAP = TRUE
  611. READ_ENABLED_CAP = TRUE
  612. READ_STATUS = TRUE
  613. READ_LOCK_CAP = TRUE
  614. READ_LOCK_STATUS = TRUE
  615. FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
  616. FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
  617. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  618. SECTION FV_IMAGE = FvAdvancedUncompact
  619. }
  620. }
  621. ################################################################################
  622. #
  623. # Rules are use with the [FV] section's module INF type to define
  624. # how an FFS file is created for a given INF file. The following Rule are the default
  625. # rules for the different module type. User can add the customized rules to define the
  626. # content of the FFS file.
  627. #
  628. ################################################################################
  629. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf