Ac01.h 9.3 KB

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  1. /** @file
  2. Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef PLATFORM_AC01_H_
  6. #define PLATFORM_AC01_H_
  7. //
  8. // Number of supported sockets in the platform
  9. //
  10. #define PLATFORM_CPU_MAX_SOCKET 2
  11. //
  12. // Maximum number of CPMs in the chip.
  13. //
  14. #define PLATFORM_CPU_MAX_CPM (FixedPcdGet32 (PcdClusterCount))
  15. //
  16. // Number of cores per CPM.
  17. //
  18. #define PLATFORM_CPU_NUM_CORES_PER_CPM (FixedPcdGet32 (PcdCoreCount) / PLATFORM_CPU_MAX_CPM)
  19. //
  20. // Maximum number of cores supported.
  21. //
  22. #define PLATFORM_CPU_MAX_NUM_CORES (PLATFORM_CPU_MAX_SOCKET * PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM)
  23. //
  24. // Maximum number of memory region
  25. //
  26. #define PLATFORM_DRAM_INFO_MAX_REGION 16
  27. //
  28. // Maximum number of DDR slots supported
  29. //
  30. #define PLATFORM_DIMM_INFO_MAX_SLOT 32
  31. //
  32. // CSR Address base for slave socket
  33. //
  34. #define SLAVE_SOCKET_BASE_ADDRESS_OFFSET 0x400000000000
  35. //
  36. // SMpro EFUSE Shadow register
  37. //
  38. #define SMPRO_EFUSE_SHADOW0 (FixedPcdGet64 (PcdSmproEfuseShadow0))
  39. //
  40. // 2P Configuration Register
  41. //
  42. #define CFG2P_OFFSET 0x200
  43. //
  44. // Slave socket present
  45. //
  46. #define SLAVE_PRESENT_N BIT1
  47. //
  48. // The maximum number of I2C bus
  49. //
  50. #define AC01_I2C_MAX_BUS_NUM 2
  51. //
  52. // The base address of DW I2C
  53. //
  54. #define AC01_I2C_BASE_ADDRESS_LIST 0x1000026B0000ULL, 0x100002750000ULL
  55. //
  56. // The Array of Soc Gpio Base Address
  57. //
  58. #define AC01_GPIO_BASE_ADDRESS_LIST 0x1000026f0000, 0x1000026e0000, 0x1000027b0000, 0x1000026d0000, 0x5000026f0000, 0x5000026e0000, 0x5000027b0000, 0x5000026d0000
  59. //
  60. // The Array of Soc Gpi Base Address
  61. //
  62. #define AC01_GPI_BASE_ADDRESS_LIST 0x1000026d0000, 0x5000026d0000
  63. //
  64. // Number of Pins Per Each Contoller
  65. //
  66. #define AC01_GPIO_PINS_PER_CONTROLLER 8
  67. //
  68. // Number of Pins Each Socket
  69. //
  70. #define AC01_GPIO_PINS_PER_SOCKET 32
  71. //
  72. // Maximum number of memory controller supports NVDIMM-N per socket
  73. //
  74. #define AC01_NVDIMM_MAX_MCU_PER_SOCKET 2
  75. //
  76. // Maximum number of NVDIMM-N per memory controller
  77. //
  78. #define AC01_NVDIMM_MAX_DIMM_PER_MCU 1
  79. //
  80. // Maximum number of NVDIMM region per socket
  81. //
  82. #define AC01_NVDIMM_MAX_REGION_PER_SOCKET 2
  83. //
  84. // Socket 0 base address of NVDIMM non-hashed region 0
  85. //
  86. #define AC01_NVDIMM_SK0_NHASHED_REGION0_BASE 0x0B0000000000ULL
  87. //
  88. // Socket 0 base address of NVDIMM non-hashed region 1
  89. //
  90. #define AC01_NVDIMM_SK0_NHASHED_REGION1_BASE 0x0F0000000000ULL
  91. //
  92. // Socket 1 base address of NVDIMM non-hashed region 0
  93. //
  94. #define AC01_NVDIMM_SK1_NHASHED_REGION0_BASE 0x430000000000ULL
  95. //
  96. // Socket 1 base address of NVDIMM non-hashed region 1
  97. //
  98. #define AC01_NVDIMM_SK1_NHASHED_REGION1_BASE 0x470000000000ULL
  99. //
  100. // DIMM ID of NVDIMM-N device 1
  101. //
  102. #define AC01_NVDIMM_NVD1_DIMM_ID 6
  103. //
  104. // DIMM ID of NVDIMM-N device 2
  105. //
  106. #define AC01_NVDIMM_NVD2_DIMM_ID 14
  107. //
  108. // DIMM ID of NVDIMM-N device 3
  109. //
  110. #define AC01_NVDIMM_NVD3_DIMM_ID 22
  111. //
  112. // DIMM ID of NVDIMM-N device 4
  113. //
  114. #define AC01_NVDIMM_NVD4_DIMM_ID 30
  115. //
  116. // NFIT device handle of NVDIMM-N device 1
  117. //
  118. #define AC01_NVDIMM_NVD1_DEVICE_HANDLE 0x0330
  119. //
  120. // NFIT device handle of NVDIMM-N device 2
  121. //
  122. #define AC01_NVDIMM_NVD2_DEVICE_HANDLE 0x0770
  123. //
  124. // NFIT device handle of NVDIMM-N device 3
  125. //
  126. #define AC01_NVDIMM_NVD3_DEVICE_HANDLE 0x1330
  127. //
  128. // NFIT device handle of NVDIMM-N device 4
  129. //
  130. #define AC01_NVDIMM_NVD4_DEVICE_HANDLE 0x1770
  131. //
  132. // Interleave ways of non-hashed NVDIMM-N
  133. //
  134. #define AC01_NVDIMM_NHASHED_INTERLEAVE_WAYS 1
  135. //
  136. // Interleave ways of hashed NVDIMM-N
  137. //
  138. #define AC01_NVDIMM_HASHED_INTERLEAVE_WAYS 2
  139. //
  140. // Region offset of hashed NVDIMM-N
  141. //
  142. #define AC01_NVDIMM_HASHED_REGION_OFFSET 512
  143. //
  144. // The base address of GIC distributor registers
  145. //
  146. #define AC01_GICD_MASTER_BASE_ADDRESS 0x100100000000
  147. //
  148. // The base address of master socket GIC redistributor registers
  149. //
  150. #define AC01_GICR_MASTER_BASE_ADDRESS 0x100100140000
  151. //
  152. // The base address of slave socket GIC distributor registers
  153. //
  154. #define AC01_GICD_SLAVE_BASE_ADDRESS 0x500100000000
  155. //
  156. // The base address of slave socket GIC redistributor registers
  157. //
  158. #define AC01_GICR_SLAVE_BASE_ADDRESS 0x500100140000
  159. //
  160. // Socket 0 first RC
  161. //
  162. #define SOCKET0_FIRST_RC 2
  163. //
  164. // Socket 0 last RC
  165. //
  166. #define SOCKET0_LAST_RC 7
  167. //
  168. // Socket 1 first RC
  169. //
  170. #define SOCKET1_FIRST_RC 10
  171. //
  172. // Socket 1 last RC
  173. //
  174. #define SOCKET1_LAST_RC 15
  175. //
  176. // Socket bit offset of core UID.
  177. //
  178. #define PLATFORM_SOCKET_UID_BIT_OFFSET 16
  179. //
  180. // CPM bit offset of core UID.
  181. //
  182. #define PLATFORM_CPM_UID_BIT_OFFSET 8
  183. //
  184. // Max number for AC01 PCIE Root Complexes
  185. //
  186. #define AC01_PCIE_MAX_ROOT_COMPLEX 16
  187. //
  188. // Max number for AC01 PCIE Root Complexes per socket
  189. //
  190. #define AC01_PCIE_MAX_RCS_PER_SOCKET 8
  191. //
  192. // The size of IO space
  193. //
  194. #define AC01_PCIE_IO_SIZE 0x2000
  195. //
  196. // The base address of {TCU, CSR, MMCONFIG} Registers
  197. //
  198. #define AC01_PCIE_CSR_BASE_LIST 0x33FFE0000000, 0x37FFE0000000, 0x3BFFE0000000, 0x3FFFE0000000, 0x23FFE0000000, 0x27FFE0000000, 0x2BFFE0000000, 0x2FFFE0000000, 0x73FFE0000000, 0x77FFE0000000, 0x7BFFE0000000, 0x7FFFE0000000, 0x63FFE0000000, 0x67FFE0000000, 0x6BFFE0000000, 0x6FFFE0000000
  199. //
  200. // The base address of MMIO Registers
  201. //
  202. #define AC01_PCIE_MMIO_BASE_LIST 0x300000000000, 0x340000000000, 0x380000000000, 0x3C0000000000, 0x200000000000, 0x240000000000, 0x280000000000, 0x2C0000000000, 0x700000000000, 0x740000000000, 0x780000000000, 0x7C0000000000, 0x600000000000, 0x640000000000, 0x680000000000, 0x6C0000000000
  203. //
  204. // The size of MMIO space
  205. //
  206. #define AC01_PCIE_MMIO_SIZE_LIST 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000
  207. //
  208. // The base address of MMIO32 Registers
  209. //
  210. #define AC01_PCIE_MMIO32_BASE_LIST 0x000020000000, 0x000028000000, 0x000030000000, 0x000038000000, 0x000004000000, 0x000008000000, 0x000010000000, 0x000018000000, 0x000060000000, 0x000068000000, 0x000070000000, 0x000078000000, 0x000040000000, 0x000048000000, 0x000050000000, 0x000058000000
  211. //
  212. // The size of MMIO32 space
  213. //
  214. #define AC01_PCIE_MMIO32_SIZE_LIST 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x4000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000
  215. //
  216. // The base address of MMIO32 Registers
  217. //
  218. #define AC01_PCIE_MMIO32_BASE_1P_LIST 0x000040000000, 0x000050000000, 0x000060000000, 0x000070000000, 0x000008000000, 0x000010000000, 0x000020000000, 0x000030000000, 0, 0, 0, 0, 0, 0, 0, 0
  219. //
  220. // The size of MMIO32 1P space
  221. //
  222. #define AC01_PCIE_MMIO32_SIZE_1P_LIST 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x8000000, 0x10000000, 0x10000000, 0x10000000, 0, 0, 0, 0, 0, 0, 0, 0
  223. //
  224. // DSDT RCA2 PCIe MMIO32 Attribute
  225. //
  226. #define AC01_PCIE_RCA2_QMEM_LIST 0x0000000000000000, 0x0000000060000000, 0x000000006FFFFFFF, 0x0000000000000000, 0x0000000010000000
  227. //
  228. // DSDT RCA3 PCIe MMIO32 Attribute
  229. //
  230. #define AC01_PCIE_RCA3_QMEM_LIST 0x0000000000000000, 0x0000000070000000, 0x000000007FFFFFFF, 0x0000000000000000, 0x0000000010000000
  231. //
  232. // DSDT RCB0 PCIe MMIO32 Attribute
  233. //
  234. #define AC01_PCIE_RCB0_QMEM_LIST 0x0000000000000000, 0x0000000008000000, 0x000000000FFFFFFF, 0x0000000000000000, 0x0000000008000000
  235. //
  236. // DSDT RCB1 PCIe MMIO32 Attribute
  237. //
  238. #define AC01_PCIE_RCB1_QMEM_LIST 0x0000000000000000, 0x0000000010000000, 0x000000001FFFFFFF, 0x0000000000000000, 0x0000000010000000
  239. //
  240. // DSDT RCB2 PCIe MMIO32 Attribute
  241. //
  242. #define AC01_PCIE_RCB2_QMEM_LIST 0x0000000000000000, 0x0000000020000000, 0x000000002FFFFFFF, 0x0000000000000000, 0x0000000010000000
  243. //
  244. // DSDT RCB3 PCIe MMIO32 Attribute
  245. //
  246. #define AC01_PCIE_RCB3_QMEM_LIST 0x0000000000000000, 0x0000000030000000, 0x000000003FFFFFFF, 0x0000000000000000, 0x0000000010000000
  247. //
  248. // TBU PMU IRQ array
  249. //
  250. #define AC01_SMMU_TBU_PMU_IRQS_LIST 224, 230, 236, 242, 160, 170, 180, 190, 544, 550, 556, 562, 480, 490, 500, 510
  251. //
  252. // TCU PMU IRQ array
  253. //
  254. #define AC01_SMMU_TCU_PMU_IRQS_LIST 256, 257, 258, 259, 260, 261, 262, 263, 576, 577, 578, 579, 580, 581, 582, 583
  255. //
  256. // Max TBU PMU of Root Complex A
  257. //
  258. #define AC01_RCA_MAX_TBU_PMU 6
  259. //
  260. // Max TBU PMU of Root Complex B
  261. //
  262. #define AC01_RCB_MAX_TBU_PMU 10
  263. //
  264. // TBU Base offset of Root Complex A
  265. //
  266. #define AC01_RCA_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE0000, 0x100000, 0x140000
  267. //
  268. // TBU Base offset of Root Complex B
  269. //
  270. #define AC01_RCB_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE0000, 0x120000, 0x160000, 0x180000, 0x1C0000, 0x200000, 0x240000
  271. #endif /* PLATFORM_AC01_H_ */