PeiKabylakeRvp3InitPreMemLib.c 9.3 KB

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  1. /** @file
  2. Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include <PiPei.h>
  6. #include <SaPolicyCommon.h>
  7. #include <Library/DebugLib.h>
  8. #include <Library/BaseMemoryLib.h>
  9. #include <Library/IoLib.h>
  10. #include <Library/HobLib.h>
  11. #include <Library/PcdLib.h>
  12. #include <Library/PchCycleDecodingLib.h>
  13. #include <Library/PciLib.h>
  14. #include <Library/PcdLib.h>
  15. #include <Library/BaseMemoryLib.h>
  16. #include <Library/PeiSaPolicyLib.h>
  17. #include <Library/BoardInitLib.h>
  18. #include <PchAccess.h>
  19. #include <Library/GpioNativeLib.h>
  20. #include <Library/GpioLib.h>
  21. #include <GpioPinsSklLp.h>
  22. #include <GpioPinsSklH.h>
  23. #include <Library/GpioExpanderLib.h>
  24. #include <SioRegs.h>
  25. #include <Library/PchPcrLib.h>
  26. #include <Library/SiliconInitLib.h>
  27. #include <Library/PchResetLib.h>
  28. #include "PeiKabylakeRvp3InitLib.h"
  29. #include <ConfigBlock.h>
  30. #include <ConfigBlock/MemoryConfig.h>
  31. //
  32. // Reference RCOMP resistors on motherboard - for SKL RVP1
  33. //
  34. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
  35. //
  36. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
  37. //
  38. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
  39. /**
  40. SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
  41. PEI_BOARD_CONFIG_PCD_INIT
  42. @param Content pointer to the buffer contain init information for board init.
  43. @retval EFI_SUCCESS The function completed successfully.
  44. @retval EFI_INVALID_PARAMETER The parameter is NULL.
  45. **/
  46. EFI_STATUS
  47. EFIAPI
  48. KabylakeRvp3InitPreMem (
  49. VOID
  50. )
  51. {
  52. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  53. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  54. PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
  55. PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
  56. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  57. PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
  58. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  59. //
  60. // HSIO PTSS Table
  61. //
  62. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
  63. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
  64. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
  65. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
  66. //
  67. // DRAM related definition
  68. //
  69. PcdSet8S (PcdSaMiscUserBd, 5);
  70. PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
  71. PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
  72. PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
  73. PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
  74. PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
  75. PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
  76. //
  77. // Example policy for DIMM slots implementation boards:
  78. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  79. // by reading from DIMM SPD.
  80. // 2. No need to apply hardcoded SpdData buffers here for such board.
  81. // Example:
  82. // PcdMrcSpdAddressTable0 = 0xA0
  83. // PcdMrcSpdAddressTable1 = 0xA2
  84. // PcdMrcSpdAddressTable2 = 0xA4
  85. // PcdMrcSpdAddressTable3 = 0xA6
  86. // PcdMrcSpdData = 0
  87. // PcdMrcSpdDataSize = 0
  88. //
  89. // Kabylake RVP3 has 8GB Memory down implementation withouit SPD,
  90. // So assign all SpdAddress to 0 and apply static SpdData buffers:
  91. // PcdMrcSpdAddressTable0 = 0
  92. // PcdMrcSpdAddressTable1 = 0
  93. // PcdMrcSpdAddressTable2 = 0
  94. // PcdMrcSpdAddressTable3 = 0
  95. // PcdMrcSpdData = static data buffer
  96. // PcdMrcSpdDataSize = sizeof (static data buffer)
  97. //
  98. PcdSet8S (PcdMrcSpdAddressTable0, 0);
  99. PcdSet8S (PcdMrcSpdAddressTable1, 0);
  100. PcdSet8S (PcdMrcSpdAddressTable2, 0);
  101. PcdSet8S (PcdMrcSpdAddressTable3, 0);
  102. PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);
  103. PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);
  104. PcdSetBoolS (PcdIoExpanderPresent, TRUE);
  105. return EFI_SUCCESS;
  106. }
  107. /**
  108. SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
  109. PEI_BOARD_CONFIG_PCD_INIT
  110. @param Content pointer to the buffer contain init information for board init.
  111. @retval EFI_SUCCESS The function completed successfully.
  112. @retval EFI_INVALID_PARAMETER The parameter is NULL.
  113. **/
  114. EFI_STATUS
  115. EFIAPI
  116. SkylakeRvp3InitPreMem (
  117. VOID
  118. )
  119. {
  120. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  121. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  122. PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
  123. PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
  124. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  125. PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
  126. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  127. //
  128. // HSIO PTSS Table
  129. //
  130. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
  131. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
  132. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
  133. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
  134. //
  135. // DRAM related definition
  136. //
  137. PcdSet8S (PcdSaMiscUserBd, 5);
  138. PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
  139. PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
  140. PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
  141. PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
  142. PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
  143. PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
  144. //
  145. // Example policy for DIMM slots implementation boards:
  146. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  147. // by reading from DIMM SPD.
  148. // 2. No need to apply hardcoded SpdData buffers here for such board.
  149. // Example:
  150. // PcdMrcSpdAddressTable0 = 0xA0
  151. // PcdMrcSpdAddressTable1 = 0xA2
  152. // PcdMrcSpdAddressTable2 = 0xA4
  153. // PcdMrcSpdAddressTable3 = 0xA6
  154. // PcdMrcSpdData = 0
  155. // PcdMrcSpdDataSize = 0
  156. //
  157. // Skylake RVP3 has 4GB Memory down implementation withouit SPD,
  158. // So assign all SpdAddress to 0 and apply static SpdData buffers:
  159. // PcdMrcSpdAddressTable0 = 0
  160. // PcdMrcSpdAddressTable1 = 0
  161. // PcdMrcSpdAddressTable2 = 0
  162. // PcdMrcSpdAddressTable3 = 0
  163. // PcdMrcSpdData = static data buffer
  164. // PcdMrcSpdDataSize = sizeof (static data buffer)
  165. //
  166. PcdSet8S (PcdMrcSpdAddressTable0, 0);
  167. PcdSet8S (PcdMrcSpdAddressTable1, 0);
  168. PcdSet8S (PcdMrcSpdAddressTable2, 0);
  169. PcdSet8S (PcdMrcSpdAddressTable3, 0);
  170. PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd);
  171. PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize);
  172. PcdSetBoolS (PcdIoExpanderPresent, TRUE);
  173. return EFI_SUCCESS;
  174. }
  175. #define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
  176. /**
  177. Configures GPIO.
  178. @param[in] GpioTable Point to Platform Gpio table
  179. @param[in] GpioTableCount Number of Gpio table entries
  180. **/
  181. VOID
  182. ConfigureGpio (
  183. IN GPIO_INIT_CONFIG *GpioDefinition,
  184. IN UINT16 GpioTableCount
  185. )
  186. {
  187. EFI_STATUS Status;
  188. DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
  189. Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
  190. DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
  191. }
  192. /**
  193. Configure GPIO Before Memory is not ready.
  194. **/
  195. VOID
  196. GpioInitPreMem (
  197. VOID
  198. )
  199. {
  200. // ConfigureGpio ();
  201. }
  202. /**
  203. Configure Super IO.
  204. **/
  205. VOID
  206. SioInit (
  207. VOID
  208. )
  209. {
  210. //
  211. // Program and Enable Default Super IO Configuration Port Addresses and range
  212. //
  213. PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
  214. //
  215. // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
  216. //
  217. PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
  218. return;
  219. }
  220. /**
  221. Configures the IC2 Controller on which GPIO Expander Communicates.
  222. This Function is to enable the I2CGPIOExapanderLib to program the Gpios
  223. Complete initialization will be done in later Stage
  224. **/
  225. VOID
  226. EFIAPI
  227. I2CGpioExpanderInitPreMem(
  228. VOID
  229. )
  230. {
  231. ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
  232. SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
  233. }
  234. /**
  235. Configure GPIO and SIO before memory ready.
  236. @retval EFI_SUCCESS Operation success.
  237. **/
  238. EFI_STATUS
  239. EFIAPI
  240. KabylakeRvp3BoardInitBeforeMemoryInit (
  241. VOID
  242. )
  243. {
  244. EFI_STATUS Status;
  245. if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
  246. KabylakeRvp3InitPreMem ();
  247. } else if (LibPcdGetSku () == BoardIdSkylakeRvp3) {
  248. SkylakeRvp3InitPreMem ();
  249. }
  250. //
  251. // Configures the I2CGpioExpander
  252. //
  253. if (PcdGetBool (PcdIoExpanderPresent)) {
  254. I2CGpioExpanderInitPreMem();
  255. }
  256. GpioInitPreMem ();
  257. SioInit ();
  258. ///
  259. /// Do basic PCH init
  260. ///
  261. SiliconInit ();
  262. //
  263. // Install PCH RESET PPI and EFI RESET2 PeiService
  264. //
  265. Status = PchInitializeReset ();
  266. ASSERT_EFI_ERROR (Status);
  267. return EFI_SUCCESS;
  268. }
  269. EFI_STATUS
  270. EFIAPI
  271. KabylakeRvp3BoardDebugInit (
  272. VOID
  273. )
  274. {
  275. return EFI_SUCCESS;
  276. }
  277. EFI_BOOT_MODE
  278. EFIAPI
  279. KabylakeRvp3BoardBootModeDetect (
  280. VOID
  281. )
  282. {
  283. return BOOT_WITH_FULL_CONFIGURATION;
  284. }