PeiGalagoPro3InitPreMemLib.c 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240
  1. /** @file
  2. System 76 GalagoPro3 board pre-memory initialization.
  3. Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiPei.h>
  7. #include <SaPolicyCommon.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/BaseMemoryLib.h>
  10. #include <Library/IoLib.h>
  11. #include <Library/HobLib.h>
  12. #include <Library/PcdLib.h>
  13. #include <Library/PchCycleDecodingLib.h>
  14. #include <Library/PciLib.h>
  15. #include <Library/PcdLib.h>
  16. #include <Library/BaseMemoryLib.h>
  17. #include <Library/PeiSaPolicyLib.h>
  18. #include <Library/BoardInitLib.h>
  19. #include <PchAccess.h>
  20. #include <Library/GpioNativeLib.h>
  21. #include <Library/GpioLib.h>
  22. #include <GpioPinsSklLp.h>
  23. #include <GpioPinsSklH.h>
  24. #include <Library/GpioExpanderLib.h>
  25. #include <SioRegs.h>
  26. #include <Library/PchPcrLib.h>
  27. #include <Library/SiliconInitLib.h>
  28. #include <Library/PchResetLib.h>
  29. #include "PeiGalagoPro3InitLib.h"
  30. #include <ConfigBlock.h>
  31. #include <ConfigBlock/MemoryConfig.h>
  32. //
  33. // Reference RCOMP resistors on motherboard - for SKL RVP1
  34. //
  35. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
  36. //
  37. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
  38. //
  39. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
  40. //
  41. // Reference RCOMP resistors on motherboard - for SKL RVP2
  42. //
  43. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp2[SA_MRC_MAX_RCOMP] = { 121, 81, 100 };
  44. //
  45. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP2
  46. //
  47. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp2[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 20, 20, 26 };
  48. /**
  49. N 1XX WU board configuration init function for PEI pre-memory phase.
  50. PEI_BOARD_CONFIG_PCD_INIT
  51. @param Content pointer to the buffer contain init information for board init.
  52. @retval EFI_SUCCESS The function completed successfully.
  53. @retval EFI_INVALID_PARAMETER The parameter is NULL.
  54. **/
  55. EFI_STATUS
  56. EFIAPI
  57. GalagoPro3InitPreMem (
  58. VOID
  59. )
  60. {
  61. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  62. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  63. PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
  64. PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
  65. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  66. PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
  67. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  68. //
  69. // HSIO PTSS Table
  70. //
  71. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_GalagoPro3);
  72. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_GALAGO_PRO_3_Size);
  73. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_GalagoPro3);
  74. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_GALAGO_PRO_3_Size);
  75. //
  76. // DRAM related definition
  77. //
  78. PcdSet8S (PcdSaMiscUserBd, 5);
  79. PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
  80. PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
  81. PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
  82. PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);
  83. PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
  84. PcdSetBoolS(PcdMrcDqPinsInterleaved, TRUE);
  85. PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorSklRvp2);
  86. PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetSklRvp2);
  87. PcdSet8S(PcdMrcCaVrefConfig, 2); // DDR4 boards
  88. PcdSetBoolS (PcdIoExpanderPresent, TRUE);
  89. return EFI_SUCCESS;
  90. }
  91. #define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
  92. /**
  93. Configures GPIO
  94. @param[in] GpioTable Point to Platform Gpio table
  95. @param[in] GpioTableCount Number of Gpio table entries
  96. **/
  97. VOID
  98. ConfigureGpio (
  99. IN GPIO_INIT_CONFIG *GpioDefinition,
  100. IN UINT16 GpioTableCount
  101. )
  102. {
  103. EFI_STATUS Status;
  104. DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
  105. Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
  106. DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
  107. }
  108. /**
  109. Configure GPIO Before Memory is not ready.
  110. **/
  111. VOID
  112. GpioInitPreMem (
  113. VOID
  114. )
  115. {
  116. // ConfigureGpio ();
  117. }
  118. /**
  119. Configure Super IO
  120. **/
  121. VOID
  122. SioInit (
  123. VOID
  124. )
  125. {
  126. //
  127. // Program and Enable Default Super IO Configuration Port Addresses and range
  128. //
  129. PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
  130. //
  131. // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
  132. //
  133. PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
  134. return;
  135. }
  136. /**
  137. Configures the IC2 Controller on which GPIO Expander Communicates.
  138. This Function is to enable the I2CGPIOExapanderLib to program the Gpios
  139. Complete initialization will be done in later Stage
  140. **/
  141. VOID
  142. EFIAPI
  143. I2CGpioExpanderInitPreMem(
  144. VOID
  145. )
  146. {
  147. ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
  148. SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
  149. }
  150. /**
  151. Configure GPIO and SIO before memory ready
  152. @retval EFI_SUCCESS Operation success.
  153. **/
  154. EFI_STATUS
  155. EFIAPI
  156. GalagoPro3BoardInitBeforeMemoryInit (
  157. VOID
  158. )
  159. {
  160. EFI_STATUS Status;
  161. GalagoPro3InitPreMem ();
  162. //
  163. // Configures the I2CGpioExpander
  164. //
  165. if (PcdGetBool (PcdIoExpanderPresent)) {
  166. I2CGpioExpanderInitPreMem();
  167. }
  168. GpioInitPreMem ();
  169. SioInit ();
  170. ///
  171. /// Do basic PCH init
  172. ///
  173. SiliconInit ();
  174. //
  175. // Install PCH RESET PPI and EFI RESET2 PeiService
  176. //
  177. Status = PchInitializeReset ();
  178. ASSERT_EFI_ERROR (Status);
  179. return EFI_SUCCESS;
  180. }
  181. EFI_STATUS
  182. EFIAPI
  183. GalagoPro3BoardDebugInit (
  184. VOID
  185. )
  186. {
  187. return EFI_SUCCESS;
  188. }
  189. EFI_BOOT_MODE
  190. EFIAPI
  191. GalagoPro3BoardBootModeDetect (
  192. VOID
  193. )
  194. {
  195. return BOOT_WITH_FULL_CONFIGURATION;
  196. }