PeiTiogaPassInitPreMemLib.c 18 KB

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  1. /** @file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. Copyright (c) 2021, American Megatrends International LLC.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Base.h>
  7. #include <PiPei.h>
  8. #include <Uefi.h>
  9. #include <Library/DebugLib.h>
  10. #include <Library/BaseLib.h>
  11. #include <Library/BaseMemoryLib.h>
  12. #include <Library/IoLib.h>
  13. #include <Library/HobLib.h>
  14. #include <Library/PcdLib.h>
  15. #include <Library/PciLib.h>
  16. #include <Library/BoardInitLib.h>
  17. #include <Library/PeiServicesLib.h>
  18. #include <Library/PeiServicesTablePointerLib.h>
  19. #include "PeiTiogaPassInitLib.h"
  20. #include <Ppi/BootInRecoveryMode.h>
  21. #include <Ppi/PchPolicy.h>
  22. #include <Ppi/ReadOnlyVariable2.h>
  23. #include <Ppi/FirmwareVolumeInfo.h>
  24. #include <Ppi/Reset.h>
  25. #include <Ppi/Smbus2.h>
  26. #include <Platform.h>
  27. #include <GpioPinsSklH.h>
  28. #include <Library/GpioLib.h>
  29. #include <Guid/SetupVariable.h>
  30. #include <Guid/PchRcVariable.h>
  31. #include <Guid/MemoryTypeInformation.h>
  32. #include <Library/MemoryAllocationLib.h>
  33. #include <Library/PeiServicesLib.h>
  34. #include <Library/DebugPrintErrorLevelLib.h>
  35. #include <Library/PrintLib.h>
  36. #include <SetupTable.h>
  37. #include <Library/PchCycleDecodingLib.h>
  38. #include <Platform.h>
  39. #include <Register/PchRegsPcr.h>
  40. #include <Register/PchRegsLpc.h>
  41. #include <Register/PchRegsSpi.h>
  42. #include <PchAccess.h>
  43. #include <Library/MmPciBaseLib.h>
  44. #include <IndustryStandard/Pci22.h>
  45. #include <Protocol/IioUds.h>
  46. #include <Ppi/MasterBootMode.h>
  47. #include <Ppi/EndOfPeiPhase.h>
  48. #include <Ppi/MemoryDiscovered.h>
  49. #include <Ppi/ReadOnlyVariable2.h>
  50. #include <Library/SiliconPolicyInitLib.h>
  51. #include <Library/SiliconPolicyUpdateLib.h>
  52. #include <Library/GpioLib.h>
  53. #include <Guid/GlobalVariable.h>
  54. #include <Library/TimerLib.h>
  55. #include <Register/PchRegsPmc.h>
  56. #include <Library/PchCycleDecodingLib.h>
  57. #include <Register/PchRegsLpc.h>
  58. #include <Guid/FirmwareFileSystem3.h>
  59. #include <Guid/SetupVariable.h>
  60. #include <Guid/PchRcVariable.h>
  61. #include <Guid/SocketVariable.h>
  62. #include <Library/PchPcrLib.h>
  63. #include <IioBifurcationSlotTable.h>
  64. #include <KtiHost.h>
  65. #include "SioRegs.h"
  66. #define LEGACY_8259_MASK_REGISTER_MASTER 0x21
  67. #define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
  68. extern GPIO_INIT_CONFIG mGpioTableTiogaPass[];
  69. extern UINTN mGpioTableSizeTiogaPass;
  70. extern PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS];
  71. extern PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS];
  72. extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[];
  73. extern UINT8 mIioBifurcationTableEntries;
  74. extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[];
  75. extern UINT8 mIioSlotTableEntries;
  76. extern ALL_LANES_EPARAM_LINK_INFO KtiTiogaPassAllLanesEparamTable[];
  77. extern UINT32 KtiTiogaPassAllLanesEparamTableSize;
  78. /**
  79. Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers.
  80. @param PeiServices - PeiService point.
  81. @param CpuIo - CpuIo PPI to read/write IO ports.
  82. @retval EFI_SUCCESS - Init succeed.
  83. **/
  84. VOID
  85. LpcSioEarlyInit (
  86. VOID
  87. )
  88. {
  89. PchLpcGenIoRangeSet ((0x600 & 0xFF0), 0x10, LPC_ESPI_FIRST_SLAVE);
  90. IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
  91. IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
  92. //
  93. //mailbox
  94. //
  95. IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
  96. IoWrite8 (SIO_DATA_PORT, SIO_MAILBOX);
  97. IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0);
  98. IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 >> 8));
  99. IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0);
  100. IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 & 0xFF));
  101. //
  102. //active mailbox
  103. //
  104. IoWrite8 (SIO_INDEX_PORT, ACTIVATE);
  105. IoWrite8 (SIO_DATA_PORT, 1);
  106. IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
  107. }
  108. VOID
  109. EarlyPlatformPchInit (
  110. IN EFI_PEI_SERVICES **PeiServices,
  111. IN SYSTEM_CONFIGURATION *SystemConfiguration,
  112. IN PCH_RC_CONFIGURATION *PchRcConfiguration
  113. )
  114. {
  115. UINT16 Data16;
  116. UINT8 Data8;
  117. UINT8 TcoRebootHappened;
  118. UINTN SpiBaseAddress;
  119. UINTN P2sbBase;
  120. DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - Start\n"));
  121. SpiBaseAddress = MmPciBase (
  122. DEFAULT_PCI_BUS_NUMBER_PCH,
  123. PCI_DEVICE_NUMBER_PCH_SPI,
  124. PCI_FUNCTION_NUMBER_PCH_SPI
  125. );
  126. //
  127. // Program bar
  128. //
  129. P2sbBase = MmPciBase (
  130. DEFAULT_PCI_BUS_NUMBER_PCH,
  131. PCI_DEVICE_NUMBER_PCH_P2SB,
  132. PCI_FUNCTION_NUMBER_PCH_P2SB
  133. );
  134. MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, PCH_PCR_BASE_ADDRESS);
  135. MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
  136. //
  137. // LPC I/O Configuration
  138. //
  139. PchLpcIoDecodeRangesSet (
  140. (V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) |
  141. (V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) |
  142. (V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA)
  143. );
  144. PchLpcIoEnableDecodingSet (
  145. B_PCH_LPC_IOE_ME2 |
  146. B_PCH_LPC_IOE_SE |
  147. B_PCH_LPC_IOE_ME1 |
  148. B_PCH_LPC_IOE_KE |
  149. B_PCH_LPC_IOE_HGE |
  150. B_PCH_LPC_IOE_LGE |
  151. B_PCH_LPC_IOE_FDE |
  152. B_PCH_LPC_IOE_PPE |
  153. B_PCH_LPC_IOE_CBE |
  154. B_PCH_LPC_IOE_CAE,
  155. LPC_ESPI_FIRST_SLAVE
  156. );
  157. //
  158. // Enable the upper 128-byte bank of RTC RAM
  159. //
  160. PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN);
  161. //
  162. // Disable the Watchdog timer expiration from causing a system reset
  163. //
  164. PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, B_PCH_PCR_ITSS_GIC_AME);
  165. //
  166. // Halt the TCO timer
  167. //
  168. Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT);
  169. Data16 |= B_PCH_TCO_CNT_TMR_HLT;
  170. IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16);
  171. //
  172. // Read the Second TO status bit
  173. //
  174. Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS);
  175. DEBUG((EFI_D_ERROR, "pre read:%x\n", Data8));
  176. Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS);
  177. DEBUG((EFI_D_ERROR, "read:%x\n", Data8));
  178. if ((Data8 & B_PCH_TCO2_STS_SECOND_TO) == B_PCH_TCO2_STS_SECOND_TO) {
  179. TcoRebootHappened = 1;
  180. } else {
  181. TcoRebootHappened = 0;
  182. }
  183. if (TcoRebootHappened) {
  184. DEBUG ((EFI_D_ERROR, "EarlyPlatformPchInit - TCO Second TO status bit is set. This might be a TCO reboot\n"));
  185. }
  186. //
  187. // Clear the Second TO status bit
  188. //
  189. Data8 |= B_PCH_TCO2_STS_SECOND_TO;
  190. IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, Data8);
  191. //
  192. // Disable SERR NMI and IOCHK# NMI in port 61
  193. //
  194. Data8 = IoRead8 (R_PCH_NMI_SC);
  195. Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN);
  196. IoWrite8 (R_PCH_NMI_SC, Data8);
  197. PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~B_PCH_PCR_ITSS_GIC_AME, 0);
  198. //
  199. // Clear EISS bit to allow for SPI use
  200. //
  201. MmioAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8)~B_PCH_SPI_BC_EISS);
  202. //
  203. // Disable/hide ME IDE-R device.
  204. //
  205. /*MmioWrite32(
  206. (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, 0x16, 0x02) + 0x54),
  207. 0x03
  208. );*/
  209. PchPcrAndThenOr32 (
  210. PID_PSF1,
  211. R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_PCR_PSFX_T0_SHDW_PCIEN,
  212. (UINT32)~0,
  213. B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS
  214. );
  215. /*MmioWrite32(
  216. (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, 0x16, 0x03) + 0x54),
  217. 0x03
  218. );*/
  219. PchPcrAndThenOr32 (
  220. PID_PSF1,
  221. R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PCR_PSFX_T0_SHDW_PCIEN,
  222. (UINT32)~0,
  223. B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS
  224. );
  225. PchPcrAndThenOr32 (
  226. PID_PSF2,
  227. R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE + R_PCH_PCR_PSFX_T0_SHDW_PCIEN,
  228. (UINT32)~0,
  229. B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS
  230. );
  231. DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - End\n"));
  232. }
  233. /**
  234. Initialize POC register by Variable.
  235. @param *SystemConfiguration - Pointer to SystemConfiguration variables.
  236. @retval EFI_SUCCESS - Success.
  237. **/
  238. EFI_STATUS
  239. UpdatePlatformInfo (
  240. IN SYSTEM_CONFIGURATION *SystemConfiguration,
  241. IN SOCKET_CONFIGURATION *SocketConfiguration
  242. )
  243. {
  244. SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCoreConfig;
  245. SOCKET_IIO_CONFIGURATION *SocketIioConfig;
  246. EFI_STATUS Status;
  247. UINT32 PcIoApicEnable;
  248. #if MAX_SOCKET <= 4
  249. UINTN Index;
  250. #endif
  251. DEBUG((EFI_D_ERROR, "platform update platform info entry\n"));
  252. SocketProcessorCoreConfig = &SocketConfiguration->SocketProcessorCoreConfiguration;
  253. SocketIioConfig = &SocketConfiguration->IioConfig;
  254. #if MAX_SOCKET <= 4
  255. for (Index = 0; Index < 24; Index++) {
  256. if (SocketIioConfig->DevPresIoApicIio[Index]) {
  257. PcIoApicEnable |= (1 << Index);
  258. }
  259. }
  260. #else
  261. // Enable all 32 IOxAPIC
  262. PcIoApicEnable = 0xFFFFFFFF;
  263. #endif
  264. Status = PcdSet32S (PcdPcIoApicEnable, PcIoApicEnable);
  265. ASSERT_EFI_ERROR (Status);
  266. //
  267. // Check to make sure TsegSize is in range, if not use default.
  268. //
  269. if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) {
  270. SocketProcessorCoreConfig->TsegSize = MAX_PROCESSOR_TSEG; // if out of range make default 64M
  271. }
  272. Status = PcdSet32S (PcdMemTsegSize, (0x400000 << SocketProcessorCoreConfig->TsegSize));
  273. ASSERT_EFI_ERROR (Status);
  274. if (SocketProcessorCoreConfig->IedSize > 0) {
  275. Status = PcdSet32S (PcdMemIedSize, (0x400000 << (SocketProcessorCoreConfig->IedSize - 1)));
  276. ASSERT_EFI_ERROR (Status);
  277. } else {
  278. Status = PcdSet32S (PcdMemIedSize, 0);
  279. ASSERT_EFI_ERROR (Status);
  280. }
  281. //
  282. // Minimum SMM range in TSEG should be larger than 3M
  283. //
  284. ASSERT (PcdGet32 (PcdMemTsegSize) - PcdGet32 (PcdMemIedSize) >= 0x300000);
  285. return EFI_SUCCESS;
  286. }
  287. /**
  288. Clear any SMI status or wake status left from boot.
  289. @retval EFI_SUCCESS The function completed successfully.
  290. **/
  291. EFI_STATUS
  292. ClearPchSmiAndWake (
  293. VOID
  294. )
  295. {
  296. UINT16 ABase;
  297. UINT16 Pm1Sts = 0;
  298. //
  299. // Clear any SMI or wake state from the boot
  300. //
  301. Pm1Sts |=
  302. (
  303. B_PCH_ACPI_PM1_STS_PWRBTN
  304. );
  305. PchAcpiBaseGet (&ABase);
  306. //
  307. // Write them back
  308. //
  309. IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts);
  310. //
  311. // Clear the GPE and PM enable
  312. //
  313. IoWrite16 (ABase + R_PCH_ACPI_PM1_EN, 0);
  314. IoWrite32 (ABase + R_PCH_ACPI_GPE0_EN_127_96, 0);
  315. return EFI_SUCCESS;
  316. }
  317. EFI_STATUS
  318. PlatformInitGpios (
  319. VOID
  320. )
  321. {
  322. EFI_STATUS Status;
  323. GPIO_INIT_CONFIG *GpioTable;
  324. UINTN TableSize;
  325. TableSize = mGpioTableSizeTiogaPass;
  326. DEBUG ((DEBUG_ERROR, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", TableSize, (TableSize/sizeof (GPIO_INIT_CONFIG)) ));
  327. GpioTable = mGpioTableTiogaPass;
  328. DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() TiogaPass Start.\n"));
  329. Status = GpioConfigurePads (TableSize/sizeof (GPIO_INIT_CONFIG), GpioTable);
  330. DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() TiogaPass End.\n"));
  331. return EFI_SUCCESS;
  332. }
  333. VOID
  334. SetUsbConfig (
  335. VOID
  336. )
  337. {
  338. EFI_STATUS Status;
  339. Status = PcdSet64S (PcdUsb20OverCurrentMappings, (UINT64)(UINTN)Usb20OverCurrentMappings);
  340. ASSERT_EFI_ERROR (Status);
  341. Status = PcdSet64S (PcdUsb30OverCurrentMappings, (UINT64)(UINTN)Usb30OverCurrentMappings);
  342. ASSERT_EFI_ERROR (Status);
  343. }
  344. VOID
  345. IioPortBifurcationConfig (
  346. VOID
  347. )
  348. {
  349. EFI_STATUS Status;
  350. Status = PcdSet64S (PcdIioBifurcationTable, (UINT64)(UINTN)mIioBifurcationTable);
  351. ASSERT_EFI_ERROR (Status);
  352. Status = PcdSet8S (PcdIioBifurcationTableEntries, mIioBifurcationTableEntries);
  353. ASSERT_EFI_ERROR (Status);
  354. Status = PcdSet64S (PcdIioSlotTable, (UINT64)(UINTN)mIioSlotTable);
  355. ASSERT_EFI_ERROR (Status);
  356. Status = PcdSet8S (PcdIioSlotTableEntries, mIioSlotTableEntries);
  357. ASSERT_EFI_ERROR (Status);
  358. }
  359. VOID
  360. AllLanesEparamTableConfig (
  361. VOID
  362. )
  363. {
  364. EFI_STATUS Status;
  365. Status = PcdSet64S (PcdAllLanesEparamTable, (UINT64)(UINTN)KtiTiogaPassAllLanesEparamTable);
  366. ASSERT_EFI_ERROR (Status);
  367. Status = PcdSet32S (PcdAllLanesEparamTableSize, KtiTiogaPassAllLanesEparamTableSize);
  368. ASSERT_EFI_ERROR (Status);
  369. }
  370. EFI_STATUS
  371. PchLanConfig (
  372. IN SYSTEM_CONFIGURATION *SystemConfig
  373. )
  374. {
  375. GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio);
  376. return EFI_SUCCESS;
  377. }
  378. /**
  379. Write to mask registers of master and slave 8259 PICs.
  380. **/
  381. VOID
  382. STATIC
  383. Mask8259Interrupts (
  384. VOID
  385. )
  386. {
  387. IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);
  388. IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);
  389. }
  390. EFI_STATUS
  391. EFIAPI
  392. TiogaPassBoardInitBeforeMemoryInit (
  393. VOID
  394. )
  395. {
  396. EFI_STATUS Status;
  397. SETUP_DATA SetupData;
  398. SYSTEM_CONFIGURATION SystemConfiguration;
  399. PCH_RC_CONFIGURATION PchRcConfiguration;
  400. SOCKET_CONFIGURATION SocketConfiguration;
  401. UINT16 ABase;
  402. UINT16 Pm1Sts;
  403. UINT32 Pm1Cnt;
  404. CONST EFI_PEI_SERVICES ** PeiServices;
  405. PeiServices = GetPeiServicesTablePointer ();
  406. ZeroMem (&SetupData, sizeof(SETUP_DATA));
  407. CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
  408. CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketCommonRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION));
  409. CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION));
  410. CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemoryConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION));
  411. CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
  412. CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGetPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
  413. CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM_CONFIGURATION));
  414. CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
  415. CopyMem (&SocketConfiguration, &(SetupData.SocketConfig), sizeof (SOCKET_CONFIGURATION));
  416. CopyMem (&PchRcConfiguration, &(SetupData.PchRcConfig), sizeof (PCH_RC_CONFIGURATION));
  417. CopyMem (&SystemConfiguration, &(SetupData.SystemConfig), sizeof (SYSTEM_CONFIGURATION));
  418. ///
  419. /// Set LPC SIO
  420. ///
  421. MmioOr16(
  422. (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_IOE),
  423. B_PCH_LPC_IOE_SE
  424. );
  425. LpcSioEarlyInit ();
  426. Status = PlatformInitGpios ();
  427. ASSERT_EFI_ERROR (Status);
  428. SetUsbConfig ();
  429. IioPortBifurcationConfig ();
  430. AllLanesEparamTableConfig ();
  431. ///
  432. /// Do Early PCH init
  433. ///
  434. EarlyPlatformPchInit ((EFI_PEI_SERVICES**)PeiServices, &SystemConfiguration, &PchRcConfiguration);
  435. ///
  436. /// Clear PCH SMI and Wake
  437. /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
  438. ///
  439. Status = ClearPchSmiAndWake();
  440. ASSERT_EFI_ERROR (Status);
  441. ///----------------------------------------------------------------------------------
  442. ///
  443. /// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE+00h) before memory
  444. /// initialization to determine if ME has reset the system while the host was in a sleep state.
  445. /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is taken by overwriting
  446. /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit.
  447. ///
  448. PchAcpiBaseGet (&ABase);
  449. Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
  450. if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) == 0) {
  451. Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT);
  452. Pm1Cnt |= V_PCH_ACPI_PM1_CNT_S5;
  453. IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
  454. }
  455. UpdatePlatformInfo (&SystemConfiguration, &SocketConfiguration);
  456. //
  457. // Do platform specific on-board Zoar init
  458. //
  459. PchLanConfig (&SystemConfiguration);
  460. //
  461. // The 8259 PIC is still functional and not masked by default even if APIC is
  462. // enabled. So need to disable all 8259 interrupts.
  463. //
  464. Mask8259Interrupts ();
  465. return EFI_SUCCESS;
  466. }
  467. /**
  468. Turn off system if needed.
  469. @param PeiServices Pointer to PEI Services
  470. @param CpuIo Pointer to CPU I/O Protocol
  471. @retval None.
  472. **/
  473. VOID
  474. CheckPowerOffNow (
  475. VOID
  476. )
  477. {
  478. UINT16 Pm1Sts;
  479. //
  480. // Read and check the ACPI registers
  481. //
  482. Pm1Sts = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS);
  483. DEBUG ((EFI_D_ERROR, "CheckPowerOffNow()- Pm1Sts= 0x%04x\n", Pm1Sts ));
  484. if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) {
  485. IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
  486. IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);
  487. IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);
  488. }
  489. }
  490. EFI_STATUS
  491. EFIAPI
  492. TiogaPassBoardInitAfterMemoryInit (
  493. VOID
  494. )
  495. {
  496. EFI_STATUS Status;
  497. EFI_BOOT_MODE BootMode;
  498. UINT16 Pm1Cnt;
  499. Status = PeiServicesGetBootMode (&BootMode);
  500. ASSERT_EFI_ERROR (Status);
  501. //
  502. // Check if user wants to turn off in PEI phase
  503. //
  504. if (BootMode != BOOT_ON_S3_RESUME) {
  505. CheckPowerOffNow ();
  506. } else {
  507. Pm1Cnt = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT);
  508. Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
  509. IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
  510. }
  511. return EFI_SUCCESS;
  512. }
  513. EFI_STATUS
  514. EFIAPI
  515. TiogaPassBoardDebugInit (
  516. VOID
  517. )
  518. {
  519. return EFI_SUCCESS;
  520. }
  521. EFI_BOOT_MODE
  522. EFIAPI
  523. TiogaPassBoardBootModeDetect (
  524. VOID
  525. )
  526. {
  527. return BOOT_WITH_FULL_CONFIGURATION;
  528. }