PchPlatformPolicy.h 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161
  1. /**
  2. **/
  3. /**
  4. Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. @file
  7. PchPlatformPolicy.h
  8. @brief
  9. PCH policy PPI produced by a platform driver specifying various
  10. expected PCH settings. This PPI is consumed by the PCH PEI modules.
  11. **/
  12. #ifndef PCH_PLATFORM_POLICY_H_
  13. #define PCH_PLATFORM_POLICY_H_
  14. //
  15. // External include files do NOT need to be explicitly specified in real EDKII
  16. // environment
  17. //
  18. #include "PchRegs.h"
  19. //
  20. #define PCH_PLATFORM_POLICY_PPI_GUID \
  21. { \
  22. 0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \
  23. }
  24. extern EFI_GUID gPchPlatformPolicyPpiGuid;
  25. ///
  26. /// Forward reference for ANSI C compatibility
  27. ///
  28. typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;
  29. ///
  30. /// PPI revision number
  31. /// Any backwards compatible changes to this PPI will result in an update in the revision number
  32. /// Major changes will require publication of a new PPI
  33. ///
  34. /// Revision 1: Original version
  35. ///
  36. #define PCH_PLATFORM_POLICY_PPI_REVISION_1 1
  37. #define PCH_PLATFORM_POLICY_PPI_REVISION_2 2
  38. #define PCH_PLATFORM_POLICY_PPI_REVISION_3 3
  39. #define PCH_PLATFORM_POLICY_PPI_REVISION_4 4
  40. #define PCH_PLATFORM_POLICY_PPI_REVISION_5 5
  41. //
  42. // Generic definitions for device enabling/disabling used by PCH code.
  43. //
  44. #define PCH_DEVICE_ENABLE 1
  45. #define PCH_DEVICE_DISABLE 0
  46. typedef struct {
  47. UINT8 ThermalDataReportEnable : 1; // OBSOLETE from Revision 5 !!! DO NOT USE !!!
  48. UINT8 MchTempReadEnable : 1;
  49. UINT8 PchTempReadEnable : 1;
  50. UINT8 CpuEnergyReadEnable : 1;
  51. UINT8 CpuTempReadEnable : 1;
  52. UINT8 Cpu2TempReadEnable : 1;
  53. UINT8 TsOnDimmEnable : 1;
  54. UINT8 Dimm1TempReadEnable : 1;
  55. UINT8 Dimm2TempReadEnable : 1;
  56. UINT8 Dimm3TempReadEnable : 1;
  57. UINT8 Dimm4TempReadEnable : 1;
  58. UINT8 Rsvdbits : 5;
  59. } PCH_THERMAL_REPORT_CONTROL;
  60. //
  61. // ---------------------------- HPET Config -----------------------------
  62. //
  63. typedef struct {
  64. BOOLEAN Enable; /// Determines if enable HPET function
  65. UINT32 Base; /// The HPET base address
  66. } PCH_HPET_CONFIG;
  67. ///
  68. /// ---------------------------- SATA Config -----------------------------
  69. ///
  70. typedef enum {
  71. PchSataModeIde,
  72. PchSataModeAhci,
  73. PchSataModeRaid,
  74. PchSataModeMax
  75. } PCH_SATA_MODE;
  76. ///
  77. /// ---------------------------- PCI Express Config -----------------------------
  78. ///
  79. typedef enum {
  80. PchPcieAuto,
  81. PchPcieGen1,
  82. PchPcieGen2
  83. } PCH_PCIE_SPEED;
  84. typedef struct {
  85. PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];
  86. } PCH_PCIE_CONFIG;
  87. ///
  88. /// ---------------------------- IO APIC Config -----------------------------
  89. ///
  90. typedef struct {
  91. UINT8 IoApicId;
  92. } PCH_IOAPIC_CONFIG;
  93. ///
  94. /// --------------------- Low Power Input Output Config ------------------------
  95. ///
  96. typedef struct {
  97. UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled
  98. UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled
  99. UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled
  100. UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled
  101. UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled
  102. UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled
  103. UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled
  104. UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled
  105. UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled
  106. UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled
  107. UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled
  108. UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled
  109. UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled
  110. UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled
  111. UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled
  112. UINT8 Rsvdbits : 2;
  113. } PEI_PCH_LPSS_CONFIG;
  114. ///
  115. /// ------------ General PCH Platform Policy PPI definition ------------
  116. ///
  117. struct _PCH_PLATFORM_POLICY_PPI {
  118. UINT8 Revision;
  119. UINT8 BusNumber; // Bus Number of the PCH device
  120. UINT32 SpiBase; // SPI Base Address.
  121. UINT32 PmcBase; // PMC Base Address.
  122. UINT32 SmbmBase; // SMB Memory Base Address.
  123. UINT32 IoBase; // IO Base Address.
  124. UINT32 IlbBase; // Intel Legacy Block Base Address.
  125. UINT32 PUnitBase; // PUnit Base Address.
  126. UINT32 Rcba; // Root Complex Base Address.
  127. UINT32 MphyBase; // MPHY Base Address.
  128. UINT16 AcpiBase; // ACPI I/O Base address.
  129. UINT16 GpioBase; // GPIO Base address
  130. PCH_HPET_CONFIG *HpetConfig;
  131. PCH_SATA_MODE SataMode;
  132. PCH_PCIE_CONFIG *PcieConfig;
  133. PCH_IOAPIC_CONFIG *IoApicConfig;
  134. PEI_PCH_LPSS_CONFIG *LpssConfig;
  135. BOOLEAN EnableRmh; // Determines if enable USB RMH function
  136. BOOLEAN EhciPllCfgEnable;
  137. };
  138. #endif