PchRegsUsb.h 3.4 KB

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  1. /**
  2. Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. @file
  5. PchRegsUsb.h
  6. @brief
  7. Register names for PCH USB devices.
  8. Conventions:
  9. - Prefixes:
  10. Definitions beginning with "R_" are registers
  11. Definitions beginning with "B_" are bits within registers
  12. Definitions beginning with "V_" are meaningful values of bits within the registers
  13. Definitions beginning with "S_" are register sizes
  14. Definitions beginning with "N_" are the bit position
  15. - In general, PCH registers are denoted by "_PCH_" in register names
  16. - Registers / bits that are different between PCH generations are denoted by
  17. "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  18. - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  19. at the end of the register/bit names
  20. - Registers / bits of new devices introduced in a PCH generation will be just named
  21. as "_PCH_" without <generation_name> inserted.
  22. **/
  23. #ifndef _PCH_REGS_USB_H_
  24. #define _PCH_REGS_USB_H_
  25. ///
  26. /// USB Definitions
  27. ///
  28. typedef enum {
  29. PchEhci1 = 0,
  30. PchEhciControllerMax
  31. } PCH_USB20_CONTROLLER_TYPE;
  32. #define PCH_USB_MAX_PHYSICAL_PORTS 4 /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.
  33. #define PCH_EHCI_MAX_PORTS 4 /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.
  34. #define PCH_HSIC_MAX_PORTS 2
  35. #define PCH_XHCI_MAX_USB3_PORTS 1
  36. #define PCI_DEVICE_NUMBER_PCH_USB 29
  37. #define PCI_FUNCTION_NUMBER_PCH_EHCI 0
  38. #define R_PCH_USB_VENDOR_ID 0x00 // Vendor ID
  39. #define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
  40. #define R_PCH_USB_DEVICE_ID 0x02 // Device ID
  41. #define V_PCH_USB_DEVICE_ID_0 0x0F34 // EHCI#1
  42. #define R_PCH_EHCI_SVID 0x2C // USB2 Subsystem Vendor ID
  43. #define B_PCH_EHCI_SVID 0xFFFF // USB2 Subsystem Vendor ID Mask
  44. #define R_PCH_EHCI_PWR_CNTL_STS 0x54 // Power Management Control / Status
  45. #define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status
  46. #define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale
  47. #define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) // Data Select
  48. #define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable
  49. #define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State
  50. #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0 0 // D0 State
  51. #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State
  52. ///
  53. /// USB3 (XHCI) related definitions
  54. ///
  55. #define PCI_DEVICE_NUMBER_PCH_XHCI 20
  56. #define PCI_FUNCTION_NUMBER_PCH_XHCI 0
  57. //
  58. /////
  59. ///// XHCI PCI Config Space registers
  60. /////
  61. #define R_PCH_XHCI_SVID 0x2C
  62. #define B_PCH_XHCI_SVID 0xFFFF
  63. #define R_PCH_XHCI_PWR_CNTL_STS 0x74
  64. #define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
  65. #define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
  66. #define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
  67. #define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
  68. #define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
  69. #define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
  70. #endif