PchRegsSmbus.h 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149
  1. /**
  2. Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. @file
  5. PchRegsSmbus.h
  6. @brief
  7. Register names for VLV Smbus Device.
  8. Conventions:
  9. - Prefixes:
  10. Definitions beginning with "R_" are registers
  11. Definitions beginning with "B_" are bits within registers
  12. Definitions beginning with "V_" are meaningful values of bits within the registers
  13. Definitions beginning with "S_" are register sizes
  14. Definitions beginning with "N_" are the bit position
  15. - In general, PCH registers are denoted by "_PCH_" in register names
  16. - Registers / bits that are different between PCH generations are denoted by
  17. "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  18. - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  19. at the end of the register/bit names
  20. - Registers / bits of new devices introduced in a PCH generation will be just named
  21. as "_PCH_" without <generation_name> inserted.
  22. **/
  23. #ifndef _PCH_REGS_SMBUS_H_
  24. #define _PCH_REGS_SMBUS_H_
  25. ///
  26. /// SMBus Controller Registers (D31:F3)
  27. ///
  28. #define PCI_DEVICE_NUMBER_PCH_SMBUS 31
  29. #define PCI_FUNCTION_NUMBER_PCH_SMBUS 3
  30. #define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID
  31. #define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
  32. #define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID
  33. #define V_PCH_SMBUS_DEVICE_ID 0x0F12
  34. #define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt
  35. #define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable
  36. #define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'
  37. #define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0'
  38. #define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0'
  39. #define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0'
  40. #define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0'
  41. #define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'
  42. #define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0'
  43. #define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'
  44. #define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable
  45. #define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable
  46. #define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar
  47. #define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address
  48. #define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator
  49. #define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID
  50. #define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID
  51. //
  52. // SMBus I/O Registers
  53. //
  54. #define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W
  55. #define B_PCH_SMBUS_HSTS_ALL 0xFF
  56. #define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status
  57. #define B_PCH_SMBUS_IUS BIT6 // In Use Status
  58. #define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert
  59. #define B_PCH_SMBUS_FAIL BIT4 // Failed
  60. #define B_PCH_SMBUS_BERR BIT3 // Bus Error
  61. #define B_PCH_SMBUS_DERR BIT2 // Device Error
  62. #define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)
  63. #define B_PCH_SMBUS_INTR BIT1 // Interrupt
  64. #define B_PCH_SMBUS_HBSY BIT0 // Host Busy
  65. #define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W
  66. #define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable
  67. #define B_PCH_SMBUS_START BIT6 // Start
  68. #define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte
  69. #define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command
  70. #define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process
  71. #define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read
  72. #define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block
  73. #define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call
  74. #define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data
  75. #define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data
  76. #define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte
  77. #define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick
  78. #define B_PCH_SMBUS_KILL BIT1 // Kill
  79. #define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable
  80. #define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W
  81. #define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted
  82. #define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W
  83. #define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave
  84. #define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write
  85. #define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read
  86. #define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write
  87. //
  88. #define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W
  89. #define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W
  90. #define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W
  91. #define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W
  92. #define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W
  93. #define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved)
  94. #define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W
  95. #define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC
  96. #define B_PCH_SMBUS_CRCE BIT0 // CRC Error
  97. //
  98. #define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W
  99. #define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer
  100. #define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC
  101. #define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W
  102. #define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported
  103. #define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported
  104. #define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported
  105. #define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W
  106. #define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control
  107. #define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status
  108. #define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status
  109. #define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC
  110. #define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status
  111. #define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W
  112. #define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
  113. #define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable
  114. #define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable
  115. #define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO
  116. #define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address
  117. #define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO
  118. #define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO
  119. #endif