PchRegsPcie.h 4.4 KB

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  1. /**
  2. Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. @file
  5. PchRegsPcie.h
  6. @brief
  7. Register names for VLV PCI-E root port devices
  8. Conventions:
  9. - Prefixes:
  10. Definitions beginning with "R_" are registers
  11. Definitions beginning with "B_" are bits within registers
  12. Definitions beginning with "V_" are meaningful values of bits within the registers
  13. Definitions beginning with "S_" are register sizes
  14. Definitions beginning with "N_" are the bit position
  15. - In general, PCH registers are denoted by "_PCH_" in register names
  16. - Registers / bits that are different between PCH generations are denoted by
  17. "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  18. - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  19. at the end of the register/bit names
  20. - Registers / bits of new devices introduced in a PCH generation will be just named
  21. as "_PCH_" without <generation_name> inserted.
  22. --*/
  23. #ifndef _PCH_REGS_PCIE_H_
  24. #define _PCH_REGS_PCIE_H_
  25. #define PCH_PCIE_MAX_ROOT_PORTS 4
  26. ///
  27. /// VLV PCI Express Root Ports (D28:F0~F3)
  28. ///
  29. #define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
  30. #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
  31. #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
  32. #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
  33. #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
  34. #define R_PCH_PCIE_ID 0x00 // Identifiers
  35. #define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID
  36. #define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1
  37. #define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2
  38. #define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3
  39. #define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4
  40. #define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID
  41. #define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID
  42. #define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer
  43. #define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer
  44. #define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number
  45. #define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number
  46. #define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number
  47. #define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer
  48. #define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer
  49. #define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status
  50. #define S_PCH_PCIE_SLCTL_SLSTS 4
  51. #define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed
  52. #define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State
  53. #define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State
  54. #define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed
  55. #define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed
  56. #define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected
  57. #define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable
  58. #define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control
  59. #define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable
  60. #define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable
  61. #define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable
  62. #define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs
  63. #define S_PCH_PCIE_SVID 4
  64. #define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier
  65. #define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier
  66. #endif