PchRegsLpss.h 26 KB

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  1. /*++
  2. Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. PchRegsLpss.h
  6. Abstract:
  7. Register names for VLV Low Input Output (LPSS) module.
  8. Conventions:
  9. - Prefixes:
  10. Definitions beginning with "R_" are registers
  11. Definitions beginning with "B_" are bits within registers
  12. Definitions beginning with "V_" are meaningful values of bits within the registers
  13. Definitions beginning with "S_" are register sizes
  14. Definitions beginning with "N_" are the bit position
  15. - In general, PCH registers are denoted by "_PCH_" in register names
  16. - Registers / bits that are different between PCH generations are denoted by
  17. "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  18. - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  19. at the end of the register/bit names
  20. - Registers / bits of new devices introduced in a PCH generation will be just named
  21. as "_PCH_" without <generation_name> inserted.
  22. --*/
  23. #ifndef _PCH_REGS_LPSS_H_
  24. #define _PCH_REGS_LPSS_H_
  25. //
  26. // Low Power Input Output (LPSS) Module Registers
  27. //
  28. //
  29. // LPSS DMAC Modules
  30. // PCI Config Space Registers
  31. //
  32. #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30
  33. #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24
  34. #define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0
  35. #define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID
  36. #define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID
  37. #define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID
  38. #define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command
  39. #define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA
  40. #define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA
  41. #define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List
  42. #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
  43. #define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable
  44. #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable
  45. #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable
  46. #define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable
  47. #define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code
  48. #define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code
  49. #define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID
  50. #define R_PCH_LPSS_DMAC_CLHB 0x0C
  51. #define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23
  52. #define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type
  53. #define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer
  54. #define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size
  55. #define R_PCH_LPSS_DMAC_BAR 0x10 // BAR
  56. #define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address
  57. #define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000
  58. #define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14
  59. #define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator
  60. #define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable
  61. #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
  62. #define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space
  63. #define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1
  64. #define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address
  65. #define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator
  66. #define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable
  67. #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
  68. #define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space
  69. #define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID
  70. #define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID
  71. #define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID
  72. #define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR
  73. #define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
  74. #define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer
  75. #define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power
  76. #define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt
  77. #define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency
  78. #define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000
  79. #define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin
  80. #define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line
  81. #define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID
  82. #define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support
  83. #define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version
  84. #define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability
  85. #define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability
  86. #define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status
  87. #define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status
  88. #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable
  89. #define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset
  90. #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State
  91. #define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID
  92. #define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID
  93. //
  94. // LPSS I2C Module
  95. // PCI Config Space Registers
  96. //
  97. #define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24
  98. #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1
  99. #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2
  100. #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3
  101. #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4
  102. #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5
  103. #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6
  104. #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7
  105. #define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID
  106. #define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID
  107. #define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID
  108. #define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
  109. #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
  110. #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
  111. #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
  112. #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
  113. #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
  114. #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
  115. #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
  116. #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
  117. #define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code
  118. #define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code
  119. #define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID
  120. #define R_PCH_LPSS_I2C_CLHB 0x0C
  121. #define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23
  122. #define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type
  123. #define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer
  124. #define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size
  125. #define R_PCH_LPSS_I2C_BAR 0x10 // BAR
  126. #define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
  127. #define V_PCH_LPSS_I2C_BAR_SIZE 0x1000
  128. #define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12
  129. #define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
  130. #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
  131. #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
  132. #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
  133. #define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
  134. #define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
  135. #define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
  136. #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
  137. #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
  138. #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
  139. #define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID
  140. #define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID
  141. #define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID
  142. #define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR
  143. #define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
  144. #define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer
  145. #define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power
  146. #define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt
  147. #define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency
  148. #define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000
  149. #define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin
  150. #define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line
  151. #define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID
  152. #define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support
  153. #define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version
  154. #define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability
  155. #define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability
  156. #define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status
  157. #define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status
  158. #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable
  159. #define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset
  160. #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State
  161. #define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID
  162. #define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID
  163. //
  164. // LPSS I2C Module
  165. // Memory Space Registers
  166. //
  167. #define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset
  168. #define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
  169. #define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
  170. //
  171. // LPSS PWM Modules
  172. // PCI Config Space Registers
  173. //
  174. #define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30
  175. #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1
  176. #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2
  177. #define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID
  178. #define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID
  179. #define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID
  180. #define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command
  181. #define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA
  182. #define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA
  183. #define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List
  184. #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
  185. #define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable
  186. #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable
  187. #define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable
  188. #define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable
  189. #define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code
  190. #define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code
  191. #define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID
  192. #define R_PCH_LPSS_PWM_CLHB 0x0C
  193. #define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23
  194. #define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type
  195. #define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer
  196. #define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size
  197. #define R_PCH_LPSS_PWM_BAR 0x10 // BAR
  198. #define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address
  199. #define V_PCH_LPSS_PWM_BAR_SIZE 0x1000
  200. #define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12
  201. #define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator
  202. #define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable
  203. #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
  204. #define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space
  205. #define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1
  206. #define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address
  207. #define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator
  208. #define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable
  209. #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
  210. #define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space
  211. #define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID
  212. #define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID
  213. #define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID
  214. #define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR
  215. #define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
  216. #define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer
  217. #define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power
  218. #define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt
  219. #define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency
  220. #define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000
  221. #define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin
  222. #define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line
  223. #define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID
  224. #define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support
  225. #define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version
  226. #define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability
  227. #define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability
  228. #define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status
  229. #define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status
  230. #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable
  231. #define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset
  232. #define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State
  233. #define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID
  234. #define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID
  235. //
  236. // LPSS PWM Module
  237. // Memory Space Registers
  238. //
  239. #define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset
  240. #define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
  241. #define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset
  242. //
  243. // LPSS HSUART Modules
  244. // PCI Config Space Registers
  245. //
  246. #define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30
  247. #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3
  248. #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4
  249. #define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID
  250. #define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID
  251. #define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID
  252. #define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command
  253. #define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA
  254. #define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA
  255. #define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List
  256. #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
  257. #define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable
  258. #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable
  259. #define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable
  260. #define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable
  261. #define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code
  262. #define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code
  263. #define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID
  264. #define R_PCH_LPSS_HSUART_CLHB 0x0C
  265. #define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23
  266. #define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type
  267. #define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer
  268. #define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size
  269. #define R_PCH_LPSS_HSUART_BAR 0x10 // BAR
  270. #define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address
  271. #define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000
  272. #define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12
  273. #define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator
  274. #define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable
  275. #define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type
  276. #define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space
  277. #define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1
  278. #define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address
  279. #define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator
  280. #define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable
  281. #define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type
  282. #define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space
  283. #define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID
  284. #define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID
  285. #define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID
  286. #define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR
  287. #define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
  288. #define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer
  289. #define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power
  290. #define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt
  291. #define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency
  292. #define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000
  293. #define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin
  294. #define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line
  295. #define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID
  296. #define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support
  297. #define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version
  298. #define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability
  299. #define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability
  300. #define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status
  301. #define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status
  302. #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable
  303. #define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset
  304. #define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State
  305. #define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID
  306. #define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID
  307. //
  308. // LPSS HSUART Module
  309. // Memory Space Registers
  310. //
  311. #define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters
  312. #define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
  313. #define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
  314. #define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
  315. #define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable
  316. #define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset
  317. #define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
  318. #define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset
  319. //
  320. // LPSS SPI Module
  321. // PCI Config Space Registers
  322. //
  323. #define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30
  324. #define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5
  325. #define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID
  326. #define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID
  327. #define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID
  328. #define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command
  329. #define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA
  330. #define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA
  331. #define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List
  332. #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
  333. #define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable
  334. #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable
  335. #define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable
  336. #define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable
  337. #define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code
  338. #define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code
  339. #define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID
  340. #define R_PCH_LPSS_SPI_CLHB 0x0C
  341. #define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23
  342. #define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type
  343. #define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer
  344. #define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size
  345. #define R_PCH_LPSS_SPI_BAR 0x10 // BAR
  346. #define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address
  347. #define V_PCH_LPSS_SPI_BAR_SIZE 0x1000
  348. #define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12
  349. #define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator
  350. #define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable
  351. #define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type
  352. #define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space
  353. #define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1
  354. #define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address
  355. #define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator
  356. #define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable
  357. #define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type
  358. #define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space
  359. #define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID
  360. #define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID
  361. #define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID
  362. #define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR
  363. #define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
  364. #define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer
  365. #define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power
  366. #define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt
  367. #define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency
  368. #define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000
  369. #define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin
  370. #define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line
  371. #define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID
  372. #define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support
  373. #define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version
  374. #define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability
  375. #define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability
  376. #define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status
  377. #define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status
  378. #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
  379. #define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset
  380. #define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State
  381. #define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID
  382. #define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID
  383. //
  384. // LPSS SPI Module
  385. // Memory Space Registers
  386. //
  387. #define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters
  388. #define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
  389. #define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
  390. #define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
  391. #define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable
  392. #define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset
  393. #define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
  394. #define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset
  395. #endif