I2CLib.h 7.5 KB

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  1. /*++
  2. Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. I2CRegs.h
  6. Abstract:
  7. Register Definitions for I2C Driver/PEIM.
  8. --*/
  9. #include <Uefi.h>
  10. #include <Library/IoLib.h>
  11. #ifndef I2C_REGS_A0_H
  12. #define I2C_REGS_A0_H
  13. //
  14. // FIFO write workaround value.
  15. //
  16. #define FIFO_WRITE_DELAY 2
  17. //
  18. // MMIO Register Definitions
  19. //
  20. #define R_IC_CON ( 0x00) // I2C Control
  21. #define B_IC_RESTART_EN BIT5
  22. #define B_IC_SLAVE_DISABLE BIT6
  23. #define V_SPEED_STANDARD 0x02
  24. #define V_SPEED_FAST 0x04
  25. #define V_SPEED_HIGH 0x06
  26. #define B_MASTER_MODE BIT0
  27. #define R_IC_TAR ( 0x04) // I2C Target Address
  28. #define IC_TAR_10BITADDR_MASTER BIT12
  29. #define R_IC_SAR ( 0x08) // I2C Slave Address
  30. #define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
  31. #define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
  32. #define B_READ_CMD BIT8 // 1 = read, 0 = write
  33. #define B_CMD_STOP BIT9 // 1 = STOP
  34. #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
  35. #define V_WRITE_CMD_MASK ( 0xFF)
  36. #define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
  37. #define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
  38. #define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
  39. #define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
  40. #define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
  41. #define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
  42. #define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
  43. #define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
  44. #define I2C_INTR_GEN_CALL BIT11 // General call received
  45. #define I2C_INTR_START_DET BIT10
  46. #define I2C_INTR_STOP_DET BIT9
  47. #define I2C_INTR_ACTIVITY BIT8
  48. #define I2C_INTR_TX_ABRT BIT6 // Set on NACK
  49. #define I2C_INTR_TX_EMPTY BIT4
  50. #define I2C_INTR_TX_OVER BIT3
  51. #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
  52. #define I2C_INTR_RX_OVER BIT1
  53. #define I2C_INTR_RX_UNDER BIT0
  54. #define R_IC_RAW_INTR_STAT ( 0x34) // I2C Raw Interrupt Status
  55. #define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
  56. #define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
  57. #define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
  58. #define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
  59. #define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
  60. #define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
  61. #define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
  62. #define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
  63. #define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
  64. #define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
  65. #define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
  66. #define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
  67. #define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
  68. #define R_IC_ENABLE ( 0x6C) // I2C Enable
  69. #define R_IC_STATUS ( 0x70) // I2C Status
  70. #define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
  71. #define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
  72. #define STAT_RFF BIT4 // RX FIFO is completely full
  73. #define STAT_RFNE BIT3 // RX FIFO is not empty
  74. #define STAT_TFE BIT2 // TX FIFO is completely empty
  75. #define STAT_TFNF BIT1 // TX FIFO is not full
  76. #define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
  77. #define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
  78. #define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
  79. #define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
  80. #define R_IC_DMA_CR ( 0x88) // DMA Control Register
  81. #define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
  82. #define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
  83. #define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
  84. #define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
  85. #define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
  86. #define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
  87. #define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
  88. #define R_IC_COMP_TYPE ( 0xFC) // Component Type
  89. #define R_IC_CLK_GATE ( 0xC0) // Clock Gate
  90. #define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
  91. #define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
  92. #define I2C_FS_SCL_HCNT_VALUE_100M 0x54
  93. #define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
  94. #define I2C_HS_SCL_HCNT_VALUE_100M 0x7
  95. #define I2C_HS_SCL_LCNT_VALUE_100M 0xE
  96. #define IC_TAR_10BITADDR_MASTER BIT12
  97. #define FIFO_SIZE 32
  98. #define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
  99. #define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
  100. #define I2C_INTR_GEN_CALL BIT11 // General call received
  101. #define I2C_INTR_START_DET BIT10
  102. #define I2C_INTR_STOP_DET BIT9
  103. #define I2C_INTR_ACTIVITY BIT8
  104. #define I2C_INTR_TX_ABRT BIT6 // Set on NACK
  105. #define I2C_INTR_TX_EMPTY BIT4
  106. #define I2C_INTR_TX_OVER BIT3
  107. #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
  108. #define I2C_INTR_RX_OVER BIT1
  109. #define I2C_INTR_RX_UNDER BIT0
  110. EFI_STATUS ProgramPciLpssI2C (
  111. IN UINT8 BusNo
  112. );
  113. EFI_STATUS ByteReadI2C_Basic(
  114. IN UINT8 BusNo,
  115. IN UINT8 SlaveAddress,
  116. IN UINTN ReadBytes,
  117. OUT UINT8 *ReadBuffer,
  118. IN UINT8 Start,
  119. IN UINT8 End
  120. );
  121. EFI_STATUS ByteWriteI2C_Basic(
  122. IN UINT8 BusNo,
  123. IN UINT8 SlaveAddress,
  124. IN UINTN WriteBytes,
  125. IN UINT8 *WriteBuffer,
  126. IN UINT8 Start,
  127. IN UINT8 End
  128. );
  129. EFI_STATUS ByteReadI2C(
  130. IN UINT8 BusNo,
  131. IN UINT8 SlaveAddress,
  132. IN UINT8 Offset,
  133. IN UINTN ReadBytes,
  134. OUT UINT8 *ReadBuffer
  135. );
  136. EFI_STATUS ByteWriteI2C(
  137. IN UINT8 BusNo,
  138. IN UINT8 SlaveAddress,
  139. IN UINT8 Offset,
  140. IN UINTN WriteBytes,
  141. IN UINT8 *WriteBuffer
  142. );
  143. #endif // I2C_REGS_A0_H