Mmc.h 14 KB

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  1. /*++
  2. Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. --*/
  5. /*++
  6. Module Name:
  7. MMC.h
  8. Abstract:
  9. Header file for Industry MMC 4.2 spec.
  10. --*/
  11. #ifndef _MMC_H
  12. #define _MMC_H
  13. #pragma pack(1)
  14. //
  15. //Command definition
  16. //
  17. #define CMD0 0
  18. #define CMD1 1
  19. #define CMD2 2
  20. #define CMD3 3
  21. #define CMD4 4
  22. #define CMD6 6
  23. #define CMD7 7
  24. #define CMD8 8
  25. #define CMD9 9
  26. #define CMD10 10
  27. #define CMD11 11
  28. #define CMD12 12
  29. #define CMD13 13
  30. #define CMD14 14
  31. #define CMD15 15
  32. #define CMD16 16
  33. #define CMD17 17
  34. #define CMD18 18
  35. #define CMD19 19
  36. #define CMD20 20
  37. #define CMD23 23
  38. #define CMD24 24
  39. #define CMD25 25
  40. #define CMD26 26
  41. #define CMD27 27
  42. #define CMD28 28
  43. #define CMD29 29
  44. #define CMD30 30
  45. #define CMD35 35
  46. #define CMD36 36
  47. #define CMD38 38
  48. #define CMD39 39
  49. #define CMD40 40
  50. #define CMD42 42
  51. #define CMD55 55
  52. #define CMD56 56
  53. #define GO_IDLE_STATE CMD0
  54. #define SEND_OP_COND CMD1
  55. #define ALL_SEND_CID CMD2
  56. #define SET_RELATIVE_ADDR CMD3
  57. #define SET_DSR CMD4
  58. #define SWITCH CMD6
  59. #define SELECT_DESELECT_CARD CMD7
  60. #define SEND_EXT_CSD CMD8
  61. #define SEND_CSD CMD9
  62. #define SEND_CID CMD10
  63. #define READ_DAT_UNTIL_STOP CMD11
  64. #define STOP_TRANSMISSION CMD12
  65. #define SEND_STATUS CMD13
  66. #define BUSTEST_R CMD14
  67. #define GO_INACTIVE_STATE CMD15
  68. #define SET_BLOCKLEN CMD16
  69. #define READ_SINGLE_BLOCK CMD17
  70. #define READ_MULTIPLE_BLOCK CMD18
  71. #define BUSTEST_W CMD19
  72. #define WRITE_DAT_UNTIL_STOP CMD20
  73. #define SET_BLOCK_COUNT CMD23
  74. #define WRITE_BLOCK CMD24
  75. #define WRITE_MULTIPLE_BLOCK CMD25
  76. #define PROGRAM_CID CMD26
  77. #define PROGRAM_CSD CMD27
  78. #define SET_WRITE_PROT CMD28
  79. #define CLR_WRITE_PROT CMD29
  80. #define SEND_WRITE_PROT CMD30
  81. #define ERASE_GROUP_START CMD35
  82. #define ERASE_GROUP_END CMD36
  83. #define ERASE CMD38
  84. #define FAST_IO CMD39
  85. #define GO_IRQ_STATE CMD40
  86. #define LOCK_UNLOCK CMD42
  87. #define APP_CMD CMD55
  88. #define GEN_CMD CMD56
  89. #define B_PERM_WP_DIS 0x10
  90. #define B_PWR_WP_EN 0x01
  91. #define US_PERM_WP_DIS 0x10
  92. #define US_PWR_WP_EN 0x01
  93. #define FREQUENCY_OD (400 * 1000)
  94. #define FREQUENCY_MMC_PP (26 * 1000 * 1000)
  95. #define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)
  96. #define DEFAULT_DSR_VALUE 0x404
  97. //
  98. //Registers definition
  99. //
  100. typedef struct {
  101. UINT32 Reserved0: 7; // 0
  102. UINT32 V170_V195: 1; // 1.70V - 1.95V
  103. UINT32 V200_V260: 7; // 2.00V - 2.60V
  104. UINT32 V270_V360: 9; // 2.70V - 3.60V
  105. UINT32 Reserved1: 5; // 0
  106. UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
  107. UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
  108. } OCR;
  109. typedef struct {
  110. UINT8 NotUsed: 1; // 1
  111. UINT8 CRC: 7; // CRC7 checksum
  112. UINT8 MDT; // Manufacturing date
  113. UINT32 PSN; // Product serial number
  114. UINT8 PRV; // Product revision
  115. UINT8 PNM[6]; // Product name
  116. UINT16 OID; // OEM/Application ID
  117. UINT8 MID; // Manufacturer ID
  118. } CID;
  119. typedef struct {
  120. UINT8 NotUsed: 1; // 1 [0:0]
  121. UINT8 CRC: 7; // CRC [7:1]
  122. UINT8 ECC: 2; // ECC code [9:8]
  123. UINT8 FILE_FORMAT: 2; // File format [11:10]
  124. UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
  125. UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
  126. UINT8 COPY: 1; // Copy flag (OTP) [14:14]
  127. UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
  128. UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]
  129. UINT16 Reserved0: 4; // 0 [20:17]
  130. UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
  131. UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
  132. UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
  133. UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
  134. UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
  135. UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]
  136. UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]
  137. UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]
  138. UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
  139. UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
  140. UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
  141. UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
  142. UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
  143. UINT32 C_SIZELow2: 2;// Device size [73:62]
  144. UINT32 C_SIZEHigh10: 10;// Device size [73:62]
  145. UINT32 Reserved1: 2; // 0 [75:74]
  146. UINT32 DSR_IMP: 1; // DSR implemented [76:76]
  147. UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
  148. UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
  149. UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
  150. UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
  151. UINT32 CCC: 12;// Card command classes [95:84]
  152. UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
  153. UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
  154. UINT8 TAAC ; // Data read access-time 1 [119:112]
  155. UINT8 Reserved2: 2; // 0 [121:120]
  156. UINT8 SPEC_VERS: 4; // System specification version [125:122]
  157. UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
  158. } CSD;
  159. typedef struct {
  160. UINT8 Reserved133_0[134]; // [133:0] 0
  161. UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode
  162. UINT8 Reserved135; // [135] 0
  163. UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address
  164. UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size
  165. UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size
  166. UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size
  167. UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size
  168. UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size
  169. UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting
  170. UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes
  171. UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size
  172. UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support
  173. UINT8 HPI_MGMT; // [161] HPI management
  174. UINT8 RST_n_FUNCTION; // [162] H/W reset function
  175. UINT8 BKOPS_EN; // [163] Enable background operations handshake
  176. UINT8 BKOPS_START; // [164] Manually start background operations
  177. UINT8 Reserved165; // [165] 0
  178. UINT8 WR_REL_PARAM; // [166] Write reliability parameter register
  179. UINT8 WR_REL_SET; // [167] Write reliability setting register
  180. UINT8 RPMB_SIZE_MULT; // [168] RPMB Size
  181. UINT8 FW_CONFIG; // [169] FW configuration
  182. UINT8 Reserved170; // [170] 0
  183. UINT8 USER_WP; // [171] User area write protection
  184. UINT8 Reserved172; // [172] 0
  185. UINT8 BOOT_WP; // [173] Boot area write protection
  186. UINT8 Reserved174; // [174] 0
  187. UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition
  188. UINT8 Reserved176; // [176] 0
  189. UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width
  190. UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection
  191. UINT8 PARTITION_CONFIG; // [179] Partition config
  192. UINT8 Reserved180; // [180] 0
  193. UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content
  194. UINT8 Reserved182; // [182] 0
  195. UINT8 BUS_WIDTH; // [183] Bus Width Mode
  196. UINT8 Reserved184; // [184] 0
  197. UINT8 HS_TIMING; // [185] High Speed Interface Timing
  198. UINT8 Reserved186; // [186] 0
  199. UINT8 POWER_CLASS; // [187] Power Class
  200. UINT8 Reserved188; // [188] 0
  201. UINT8 CMD_SET_REV; // [189] Command Set Revision
  202. UINT8 Reserved190; // [190] 0
  203. UINT8 CMD_SET; // [191] Command Set
  204. UINT8 EXT_CSD_REV; // [192] Extended CSD Revision
  205. UINT8 Reserved193; // [193] 0
  206. UINT8 CSD_STRUCTURE; // [194] CSD Structure Version
  207. UINT8 Reserved195; // [195] 0
  208. UINT8 CARD_TYPE; // [196] Card Type
  209. UINT8 Reserved197; // [197] 0
  210. UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing
  211. UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing
  212. UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V
  213. UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V
  214. UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V
  215. UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V
  216. UINT8 Reserved204; // [204] 0
  217. UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz
  218. UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz
  219. UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz
  220. UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz
  221. UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz
  222. UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz
  223. UINT8 Reserved211; // [211] 0
  224. UINT8 SEC_COUNT[4]; // [215:212] Sector Count
  225. UINT8 Reserved216; // [216] 0
  226. UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout
  227. UINT8 Reserved218; // [218] 0
  228. UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ)
  229. UINT8 S_C_VCC; // [220] Sleep current (VCC)
  230. UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size
  231. UINT8 REL_WR_SEC_C; // [222] Reliable write sector count
  232. UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout
  233. UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size
  234. UINT8 ACC_SIZE; // [225] Access size
  235. UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size
  236. UINT8 Reserved227; // [227] 0
  237. UINT8 BOOT_INFO; // [228] Boot information
  238. UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier
  239. UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier
  240. UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support
  241. UINT8 TRIM_MULT; // [232] TRIM Multiplier
  242. UINT8 Reserved233; // [233] 0
  243. UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz
  244. UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz
  245. UINT8 Reserved237_236[2]; // [237:236] 0
  246. UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V
  247. UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V
  248. UINT8 Reserved240; // [240] 0
  249. UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning
  250. UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors
  251. UINT8 BKOPS_STATUS; // [246] Background operations status
  252. UINT8 Reserved501_247[255]; // [501:247] 0
  253. UINT8 BKOPS_SUPPORT; // [502] Background operations support
  254. UINT8 HPI_FEATURES; // [503] HPI features
  255. UINT8 S_CMD_SET; // [504] Sector Count
  256. UINT8 Reserved511_505[7]; // [511:505] Sector Count
  257. } EXT_CSD;
  258. //
  259. //Card Status definition
  260. //
  261. typedef struct {
  262. UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode
  263. UINT32 Reserved1: 2; //Reserved for Application Specific commands
  264. UINT32 Reserved2: 1; //
  265. UINT32 SAPP_CMD: 1; //
  266. UINT32 Reserved3: 1; //Reserved
  267. UINT32 SWITCH_ERROR: 1; //
  268. UINT32 READY_FOR_DATA: 1; //
  269. UINT32 CURRENT_STATE: 4; //
  270. UINT32 ERASE_RESET: 1; //
  271. UINT32 Reserved4: 1; //Reserved
  272. UINT32 WP_ERASE_SKIP: 1; //
  273. UINT32 CID_CSD_OVERWRITE: 1; //
  274. UINT32 OVERRUN: 1; //
  275. UINT32 UNDERRUN: 1; //
  276. UINT32 ERROR: 1; //
  277. UINT32 CC_ERROR: 1; //
  278. UINT32 CARD_ECC_FAILED: 1; //
  279. UINT32 ILLEGAL_COMMAND: 1; //
  280. UINT32 COM_CRC_ERROR: 1; //
  281. UINT32 LOCK_UNLOCK_FAILED: 1; //
  282. UINT32 CARD_IS_LOCKED: 1; //
  283. UINT32 WP_VIOLATION: 1; //
  284. UINT32 ERASE_PARAM: 1; //
  285. UINT32 ERASE_SEQ_ERROR: 1; //
  286. UINT32 BLOCK_LEN_ERROR: 1; //
  287. UINT32 ADDRESS_MISALIGN: 1; //
  288. UINT32 ADDRESS_OUT_OF_RANGE:1; //
  289. } CARD_STATUS;
  290. typedef struct {
  291. UINT32 CmdSet: 3;
  292. UINT32 Reserved0: 5;
  293. UINT32 Value: 8;
  294. UINT32 Index: 8;
  295. UINT32 Access: 2;
  296. UINT32 Reserved1: 6;
  297. } SWITCH_ARGUMENT;
  298. #define CommandSet_Mode 0
  299. #define SetBits_Mode 1
  300. #define ClearBits_Mode 2
  301. #define WriteByte_Mode 3
  302. #define Idle_STATE 0
  303. #define Ready_STATE 1
  304. #define Ident_STATE 2
  305. #define Stby_STATE 3
  306. #define Tran_STATE 4
  307. #define Data_STATE 5
  308. #define Rcv_STATE 6
  309. #define Prg_STATE 7
  310. #define Dis_STATE 8
  311. #define Btst_STATE 9
  312. #pragma pack()
  313. #endif