VlvCommonDefinitions.h 9.2 KB

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  1. /*++
  2. Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. VlvCommonDefinitions.h
  6. Abstract:
  7. Macros to simplify and abstract the interface to PCI configuration.
  8. --*/
  9. ///
  10. /// PCI CONFIGURATION MAP REGISTER OFFSETS
  11. ///
  12. #ifndef PCI_VID
  13. #define PCI_VID 0x0000 ///< Vendor ID Register
  14. #define PCI_DID 0x0002 ///< Device ID Register
  15. #define PCI_CMD 0x0004 ///< PCI Command Register
  16. #define PCI_STS 0x0006 ///< PCI Status Register
  17. #define PCI_RID 0x0008 ///< Revision ID Register
  18. #define PCI_IFT 0x0009 ///< Interface Type
  19. #define PCI_SCC 0x000A ///< Sub Class Code Register
  20. #define PCI_BCC 0x000B ///< Base Class Code Register
  21. #define PCI_CLS 0x000C ///< Cache Line Size
  22. #define PCI_PMLT 0x000D ///< Primary Master Latency Timer
  23. #define PCI_HDR 0x000E ///< Header Type Register
  24. #define PCI_BIST 0x000F ///< Built in Self Test Register
  25. #define PCI_BAR0 0x0010 ///< Base Address Register 0
  26. #define PCI_BAR1 0x0014 ///< Base Address Register 1
  27. #define PCI_BAR2 0x0018 ///< Base Address Register 2
  28. #define PCI_PBUS 0x0018 ///< Primary Bus Number Register
  29. #define PCI_SBUS 0x0019 ///< Secondary Bus Number Register
  30. #define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register
  31. #define PCI_SMLT 0x001B ///< Secondary Master Latency Timer
  32. #define PCI_BAR3 0x001C ///< Base Address Register 3
  33. #define PCI_IOBASE 0x001C ///< I/O base Register
  34. #define PCI_IOLIMIT 0x001D ///< I/O Limit Register
  35. #define PCI_SECSTATUS 0x001E ///< Secondary Status Register
  36. #define PCI_BAR4 0x0020 ///< Base Address Register 4
  37. #define PCI_MEMBASE 0x0020 ///< Memory Base Register
  38. #define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register
  39. #define PCI_BAR5 0x0024 ///< Base Address Register 5
  40. #define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register
  41. #define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register
  42. #define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits
  43. #define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits
  44. #define PCI_SVID 0x002C ///< Subsystem Vendor ID
  45. #define PCI_SID 0x002E ///< Subsystem ID
  46. #define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register
  47. #define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register
  48. #define PCI_CAPP 0x0034 ///< Capabilities Pointer
  49. #define PCI_EROM 0x0038 ///< Expansion ROM Base Address
  50. #define PCI_INTLINE 0x003C ///< Interrupt Line Register
  51. #define PCI_INTPIN 0x003D ///< Interrupt Pin Register
  52. #define PCI_MAXGNT 0x003E ///< Max Grant Register
  53. #define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register
  54. #define PCI_MAXLAT 0x003F ///< Max Latency Register
  55. #endif
  56. //
  57. // Bit Difinitions
  58. //
  59. #ifndef BIT0
  60. #define BIT0 0x0001
  61. #define BIT1 0x0002
  62. #define BIT2 0x0004
  63. #define BIT3 0x0008
  64. #define BIT4 0x0010
  65. #define BIT5 0x0020
  66. #define BIT6 0x0040
  67. #define BIT7 0x0080
  68. #define BIT8 0x0100
  69. #define BIT9 0x0200
  70. #define BIT10 0x0400
  71. #define BIT11 0x0800
  72. #define BIT12 0x1000
  73. #define BIT13 0x2000
  74. #define BIT14 0x4000
  75. #define BIT15 0x8000
  76. #define BIT16 0x00010000
  77. #define BIT17 0x00020000
  78. #define BIT18 0x00040000
  79. #define BIT19 0x00080000
  80. #define BIT20 0x00100000
  81. #define BIT21 0x00200000
  82. #define BIT22 0x00400000
  83. #define BIT23 0x00800000
  84. #define BIT24 0x01000000
  85. #define BIT25 0x02000000
  86. #define BIT26 0x04000000
  87. #define BIT27 0x08000000
  88. #define BIT28 0x10000000
  89. #define BIT29 0x20000000
  90. #define BIT30 0x40000000
  91. #define BIT31 0x80000000
  92. #endif
  93. #ifndef _PCIACCESS_H_INCLUDED_
  94. #define _PCIACCESS_H_INCLUDED_
  95. #ifndef PCI_EXPRESS_BASE_ADDRESS
  96. #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000
  97. #endif
  98. #ifndef MmPciAddress
  99. #define MmPciAddress( Segment, Bus, Device, Function, Register ) \
  100. ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
  101. (UINTN)(Bus << 20) + \
  102. (UINTN)(Device << 15) + \
  103. (UINTN)(Function << 12) + \
  104. (UINTN)(Register) \
  105. )
  106. #endif
  107. //
  108. // UINT64
  109. //
  110. #define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \
  111. ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
  112. #define MmPci64( Segment, Bus, Device, Function, Register ) \
  113. *MmPci64Ptr( Segment, Bus, Device, Function, Register )
  114. #define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \
  115. MmPci64( Segment, Bus, Device, Function, Register ) = \
  116. (UINT64) ( \
  117. MmPci64( Segment, Bus, Device, Function, Register ) | \
  118. (UINT64)(OrData) \
  119. )
  120. #define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \
  121. MmPci64( Segment, Bus, Device, Function, Register ) = \
  122. (UINT64) ( \
  123. MmPci64( Segment, Bus, Device, Function, Register ) & \
  124. (UINT64)(AndData) \
  125. )
  126. #define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
  127. MmPci64( Segment, Bus, Device, Function, Register ) = \
  128. (UINT64) ( \
  129. ( MmPci64( Segment, Bus, Device, Function, Register ) & \
  130. (UINT64)(AndData) \
  131. ) | \
  132. (UINT64)(OrData) \
  133. )
  134. //
  135. // UINT32
  136. //
  137. #define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \
  138. ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )
  139. #define MmPci32( Segment, Bus, Device, Function, Register ) \
  140. *MmPci32Ptr( Segment, Bus, Device, Function, Register )
  141. #define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
  142. MmPci32( Segment, Bus, Device, Function, Register ) = \
  143. (UINT32) ( \
  144. MmPci32( Segment, Bus, Device, Function, Register ) | \
  145. (UINT32)(OrData) \
  146. )
  147. #define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
  148. MmPci32( Segment, Bus, Device, Function, Register ) = \
  149. (UINT32) ( \
  150. MmPci32( Segment, Bus, Device, Function, Register ) & \
  151. (UINT32)(AndData) \
  152. )
  153. #define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
  154. MmPci32( Segment, Bus, Device, Function, Register ) = \
  155. (UINT32) ( \
  156. ( MmPci32( Segment, Bus, Device, Function, Register ) & \
  157. (UINT32)(AndData) \
  158. ) | \
  159. (UINT32)(OrData) \
  160. )
  161. //
  162. // UINT16
  163. //
  164. #define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \
  165. ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
  166. #define MmPci16( Segment, Bus, Device, Function, Register ) \
  167. *MmPci16Ptr( Segment, Bus, Device, Function, Register )
  168. #define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
  169. MmPci16( Segment, Bus, Device, Function, Register ) = \
  170. (UINT16) ( \
  171. MmPci16( Segment, Bus, Device, Function, Register ) | \
  172. (UINT16)(OrData) \
  173. )
  174. #define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
  175. MmPci16( Segment, Bus, Device, Function, Register ) = \
  176. (UINT16) ( \
  177. MmPci16( Segment, Bus, Device, Function, Register ) & \
  178. (UINT16)(AndData) \
  179. )
  180. #define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
  181. MmPci16( Segment, Bus, Device, Function, Register ) = \
  182. (UINT16) ( \
  183. ( MmPci16( Segment, Bus, Device, Function, Register ) & \
  184. (UINT16)(AndData) \
  185. ) | \
  186. (UINT16)(OrData) \
  187. )
  188. //
  189. // UINT8
  190. //
  191. #define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \
  192. ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
  193. #define MmPci8( Segment, Bus, Device, Function, Register ) \
  194. *MmPci8Ptr( Segment, Bus, Device, Function, Register )
  195. #define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
  196. MmPci8( Segment, Bus, Device, Function, Register ) = \
  197. (UINT8) ( \
  198. MmPci8( Segment, Bus, Device, Function, Register ) | \
  199. (UINT8)(OrData) \
  200. )
  201. #define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
  202. MmPci8( Segment, Bus, Device, Function, Register ) = \
  203. (UINT8) ( \
  204. MmPci8( Segment, Bus, Device, Function, Register ) & \
  205. (UINT8)(AndData) \
  206. )
  207. #define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
  208. MmPci8( Segment, Bus, Device, Function, Register ) = \
  209. (UINT8) ( \
  210. ( MmPci8( Segment, Bus, Device, Function, Register ) & \
  211. (UINT8)(AndData) \
  212. ) | \
  213. (UINT8)(OrData) \
  214. )
  215. #endif