PlatformMemoryRange.h 5.1 KB

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  1. /*++
  2. Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. PlatformMemoryRange.h
  6. Abstract:
  7. Platform Memory Range PPI as defined in EFI 2.0
  8. PPI for reserving special purpose memory ranges.
  9. --*/
  10. //
  11. //
  12. #ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
  13. #define _PEI_PLATFORM_MEMORY_RANGE_H_
  14. #define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
  15. { \
  16. 0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
  17. }
  18. typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ;
  19. #define PEI_MEMORY_RANGE_OPTION_ROM UINT32
  20. #define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF
  21. #define PEI_MR_OPTION_ROM_NONE 0x00000000
  22. #define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
  23. #define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
  24. #define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
  25. #define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
  26. #define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
  27. #define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
  28. #define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
  29. #define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
  30. #define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
  31. #define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
  32. #define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
  33. #define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
  34. #define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
  35. #define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
  36. #define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
  37. #define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
  38. //
  39. // SMRAM Memory Range
  40. //
  41. #define PEI_MEMORY_RANGE_SMRAM UINT32
  42. #define PEI_MR_SMRAM_ALL 0xFFFFFFFF
  43. #define PEI_MR_SMRAM_NONE 0x00000000
  44. #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
  45. #define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
  46. #define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
  47. #define PEI_MR_SMRAM_HSEG_MASK 0x00020000
  48. #define PEI_MR_SMRAM_TSEG_MASK 0x00040000
  49. //
  50. // If adding additional entries, SMRAM Size
  51. // is a multiple of 128KB.
  52. //
  53. #define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
  54. #define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001
  55. #define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002
  56. #define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004
  57. #define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008
  58. #define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010
  59. #define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020
  60. #define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040
  61. #define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
  62. #define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001
  63. #define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001
  64. #define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001
  65. #define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001
  66. #define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002
  67. #define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002
  68. #define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004
  69. #define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004
  70. #define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008
  71. #define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
  72. //
  73. // Graphics Memory Range
  74. //
  75. #define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32
  76. #define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF
  77. #define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000
  78. #define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000
  79. //
  80. // If adding additional entries, Graphics Memory Size
  81. // is a multiple of 512KB.
  82. //
  83. #define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF
  84. #define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
  85. #define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001
  86. #define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002
  87. #define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002
  88. #define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008
  89. #define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008
  90. #define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010
  91. #define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010
  92. #define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020
  93. #define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020
  94. #define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040
  95. #define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040
  96. #define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060
  97. #define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060
  98. #define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080
  99. #define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080
  100. #define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
  101. #define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100
  102. #define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
  103. #define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200
  104. //
  105. // Pci Memory Hole
  106. //
  107. #define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
  108. #define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001
  109. typedef
  110. EFI_STATUS
  111. (EFIAPI *PEI_CHOOSE_RANGES) (
  112. IN EFI_PEI_SERVICES **PeiServices,
  113. IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,
  114. IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,
  115. IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,
  116. IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,
  117. IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask
  118. );
  119. struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
  120. PEI_CHOOSE_RANGES ChooseRanges;
  121. };
  122. extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
  123. #endif