Cpu0Tst.asl 11 KB

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  1. /*-----------------------------------------------------------------------------
  2. -------------------------------------------------------------------------------
  3. Intel Silvermont Processor Power Management BIOS Reference Code
  4. Copyright (c) 2006 - 2014, Intel Corporation
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. Filename: CPU0TST.ASL
  7. Revision: Refer to Readme
  8. Date: Refer to Readme
  9. --------------------------------------------------------------------------------
  10. -------------------------------------------------------------------------------
  11. This Processor Power Management BIOS Source Code is furnished under license
  12. and may only be used or copied in accordance with the terms of the license.
  13. The information in this document is furnished for informational use only, is
  14. subject to change without notice, and should not be construed as a commitment
  15. by Intel Corporation. Intel Corporation assumes no responsibility or liability
  16. for any errors or inaccuracies that may appear in this document or any
  17. software that may be provided in association with this document.
  18. Except as permitted by such license, no part of this document may be
  19. reproduced, stored in a retrieval system, or transmitted in any form or by
  20. any means without the express written consent of Intel Corporation.
  21. WARNING: You are authorized and licensed to install and use this BIOS code
  22. ONLY on an IST PC. This utility may damage any system that does not
  23. meet these requirements.
  24. An IST PC is a computer which
  25. (1) Is capable of seamlessly and automatically transitioning among
  26. multiple performance states (potentially operating at different
  27. efficiency ratings) based upon power source changes, end user
  28. preference, processor performance demand, and thermal conditions; and
  29. (2) Includes an Intel Pentium II processors, Intel Pentium III
  30. processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  31. Processor-M, Intel Pentium M Processor, or any other future Intel
  32. processors that incorporates the capability to transition between
  33. different performance states by altering some, or any combination of,
  34. the following processor attributes: core voltage, core frequency, bus
  35. frequency, number of processor cores available, or any other attribute
  36. that changes the efficiency (instructions/unit time-power) at which the
  37. processor operates.
  38. -------------------------------------------------------------------------------
  39. -------------------------------------------------------------------------------
  40. NOTES:
  41. (1) <TODO> - IF the trap range and port definitions do not match those
  42. specified by this reference code, this file must be modified IAW the
  43. individual implmentation.
  44. --------------------------------------------------------------------------------
  45. ------------------------------------------------------------------------------*/
  46. DefinitionBlock(
  47. "CPU0TST.aml",
  48. "SSDT",
  49. 0x01,
  50. "PmRef",
  51. "Cpu0Tst",
  52. 0x3000
  53. )
  54. {
  55. External(\_PR.CPU0, DeviceObj)
  56. External(PDC0)
  57. External(CFGD)
  58. External(_PSS)
  59. Scope(\_PR.CPU0)
  60. {
  61. Name(_TPC, 0) // All T-States are available
  62. //
  63. // T-State Control/Status interface
  64. //
  65. Method(_PTC, 0)
  66. {
  67. //
  68. // IF OSPM is capable of direct access to MSR
  69. // Report MSR interface
  70. // ELSE
  71. // Report I/O interface
  72. //
  73. // PDCx[2] = OSPM is capable of direct access to On
  74. // Demand throttling MSR
  75. //
  76. If(And(PDC0, 0x0004)) {
  77. Return(Package() {
  78. ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
  79. ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
  80. })
  81. }
  82. }
  83. // _TSS package for I/O port based T-State control
  84. // "Power" fields are replaced with real values by the first
  85. // call of _TSS method.
  86. //
  87. Name(TSSI, Package() {
  88. Package(){100, 1000, 0, 0x00, 0},
  89. Package(){ 88, 875, 0, 0x0F, 0},
  90. Package(){ 75, 750, 0, 0x0E, 0},
  91. Package(){ 63, 625, 0, 0x0D, 0},
  92. Package(){ 50, 500, 0, 0x0C, 0},
  93. Package(){ 38, 375, 0, 0x0B, 0},
  94. Package(){ 25, 250, 0, 0x0A, 0},
  95. Package(){ 13, 125, 0, 0x09, 0}
  96. })
  97. // _TSS package for MSR based T-State control
  98. // "Power" fields are replaced with real values by the first
  99. // call of _TSS method.
  100. //
  101. Name(TSSM, Package() {
  102. Package(){100, 1000, 0, 0x00, 0},
  103. Package(){ 88, 875, 0, 0x1E, 0},
  104. Package(){ 75, 750, 0, 0x1C, 0},
  105. Package(){ 63, 625, 0, 0x1A, 0},
  106. Package(){ 50, 500, 0, 0x18, 0},
  107. Package(){ 38, 375, 0, 0x16, 0},
  108. Package(){ 25, 250, 0, 0x14, 0},
  109. Package(){ 13, 125, 0, 0x12, 0}
  110. })
  111. Name(TSSF, 0) // Flag for TSSI/TSSM initialization
  112. Method(_TSS, 0)
  113. {
  114. // Update "Power" fields of TSSI/TSSM with the LFM
  115. // power data IF _PSS is available
  116. //
  117. IF (LAnd(LNot(TSSF),CondRefOf(_PSS)))
  118. {
  119. Store(_PSS, Local0)
  120. Store(SizeOf(Local0), Local1) // _PSS size
  121. Decrement(Local1) // Index of LFM
  122. Store(DerefOf(Index(DerefOf(Index(Local0,Local1)),1)), Local2) // LFM Power
  123. Store(0, Local3)
  124. While(LLess(Local3, SizeOf(TSSI)))
  125. {
  126. Store(Divide(Multiply(Local2, Subtract(8, Local3)), 8),
  127. Local4) // Power for this TSSI/TSSM entry
  128. Store(Local4,Index(DerefOf(Index(TSSI,Local3)),1))
  129. Store(Local4,Index(DerefOf(Index(TSSM,Local3)),1))
  130. Increment(Local3)
  131. }
  132. Store(Ones, TSSF) // TSSI/TSSM are updated
  133. }
  134. //
  135. // IF OSPM is capable of direct access to MSR
  136. // Report TSSM
  137. // ELSE
  138. // Report TSSI
  139. //
  140. If(And(PDC0, 0x0004))
  141. {
  142. Return(TSSM)
  143. }
  144. Return(TSSI)
  145. }
  146. Method(_TDL, 0)
  147. {
  148. Store ("Cpu0: _TDL Called", Debug)
  149. Name ( LFMI, 0)
  150. Store (SizeOf(TSSM), LFMI)
  151. Decrement(LFMI) // Index of LFM entry in TSSM
  152. Return(LFMI)
  153. }
  154. //
  155. // T-State Dependency
  156. //
  157. Method(_TSD, 0)
  158. {
  159. //
  160. // IF four cores are supported/enabled && !(direct access to MSR)
  161. // Report 4 processors and SW_ANY as the coordination type
  162. // ELSE IF two cores are supported/enabled && !(direct access to MSR)
  163. // Report 2 processors and SW_ANY as the coordination type
  164. // ELSE
  165. // Report 1 processor and SW_ALL as the coordination type
  166. //
  167. // CFGD[23] = Four cores enabled
  168. // CFGD[24] = Two or more cores enabled
  169. // PDCx[2] = OSPM is capable of direct access to On
  170. // Demand throttling MSR
  171. //
  172. If(LAnd(And(CFGD,0x0800000),LNot(And(PDC0,4))))
  173. {
  174. Return(Package(){ // SW_ANY
  175. Package(){
  176. 5, // # entries.
  177. 0, // Revision.
  178. 0, // Domain #.
  179. 0xFD, // Coord Type- SW_ANY
  180. 4 // # processors.
  181. }
  182. })
  183. }
  184. If(LAnd(And(CFGD,0x1000000),LNot(And(PDC0,4))))
  185. {
  186. Return(Package(){ // SW_ANY
  187. Package(){
  188. 5, // # entries.
  189. 0, // Revision.
  190. 0, // Domain #.
  191. 0xFD, // Coord Type- SW_ANY
  192. 2 // # processors.
  193. }
  194. })
  195. }
  196. Return(Package(){ // SW_ALL
  197. Package(){
  198. 5, // # entries.
  199. 0, // Revision.
  200. 0, // Domain #.
  201. 0xFC, // Coord Type- SW_ALL
  202. 1 // # processors.
  203. }
  204. })
  205. }
  206. }
  207. } // End of Definition Block