Cpu0Cst.asl 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274
  1. /*-----------------------------------------------------------------------------
  2. -------------------------------------------------------------------------------
  3. Intel Silvermont Processor Power Management BIOS Reference Code
  4. Copyright (c) 2006 - 2014, Intel Corporation
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. Filename: CPU0CST.ASL
  7. Revision: Refer to Readme
  8. Date: Refer to Readme
  9. --------------------------------------------------------------------------------
  10. -------------------------------------------------------------------------------
  11. This Processor Power Management BIOS Source Code is furnished under license
  12. and may only be used or copied in accordance with the terms of the license.
  13. The information in this document is furnished for informational use only, is
  14. subject to change without notice, and should not be construed as a commitment
  15. by Intel Corporation. Intel Corporation assumes no responsibility or liability
  16. for any errors or inaccuracies that may appear in this document or any
  17. software that may be provided in association with this document.
  18. Except as permitted by such license, no part of this document may be
  19. reproduced, stored in a retrieval system, or transmitted in any form or by
  20. any means without the express written consent of Intel Corporation.
  21. WARNING: You are authorized and licensed to install and use this BIOS code
  22. ONLY on an IST PC. This utility may damage any system that does not
  23. meet these requirements.
  24. An IST PC is a computer which
  25. (1) Is capable of seamlessly and automatically transitioning among
  26. multiple performance states (potentially operating at different
  27. efficiency ratings) based upon power source changes, END user
  28. preference, processor performance demand, and thermal conditions; and
  29. (2) Includes an Intel Pentium II processors, Intel Pentium III
  30. processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  31. Processor-M, Intel Pentium M Processor, or any other future Intel
  32. processors that incorporates the capability to transition between
  33. different performance states by altering some, or any combination of,
  34. the following processor attributes: core voltage, core frequency, bus
  35. frequency, number of processor cores available, or any other attribute
  36. that changes the efficiency (instructions/unit time-power) at which the
  37. processor operates.
  38. -------------------------------------------------------------------------------
  39. -------------------------------------------------------------------------------
  40. NOTES:
  41. (1) <TODO> - IF the trap range and port definitions do not match those
  42. specified by this reference code, this file must be modified IAW the
  43. individual implmentation.
  44. --------------------------------------------------------------------------------
  45. ------------------------------------------------------------------------------*/
  46. DefinitionBlock (
  47. "CPU0CST.aml",
  48. "SSDT",
  49. 1,
  50. "PmRef",
  51. "Cpu0Cst",
  52. 0x3001
  53. )
  54. {
  55. External(\_PR.CPU0, DeviceObj)
  56. External(PWRS)
  57. External(CFGD)
  58. External(PDC0)
  59. Scope(\_PR.CPU0)
  60. {
  61. OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG
  62. Field (DEB0, ByteAcc,NoLock,Preserve) //DBG
  63. { DBG8, 8,} //DBG
  64. Method (_CST, 0)
  65. {
  66. Store(0x60,DBG8) //DBG
  67. // IF CMP is supported, but independent C-States beyond C1 are
  68. // not supported; return C1 Halt and rely on BIOS based software
  69. // coordination
  70. //
  71. // CFGD[24] = CMP support
  72. // PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems
  73. //
  74. // Note: SMI will be generated when both processor enter the
  75. // Halt state.
  76. //
  77. If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
  78. {
  79. Store(0x61,DBG8) //DBG
  80. Return(Package() {
  81. 1,
  82. Package()
  83. { // C1 halt, but with BIOS coordination
  84. ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
  85. 1,
  86. 157,
  87. 1000
  88. }
  89. })
  90. }
  91. // IF MWAIT extensions are supported, use them.
  92. //
  93. // IF C6 capable/enabled AND Battery
  94. // Report MWAIT C1, C2, C6 w/ BM_STS avoidance
  95. // ELSE IF C4 capable/enabled AND Battery
  96. // Report MWAIT C1, C2, C4 w/ BM_STS avoidance
  97. // ELSE IF C3 capable/enabled
  98. // Report MWAIT C1, C2, C3 w/ BM_STS avoidance
  99. // ELSE IF C2 capable/enabled
  100. // Report MWAIT C1, C2
  101. // ELSE
  102. // Report MWAIT C1
  103. //
  104. // CFGD[21] = 1 - MWAIT extensions supported
  105. // CFGD[13] = 1 - C7 Capable/Enabled
  106. // CFGD[12] = 1 - C6S Capable/Enabled
  107. // CFGD[11] = 1 - C6 Capable/Enabled
  108. // CFGD[7] = 1 - C4 Capable/Enabled
  109. // CFGD[5] = 1 - C3 Capable/Enabled
  110. // PDCx[9] = 1 - OS supports MWAIT extensions
  111. // PDCx[8] = 1 - OS supports MWAIT for C1
  112. // (Inferred from PDCx[9] = 1.)
  113. // PDCx[4] = 1 - OS supports independent C2/C3 in MP systems
  114. // or
  115. // NOT CMP (Inferred from previous check.)
  116. //
  117. If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
  118. {
  119. //
  120. // <TODO> The implementor may wish to only report C1-C2
  121. // when on AC power. In this case, the IF clause below can
  122. // be modified to something like:
  123. //
  124. // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"
  125. //
  126. // Which uses the power state of the system (PWRS) to
  127. // determine whether to allow deepers states.
  128. //
  129. // IF C7 supported AND on battery
  130. // report MWAIT C1, C6, C7
  131. //
  132. // CFGD[13] = C7 Capable/Enabled
  133. // CFGD[11] = C6 Capable/Enabled
  134. //
  135. If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))
  136. {
  137. Store(0x77,DBG8) //DBG
  138. Return( Package()
  139. {
  140. 3,
  141. Package()
  142. { // C1, MWAIT
  143. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
  144. 1,
  145. 1,
  146. 1000
  147. },
  148. Package()
  149. {
  150. // C6, MWAIT Extension with Incremental L2 Shrink
  151. // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
  152. // C6, MWAIT Extension with No L2 Shrink
  153. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
  154. 2,
  155. 500,
  156. 10
  157. },
  158. Package()
  159. {
  160. // C7, MWAIT Extension with Full L2 Shrink
  161. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},
  162. 3,
  163. 1500, //PnP setting, 1.5 ms for worst-case exit latency
  164. 10
  165. }
  166. })
  167. }
  168. If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))
  169. {
  170. Store(0x67,DBG8) //DBG
  171. Return( Package()
  172. {
  173. 3,
  174. Package()
  175. { // C1, MWAIT
  176. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
  177. 1,
  178. 1,
  179. 1000
  180. },
  181. Package()
  182. {
  183. // C6, MWAIT Extension with Incremental L2 Shrink
  184. // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
  185. // C6 = C6NS, MWAIT Extension with No L2 Shrink
  186. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
  187. 2,
  188. 500,
  189. 10
  190. },
  191. Package()
  192. {
  193. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},
  194. 3,
  195. 1500, //PnP setting, 1.5 ms for worst-case exit latency
  196. 10
  197. }
  198. })
  199. }
  200. If(And(CFGD,0x800)) // Setup Max C-State = C6
  201. {
  202. Store(0x76,DBG8) //DBG
  203. Return( Package()
  204. {
  205. 2,
  206. Package()
  207. { // C1, MWAIT
  208. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
  209. 1,
  210. 1,
  211. 1000
  212. },
  213. Package()
  214. {
  215. // C6, MWAIT Extension with Incremental L2 Shrink
  216. // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
  217. // C6, MWAIT Extension with No L2 Shrink
  218. ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
  219. 2,
  220. 500,
  221. 10
  222. }
  223. })
  224. }
  225. //
  226. // IF no deeper C-States are supported; report MWAIT C1.
  227. //
  228. Store(0x71,DBG8) //DBG
  229. Return(Package()
  230. {
  231. 1,
  232. Package()
  233. { // C1, MWAIT
  234. ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
  235. 1,
  236. 1,
  237. 1000
  238. }
  239. })
  240. }
  241. }
  242. }
  243. }