ApTst.asl 11 KB

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  1. /*-----------------------------------------------------------------------------
  2. -------------------------------------------------------------------------------
  3. Intel Platform Processor Power Management BIOS Reference Code
  4. Copyright (c) 2007 - 2014, Intel Corporation
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. Filename: APTST.ASL
  7. Revision: Refer to Readme
  8. Date: Refer to Readme
  9. --------------------------------------------------------------------------------
  10. -------------------------------------------------------------------------------
  11. This Processor Power Management BIOS Source Code is furnished under license
  12. and may only be used or copied in accordance with the terms of the license.
  13. The information in this document is furnished for informational use only, is
  14. subject to change without notice, and should not be construed as a commitment
  15. by Intel Corporation. Intel Corporation assumes no responsibility or liability
  16. for any errors or inaccuracies that may appear in this document or any
  17. software that may be provided in association with this document.
  18. Except as permitted by such license, no part of this document may be
  19. reproduced, stored in a retrieval system, or transmitted in any form or by
  20. any means without the express written consent of Intel Corporation.
  21. WARNING: You are authorized and licensed to install and use this BIOS code
  22. ONLY on an IST PC. This utility may damage any system that does not
  23. meet these requirements.
  24. An IST PC is a computer which
  25. (1) Is capable of seamlessly and automatically transitioning among
  26. multiple performance states (potentially operating at different
  27. efficiency ratings) based upon power source changes, END user
  28. preference, processor performance demand, and thermal conditions; and
  29. (2) Includes an Intel Pentium II processors, Intel Pentium III
  30. processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  31. Processor-M, Intel Pentium M Processor, or any other future Intel
  32. processors that incorporates the capability to transition between
  33. different performance states by altering some, or any combination of,
  34. the following processor attributes: core voltage, core frequency, bus
  35. frequency, number of processor cores available, or any other attribute
  36. that changes the efficiency (instructions/unit time-power) at which the
  37. processor operates.
  38. -------------------------------------------------------------------------------
  39. -------------------------------------------------------------------------------
  40. NOTES:
  41. (1) <TODO> - IF the trap range and port definitions do not match those
  42. specified by this reference code, this file must be modified IAW the
  43. individual implmentation.
  44. --------------------------------------------------------------------------------
  45. ------------------------------------------------------------------------------*/
  46. DefinitionBlock(
  47. "APTST.aml",
  48. "SSDT",
  49. 0x01,
  50. "PmRef",
  51. "ApTst",
  52. 0x3000
  53. )
  54. {
  55. External(\_PR.CPU1, DeviceObj)
  56. External(\_PR.CPU2, DeviceObj)
  57. External(\_PR.CPU3, DeviceObj)
  58. External(\_PR.CPU0._PTC)
  59. External(\_PR.CPU0._TSS)
  60. External(PDC0)
  61. External(CFGD)
  62. External(MPEN)
  63. Scope(\_PR.CPU1)
  64. {
  65. Name(_TPC, 0) // All T-States are available
  66. //
  67. // T-State Control/Status interface
  68. //
  69. Method(_PTC, 0)
  70. {
  71. Return(\_PR.CPU0._PTC)
  72. }
  73. Method(_TSS, 0)
  74. {
  75. Return(\_PR.CPU0._TSS)
  76. }
  77. //
  78. // T-State Dependency
  79. //
  80. Method(_TSD, 0)
  81. {
  82. //
  83. // IF four cores are supported/enabled && !(direct access to MSR)
  84. // Report 4 processors and SW_ANY as the coordination
  85. // IF two cores are supported/enabled && !(direct access to MSR)
  86. // Report 2 processors and SW_ANY as the coordination type
  87. // ELSE
  88. // Report 1 processor and SW_ALL as the coordination type (domain 1)
  89. //
  90. // CFGD[23] = Four cores enabled
  91. // CFGD[24] = Two or more cores enabled
  92. // PDCx[2] = OSPM is capable of direct access to On
  93. // Demand throttling MSR
  94. //
  95. If(LNot(And(PDC0,4)))
  96. {
  97. Return(Package(){ // SW_ANY
  98. Package(){
  99. 5, // # entries.
  100. 0, // Revision.
  101. 0, // Domain #.
  102. 0xFD, // Coord Type- SW_ANY
  103. MPEN // # processors.
  104. }
  105. })
  106. }
  107. Return(Package(){ // SW_ALL
  108. Package(){
  109. 5, // # entries.
  110. 0, // Revision.
  111. 1, // Domain #.
  112. 0xFC, // Coord Type- SW_ALL
  113. 1 // # processors.
  114. }
  115. })
  116. }
  117. } // End of CPU1
  118. Scope(\_PR.CPU2)
  119. {
  120. Name(_TPC, 0) // All T-States are available
  121. //
  122. // T-State Control/Status interface
  123. //
  124. Method(_PTC, 0)
  125. {
  126. Return(\_PR.CPU0._PTC)
  127. }
  128. Method(_TSS, 0)
  129. {
  130. Return(\_PR.CPU0._TSS)
  131. }
  132. //
  133. // T-State Dependency
  134. //
  135. Method(_TSD, 0)
  136. {
  137. //
  138. // IF four cores are supported/enabled && !(direct access to MSR)
  139. // Report 4 processors and SW_ANY as the coordination
  140. // IF two cores are supported/enabled && !(direct access to MSR)
  141. // Report 2 processors and SW_ANY as the coordination type
  142. // ELSE
  143. // Report 1 processor and SW_ALL as the coordination type (domain 1)
  144. //
  145. // CFGD[23] = Four cores enabled
  146. // CFGD[24] = Two or more cores enabled
  147. // PDCx[2] = OSPM is capable of direct access to On
  148. // Demand throttling MSR
  149. //
  150. If(LNot(And(PDC0,4)))
  151. {
  152. Return(Package(){ // SW_ANY
  153. Package(){
  154. 5, // # entries.
  155. 0, // Revision.
  156. 0, // Domain #.
  157. 0xFD, // Coord Type- SW_ANY
  158. MPEN // # processors.
  159. }
  160. })
  161. }
  162. Return(Package(){ // SW_ALL
  163. Package(){
  164. 5, // # entries.
  165. 0, // Revision.
  166. 1, // Domain #.
  167. 0xFC, // Coord Type- SW_ALL
  168. 1 // # processors.
  169. }
  170. })
  171. }
  172. } // End of CPU2
  173. Scope(\_PR.CPU3)
  174. {
  175. Name(_TPC, 0) // All T-States are available
  176. //
  177. // T-State Control/Status interface
  178. //
  179. Method(_PTC, 0)
  180. {
  181. Return(\_PR.CPU0._PTC)
  182. }
  183. Method(_TSS, 0)
  184. {
  185. Return(\_PR.CPU0._TSS)
  186. }
  187. //
  188. // T-State Dependency
  189. //
  190. Method(_TSD, 0)
  191. {
  192. //
  193. // IF four cores are supported/enabled && !(direct access to MSR)
  194. // Report 4 processors and SW_ANY as the coordination
  195. // IF two cores are supported/enabled && !(direct access to MSR)
  196. // Report 2 processors and SW_ANY as the coordination type
  197. // ELSE
  198. // Report 1 processor and SW_ALL as the coordination type (domain 1)
  199. //
  200. // CFGD[23] = Four cores enabled
  201. // CFGD[24] = Two or more cores enabled
  202. // PDCx[2] = OSPM is capable of direct access to On
  203. // Demand throttling MSR
  204. //
  205. If(LNot(And(PDC0,4)))
  206. {
  207. Return(Package(){ // SW_ANY
  208. Package(){
  209. 5, // # entries.
  210. 0, // Revision.
  211. 0, // Domain #.
  212. 0xFD, // Coord Type- SW_ANY
  213. MPEN // # processors.
  214. }
  215. })
  216. }
  217. Return(Package(){ // SW_ALL
  218. Package(){
  219. 5, // # entries.
  220. 0, // Revision.
  221. 1, // Domain #.
  222. 0xFC, // Coord Type- SW_ALL
  223. 1 // # processors.
  224. }
  225. })
  226. }
  227. } // End of CPU3
  228. } // End of Definition Block