ApIst.asl 6.1 KB

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  1. /*-----------------------------------------------------------------------------
  2. -------------------------------------------------------------------------------
  3. Intel Silvermont Processor Power Management BIOS Reference Code
  4. Copyright (c) 2006 - 2014, Intel Corporation
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. Filename: APIST.ASL
  7. Revision: Refer to Readme
  8. Date: Refer to Readme
  9. --------------------------------------------------------------------------------
  10. -------------------------------------------------------------------------------
  11. This Processor Power Management BIOS Source Code is furnished under license
  12. and may only be used or copied in accordance with the terms of the license.
  13. The information in this document is furnished for informational use only, is
  14. subject to change without notice, and should not be construed as a commitment
  15. by Intel Corporation. Intel Corporation assumes no responsibility or liability
  16. for any errors or inaccuracies that may appear in this document or any
  17. software that may be provided in association with this document.
  18. Except as permitted by such license, no part of this document may be
  19. reproduced, stored in a retrieval system, or transmitted in any form or by
  20. any means without the express written consent of Intel Corporation.
  21. WARNING: You are authorized and licensed to install and use this BIOS code
  22. ONLY on an IST PC. This utility may damage any system that does not
  23. meet these requirements.
  24. An IST PC is a computer which
  25. (1) Is capable of seamlessly and automatically transitioning among
  26. multiple performance states (potentially operating at different
  27. efficiency ratings) based upon power source changes, END user
  28. preference, processor performance demand, and thermal conditions; and
  29. (2) Includes an Intel Pentium II processors, Intel Pentium III
  30. processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  31. Processor-M, Intel Pentium M Processor, or any other future Intel
  32. processors that incorporates the capability to transition between
  33. different performance states by altering some, or any combination of,
  34. the following processor attributes: core voltage, core frequency, bus
  35. frequency, number of processor cores available, or any other attribute
  36. that changes the efficiency (instructions/unit time-power) at which the
  37. processor operates.
  38. -------------------------------------------------------------------------------
  39. -------------------------------------------------------------------------------
  40. NOTES:
  41. (1) <TODO> - IF the trap range and port definitions do not match those
  42. specified by this reference code, this file must be modified IAW the
  43. individual implmentation.
  44. --------------------------------------------------------------------------------
  45. ------------------------------------------------------------------------------*/
  46. DefinitionBlock (
  47. "APIST.aml",
  48. "SSDT",
  49. 1,
  50. "PmRef",
  51. "ApIst",
  52. 0x3000
  53. )
  54. {
  55. External(\_PR.CPU0._PSS, MethodObj)
  56. External(\_PR.CPU0._PCT, MethodObj)
  57. External(\_PR.CPU0._PPC, IntObj)
  58. External(\_PR.CPU0._PSD, MethodObj)
  59. External(\_PR.CPU1, DeviceObj)
  60. External(\_PR.CPU2, DeviceObj)
  61. External(\_PR.CPU3, DeviceObj)
  62. External (CFGD)
  63. External (PDC0)
  64. Scope(\_PR.CPU1)
  65. {
  66. Method(_PPC,0)
  67. {
  68. Return(\_PR.CPU0._PPC) // Return P0 _PPC value.
  69. }
  70. Method(_PCT,0)
  71. {
  72. Return(\_PR.CPU0._PCT) // Return P0 _PCT.
  73. }
  74. Method(_PSS,0)
  75. {
  76. //Return the same table as CPU0 for CMP cases.
  77. Return(\_PR.CPU0._PSS)
  78. }
  79. // The _PSD object provides information to the OSPM related
  80. // to P-State coordination between processors in a multi-processor
  81. // configurations.
  82. //
  83. Method(_PSD,0)
  84. {
  85. Return(\_PR.CPU0._PSD) // Return P0 _PSD.
  86. }
  87. }
  88. Scope(\_PR.CPU2)
  89. {
  90. Method(_PPC,0)
  91. {
  92. Return(\_PR.CPU0._PPC) // Return P0 _PPC value.
  93. }
  94. Method(_PCT,0)
  95. {
  96. Return(\_PR.CPU0._PCT) // Return P0 _PCT.
  97. }
  98. Method(_PSS,0)
  99. {
  100. //Return the same table as CPU0 for CMP cases.
  101. Return(\_PR.CPU0._PSS)
  102. }
  103. // The _PSD object provides information to the OSPM related
  104. // to P-State coordination between processors in a multi-processor
  105. // configurations.
  106. //
  107. Method(_PSD,0)
  108. {
  109. Return(\_PR.CPU0._PSD) // Return P0 _PSD.
  110. }
  111. }
  112. Scope(\_PR.CPU3)
  113. {
  114. Method(_PPC,0)
  115. {
  116. Return(\_PR.CPU0._PPC) // Return P0 _PPC value.
  117. }
  118. Method(_PCT,0)
  119. {
  120. Return(\_PR.CPU0._PCT) // Return P0 _PCT.
  121. }
  122. Method(_PSS,0)
  123. {
  124. //Return the same table as CPU0 for CMP cases.
  125. Return(\_PR.CPU0._PSS)
  126. }
  127. // The _PSD object provides information to the OSPM related
  128. // to P-State coordination between processors in a multi-processor
  129. // configurations.
  130. //
  131. Method(_PSD,0)
  132. {
  133. Return(\_PR.CPU0._PSD) // Return P0 _PSD.
  134. }
  135. }
  136. } // End of Definition Block