Platform.asl 19 KB

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  1. /**************************************************************************;
  2. ;* *;
  3. ;* *;
  4. ;* Intel Corporation - ACPI Reference Code for the Baytrail *;
  5. ;* Family of Customer Reference Boards. *;
  6. ;* *;
  7. ;* *;
  8. ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
  9. ;
  10. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11. ;
  12. ;* *;
  13. ;* *;
  14. ;**************************************************************************/
  15. // Define the following External variables to prevent a WARNING when
  16. // using ASL.EXE and an ERROR when using IASL.EXE.
  17. External(PDC0)
  18. External(PDC1)
  19. External(PDC2)
  20. External(PDC3)
  21. External(CFGD)
  22. External(\_PR.CPU0._PPC, IntObj)
  23. External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj)
  24. External(\_SB.STR3, DeviceObj)
  25. External(\_SB.I2C1.BATC, DeviceObj)
  26. External(\_SB.DPTF, DeviceObj)
  27. External(\_SB.TCHG, DeviceObj)
  28. External(\_SB.IAOE.PTSL)
  29. External(\_SB.IAOE.WKRS)
  30. //
  31. // Create a Global MUTEX.
  32. //
  33. Mutex(MUTX,0)
  34. // Port 80h Update:
  35. // Update 8 bits of the 32-bit Port 80h.
  36. //
  37. // Arguments:
  38. // Arg0: 0 = Write Port 80h, Bits 7:0 Only.
  39. // 1 = Write Port 80h, Bits 15:8 Only.
  40. // 2 = Write Port 80h, Bits 23:16 Only.
  41. // 3 = Write Port 80h, Bits 31:24 Only.
  42. // Arg1: 8-bit Value to write
  43. //
  44. // Return Value:
  45. // None
  46. Method(P8XH,2,Serialized)
  47. {
  48. If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0.
  49. {
  50. Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
  51. }
  52. If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8.
  53. {
  54. Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
  55. }
  56. If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16.
  57. {
  58. Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
  59. }
  60. If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24.
  61. {
  62. Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
  63. }
  64. }
  65. //
  66. // Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
  67. //
  68. OperationRegion (SPRT, SystemIO, 0xB2, 2)
  69. Field (SPRT, ByteAcc, Lock, Preserve)
  70. {
  71. SSMP, 8
  72. }
  73. // The _PIC Control Method is optional for ACPI design. It allows the
  74. // OS to inform the ASL code which interrupt controller is being used,
  75. // the 8259 or APIC. The reference code in this document will address
  76. // PCI IRQ Routing and resource allocation for both cases.
  77. //
  78. // The values passed into _PIC are:
  79. // 0 = 8259
  80. // 1 = IOAPIC
  81. Method(\_PIC,1)
  82. {
  83. Store(Arg0,GPIC)
  84. Store(Arg0,PICM)
  85. }
  86. OperationRegion(SWC0, SystemIO, 0x610, 0x0F)
  87. Field(SWC0, ByteAcc, NoLock, Preserve)
  88. {
  89. G1S, 8, //SWC GPE1_STS
  90. Offset(0x4),
  91. G1E, 8,
  92. Offset(0xA),
  93. G1S2, 8, //SWC GPE1_STS_2
  94. G1S3, 8 //SWC GPE1_STS_3
  95. }
  96. OperationRegion (SWC1, SystemIO, \PMBS, 0x2C)
  97. Field(SWC1, DWordAcc, NoLock, Preserve)
  98. {
  99. Offset(0x20),
  100. G0S, 32, //GPE0_STS
  101. Offset(0x28),
  102. G0EN, 32 //GPE0_EN
  103. }
  104. // Prepare to Sleep. The hook is called when the OS is about to
  105. // enter a sleep state. The argument passed is the numeric value of
  106. // the Sx state.
  107. Method(_PTS,1)
  108. {
  109. Store(0,P80D) // Zero out the entire Port 80h DWord.
  110. P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0.
  111. //clear the 3 SWC status bits
  112. Store(Ones, G1S3)
  113. Store(Ones, G1S2)
  114. Store(1, G1S)
  115. //set SWC GPE1_EN
  116. Store(1,G1E)
  117. //clear GPE0_STS
  118. Store(Ones, G0S)
  119. If(LEqual(Arg0,3)) // If S3 Suspend
  120. {
  121. //
  122. // Disable Digital Thermal Sensor function when doing S3 suspend
  123. //
  124. If(CondRefOf(DTSE))
  125. {
  126. If(LGreaterEqual(DTSE, 0x01))
  127. {
  128. Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI
  129. Store(0xD0, SSMP) // DTS SW SMI
  130. }
  131. }
  132. }
  133. }
  134. // Wake. This hook is called when the OS is about to wake from a
  135. // sleep state. The argument passed is the numeric value of the
  136. // sleep state the system is waking from.
  137. Method(_WAK,1,Serialized)
  138. {
  139. P8XH(1,0xAB) // Beginning of _WAK.
  140. Notify(\_SB.PWRB,0x02)
  141. If(NEXP)
  142. {
  143. // Reinitialize the Native PCI Express after resume
  144. If(And(OSCC,0x02))
  145. {
  146. \_SB.PCI0.NHPG()
  147. }
  148. If(And(OSCC,0x04)) // PME control granted?
  149. {
  150. \_SB.PCI0.NPME()
  151. }
  152. }
  153. If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume
  154. {
  155. // If CMP is enabled, we may need to restore the C-State and/or
  156. // P-State configuration, as it may have been saved before the
  157. // configuration was finalized based on OS/driver support.
  158. //
  159. // CFGD[24] = Two or more cores enabled
  160. //
  161. If(And(CFGD,0x01000000))
  162. {
  163. //
  164. // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if
  165. // C-States are enabled.
  166. //
  167. // CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled
  168. //
  169. //
  170. }
  171. // Windows XP SP2 does not properly restore the P-State
  172. // upon resume from S4 or S3 with degrade modes enabled.
  173. // Use the existing _PPC methods to cycle the available
  174. // P-States such that the processor ends up running at
  175. // the proper P-State.
  176. //
  177. // Note: For S4, another possible W/A is to always boot
  178. // the system in LFM.
  179. //
  180. If(LEqual(OSYS,2002))
  181. {
  182. If(And(CFGD,0x01))
  183. {
  184. If(LGreater(\_PR.CPU0._PPC,0))
  185. {
  186. Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
  187. PNOT()
  188. Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
  189. PNOT()
  190. }
  191. Else
  192. {
  193. Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
  194. PNOT()
  195. Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
  196. PNOT()
  197. }
  198. }
  199. }
  200. }
  201. Return(Package() {0,0})
  202. }
  203. // Power Notification:
  204. // Perform all needed OS notifications during a
  205. // Power Switch.
  206. //
  207. // Arguments:
  208. // None
  209. //
  210. // Return Value:
  211. // None
  212. Method(PNOT,0,Serialized)
  213. {
  214. // If MP enabled and driver support is present, notify all
  215. // processors.
  216. If(MPEN)
  217. {
  218. If(And(PDC0,0x0008))
  219. {
  220. Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC.
  221. If(And(PDC0,0x0010))
  222. {
  223. Sleep(100)
  224. Notify(\_PR.CPU0,0x81) // Eval _CST.
  225. }
  226. }
  227. If(And(PDC1,0x0008))
  228. {
  229. Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC.
  230. If(And(PDC1,0x0010))
  231. {
  232. Sleep(100)
  233. Notify(\_PR.CPU1,0x81) // Eval _CST.
  234. }
  235. }
  236. If(And(PDC2,0x0008))
  237. {
  238. Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC.
  239. If(And(PDC2,0x0010))
  240. {
  241. Sleep(100)
  242. Notify(\_PR.CPU2,0x81) // Eval _CST.
  243. }
  244. }
  245. If(And(PDC3,0x0008))
  246. {
  247. Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC.
  248. If(And(PDC3,0x0010))
  249. {
  250. Sleep(100)
  251. Notify(\_PR.CPU3,0x81) // Eval _CST.
  252. }
  253. }
  254. }
  255. Else
  256. {
  257. Notify(\_PR.CPU0,0x80) // Eval _PPC.
  258. Sleep(100)
  259. Notify(\_PR.CPU0,0x81) // Eval _CST
  260. }
  261. }
  262. //
  263. // System Bus
  264. //
  265. Scope(\_SB)
  266. {
  267. Name(CRTT, 110) // Processor critical temperature
  268. Name(ACTT, 77) // Active temperature limit for processor participant
  269. Name(GCR0, 70) // Critical temperature for Generic participant 0 in degree celsius
  270. Name(GCR1, 70) // Critical temperature for Generic participant 1 in degree celsius
  271. Name(GCR2, 70) // Critical temperature for Generic participant 2 in degree celsius
  272. Name(GCR3, 70) // Critical temperature for Generic participant 3 in degree celsius
  273. Name(GCR4, 70) // Critical temperature for Generic participant 4 in degree celsius
  274. Name(GCR5, 70) // Critical temperature for Generic participant 5 in degree celsius
  275. Name(GCR6, 70) // Critical temperature for Generic participant 6 in degree celsius
  276. Name(PST0, 60) // Passive temperature limit for Generic Participant 0 in degree celsius
  277. Name(PST1, 60) // Passive temperature limit for Generic Participant 1 in degree celsius
  278. Name(PST2, 60) // Passive temperature limit for Generic Participant 2 in degree celsius
  279. Name(PST3, 60) // Passive temperature limit for Generic Participant 3 in degree celsius
  280. Name(PST4, 60) // Passive temperature limit for Generic Participant 4 in degree celsius
  281. Name(PST5, 60) // Passive temperature limit for Generic Participant 5 in degree celsius
  282. Name(PST6, 60) // Passive temperature limit for Generic Participant 6 in degree celsius
  283. Name(LPMV, 3)
  284. Name(PDBG, 0) // DPTF Super debug option
  285. Name(PDPM, 1) // DPTF DPPM enable
  286. Name(PDBP, 1) // DPTF DBPT enable (dynamic battery protection technology)
  287. Name(DLPO, Package()
  288. {
  289. 0x1, // Revision
  290. 0x1, // LPO Enable
  291. 0x1, // LPO StartPState
  292. 25, // LPO StepSize
  293. 0x1, //
  294. 0x1, //
  295. })
  296. Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change
  297. // or it is from Graphics driver. Value of 1 is for DPTF else it is 0
  298. Method(_INI,0)
  299. {
  300. // NVS has stale DTS data. Get and update the values
  301. // with current temperatures. Note that this will also
  302. // re-arm any AP Thermal Interrupts.
  303. // Read temperature settings from global NVS
  304. Store(DPCT, CRTT)
  305. Store(Subtract(DPPT, 8), ACTT) // Active Trip point = Passive trip point - 8
  306. Store(DGC0, GCR0)
  307. Store(DGC0, GCR1)
  308. Store(DGC1, GCR2)
  309. Store(DGC1, GCR3)
  310. Store(DGC1, GCR4)
  311. Store(DGC2, GCR5)
  312. Store(DGC2, GCR6)
  313. Store(DGP0, PST0)
  314. Store(DGP0, PST1)
  315. Store(DGP1, PST2)
  316. Store(DGP1, PST3)
  317. Store(DGP1, PST4)
  318. Store(DGP2, PST5)
  319. Store(DGP2, PST6)
  320. // Read Current low power mode setting from global NVS
  321. Store(DLPM, LPMV)
  322. // Update DPTF Super Debug option
  323. Store(DDBG, PDBG)
  324. // Update DPTF LPO Options
  325. Store(LPOE, Index(DLPO,1))
  326. Store(LPPS, Index(DLPO,2))
  327. Store(LPST, Index(DLPO,3))
  328. Store(LPPC, Index(DLPO,4))
  329. Store(LPPF, Index(DLPO,5))
  330. Store(DPME, PDPM)
  331. }
  332. // Define a (Control Method) Power Button.
  333. Device(PWRB)
  334. {
  335. Name(_HID,EISAID("PNP0C0C"))
  336. // GPI_SUS0 = GPE16 = Waketime SCI. The PRW isn't working when
  337. // placed in any of the logical locations ( PS2K, PS2M),
  338. // so a Power Button Device was created specifically
  339. // for the WAKETIME_SCI PRW.
  340. Name(_PRW, Package() {16,4})
  341. }
  342. Device(SLPB)
  343. {
  344. Name(_HID, EISAID("PNP0C0E"))
  345. } // END SLPB
  346. Scope(PCI0)
  347. {
  348. Method(_INI,0)
  349. {
  350. // Determine the OS and store the value, where:
  351. //
  352. // OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
  353. // OSYS = 2012 = Windows 8 and Windows Server 2012.
  354. //
  355. // Assume Windows 7 at a minimum.
  356. Store(2009,OSYS)
  357. // Check for a specific OS which supports _OSI.
  358. If(CondRefOf(\_OSI,Local0))
  359. {
  360. // Linux returns _OSI = TRUE for numerous Windows
  361. // strings so that it is fully compatible with
  362. // BIOSes available in the market today. There are
  363. // currently 2 known exceptions to this model:
  364. // 1) Video Repost - Linux supports S3 without
  365. // requireing a Driver, meaning a Video
  366. // Repost will be required.
  367. // 2) On-Screen Branding - a full CMT Logo
  368. // is limited to the WIN2K and WINXP
  369. // Operating Systems only.
  370. // Use OSYS for Windows Compatibility.
  371. If(\_OSI("Windows 2009")) // Windows 7 or Windows Server 2008 R2
  372. {
  373. Store(2009,OSYS)
  374. }
  375. If(\_OSI("Windows 2012")) // Windows 8 or Windows Server 2012
  376. {
  377. Store(2012,OSYS)
  378. }
  379. If(\_OSI("Windows 2013")) //Windows Blue
  380. {
  381. Store(2013,OSYS)
  382. }
  383. //
  384. // If CMP is enabled, enable SMM C-State
  385. // coordination. SMM C-State coordination
  386. // will be disabled in _PDC if driver support
  387. // for independent C-States deeper than C1
  388. // is indicated.
  389. }
  390. }
  391. Method(NHPG,0,Serialized)
  392. {
  393. }
  394. Method(NPME,0,Serialized)
  395. {
  396. }
  397. } // end Scope(PCI0)
  398. Device (GPED) //virtual GPIO device for ASL based AC/Battery/Expection notification
  399. {
  400. Name (_ADR, 0)
  401. Name (_HID, "INT0002")
  402. Name (_CID, "INT0002")
  403. Name (_DDN, "Virtual GPIO controller" )
  404. Name (_UID, 1)
  405. Method (_CRS, 0x0, Serialized)
  406. {
  407. Name (RBUF, ResourceTemplate ()
  408. {
  409. Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9
  410. })
  411. Return (RBUF)
  412. }
  413. Method (_STA, 0x0, NotSerialized)
  414. {
  415. Return(0x0)
  416. }
  417. Method (_AEI, 0x0, Serialized)
  418. {
  419. Name(RBUF, ResourceTemplate()
  420. {
  421. GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2
  422. })
  423. Return(RBUF)
  424. }
  425. Method(_E02) // _Exx method will be called when interrupt is raised
  426. {
  427. If (LEqual (PWBS, 1))
  428. {
  429. Store (1, PWBS) //Clear PowerButton Status
  430. }
  431. If (LEqual (PMEB, 1))
  432. {
  433. Store (1, PMEB) //Clear PME_B0_STS
  434. }
  435. If (LEqual (\_SB.PCI0.SATA.PMES, 1))
  436. {
  437. Store (1, \_SB.PCI0.SATA.PMES)
  438. Notify (\_SB.PCI0.SATA, 0x02)
  439. }
  440. //
  441. // eMMC 4.41
  442. //
  443. If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1)))
  444. {
  445. Store (1, \_SB.PCI0.EM41.PMES)
  446. Notify (\_SB.PCI0.EM41, 0x02)
  447. }
  448. //
  449. // eMMC 4.5
  450. //
  451. If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1)))
  452. {
  453. Store (1, \_SB.PCI0.EM45.PMES)
  454. Notify (\_SB.PCI0.EM45, 0x02)
  455. }
  456. If (LEqual(HDAD, 0))
  457. {
  458. If (LEqual (\_SB.PCI0.HDEF.PMES, 1))
  459. {
  460. Store (1, \_SB.PCI0.HDEF.PMES)
  461. Notify (\_SB.PCI0.HDEF, 0x02)
  462. }
  463. }
  464. If (LEqual (\_SB.PCI0.EHC1.PMES, 1))
  465. {
  466. Store (1, \_SB.PCI0.EHC1.PMES)
  467. Notify (\_SB.PCI0.EHC1, 0x02)
  468. }
  469. If (LEqual (\_SB.PCI0.XHC1.PMES, 1))
  470. {
  471. Store (1, \_SB.PCI0.XHC1.PMES)
  472. Notify (\_SB.PCI0.XHC1, 0x02)
  473. }
  474. If (LEqual (\_SB.PCI0.SEC0.PMES, 1))
  475. {
  476. Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES)
  477. Notify (\_SB.PCI0.SEC0, 0x02)
  478. }
  479. }
  480. } // Device (GPED)
  481. //--------------------
  482. // GPIO
  483. //--------------------
  484. Device (GPO0)
  485. {
  486. Name (_ADR, 0)
  487. Name (_HID, "INT33FC")
  488. Name (_CID, "INT33B2")
  489. Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" )
  490. Name (_UID, 1)
  491. Method (_CRS, 0x0, Serialized)
  492. {
  493. Name (RBUF, ResourceTemplate ()
  494. {
  495. Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000)
  496. Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49}
  497. })
  498. Return (RBUF)
  499. }
  500. Method (_STA, 0x0, NotSerialized)
  501. {
  502. //
  503. // GPO driver will report present if any of below New IO bus exist
  504. //
  505. If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist
  506. { Return(0xF) }
  507. If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist
  508. { Return(0xF) }
  509. If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist
  510. { Return(0xF) }
  511. If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist
  512. { Return(0xF) }
  513. If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist
  514. { Return(0xF) }
  515. If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist
  516. { Return(0xF) }
  517. If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist
  518. { Return(0xF) }
  519. If (LEqual(L27D, 0)) // LPIO2 I2C #7 exist
  520. { Return(0xF) }
  521. Return(0x0)
  522. }
  523. // Track status of GPIO OpRegion availability for this controller
  524. Name(AVBL, 0)
  525. Method(_REG,2)
  526. {
  527. If (Lequal(Arg0, 8))
  528. {
  529. Store(Arg1, ^AVBL)
  530. }
  531. }
  532. OperationRegion(GPOP, SystemIo, \GPBS, 0x50)
  533. Field(GPOP, ByteAcc, NoLock, Preserve) {
  534. Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h
  535. , 21,
  536. BTD3, 1, //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP
  537. Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h
  538. , 30,
  539. SHD3, 1 //GPIO_S0_SC_95 - SENS_HUB_RST_N
  540. }
  541. } // Device (GPO0)
  542. Device (GPO1)
  543. {
  544. Name (_ADR, 0)
  545. Name (_HID, "INT33FC")
  546. Name (_CID, "INT33B2")
  547. Name (_DDN, "ValleyView2 GPNCORE controller" )
  548. Name (_UID, 2)
  549. Method (_CRS, 0x0, Serialized)
  550. {
  551. Name (RBUF, ResourceTemplate ()
  552. {
  553. Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000)
  554. Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48}
  555. })
  556. Return (RBUF)
  557. }
  558. Method (_STA, 0x0, NotSerialized)
  559. {
  560. Return(\_SB.GPO0._STA)
  561. }
  562. } // Device (GPO1)
  563. Device (GPO2)
  564. {
  565. Name (_ADR, 0)
  566. Name (_HID, "INT33FC")
  567. Name (_CID, "INT33B2")
  568. Name (_DDN, "ValleyView2 GPSUS controller" )
  569. Name (_UID, 3)
  570. Method (_CRS, 0x0, Serialized)
  571. {
  572. Name (RBUF, ResourceTemplate ()
  573. {
  574. Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000)
  575. Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50}
  576. })
  577. Return (RBUF)
  578. }
  579. Method (_STA, 0x0, NotSerialized)
  580. {
  581. Return(^^GPO0._STA)
  582. }
  583. // Track status of GPIO OpRegion availability for this controller
  584. Name(AVBL, 0)
  585. Method(_REG,2)
  586. {
  587. If (Lequal(Arg0, 8))
  588. {
  589. Store(Arg1, ^AVBL)
  590. }
  591. }
  592. //Manipulate GPIO line using GPIO operation regions.
  593. Name (GMOD, ResourceTemplate () //One method of creating a Connection for OpRegion accesses in Field definitions
  594. {
  595. //is creating a named object that refers to the connection attributes
  596. GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21} //sus 21+128 BT+WLAN_ENABLE
  597. })
  598. OperationRegion(GPOP, SystemIo, \GPBS, 0x100)
  599. Field(GPOP, ByteAcc, NoLock, Preserve) {
  600. Offset(0x88), // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h
  601. , 20,
  602. WFD3, 1
  603. }
  604. } // Device (GPO2)
  605. include ("PchScc.asl")
  606. include ("PchLpss.asl")
  607. Scope(I2C7)
  608. {
  609. } //End Scope(I2C7)
  610. } // end Scope(\_SB)
  611. Name(PICM, 0) // Global Name, returns current Interrupt controller mode; updated from _PIC control method