PchXhci.asl 14 KB

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  1. /**************************************************************************;
  2. ;* *;
  3. ;* *;
  4. ;* Intel Corporation - ACPI Reference Code for the Haswell *;
  5. ;* Family of Customer Reference Boards. *;
  6. ;* *;
  7. ;* *;
  8. ;* Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved *;
  9. ;
  10. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11. ;
  12. ;* *;
  13. ;* *;
  14. ;**************************************************************************/
  15. //scope is \_SB.PCI0.XHC
  16. Device(XHC1)
  17. {
  18. Name(_ADR, 0x00140000) //Device 20, Function 0
  19. //When it is in Host mode, USH core is connected to USB3 microAB(USB3 P1 and USB2 P0)
  20. Name (_DDN, "Baytrail XHCI controller (CCG core/Host only)" )
  21. Method(XDEP, 0)
  22. {
  23. If(LEqual(OSYS,2013))
  24. {
  25. Name(_DEP, Package(0x1)
  26. {
  27. PEPD
  28. })
  29. }
  30. }
  31. Name (_STR, Unicode ("Baytrail XHCI controller (CCG core/Host only)"))
  32. Name(_PRW, Package() {0xD,4})
  33. Method(_PSW,1)
  34. {
  35. If (LAnd (PMES, PMEE)) {
  36. Store (0, PMEE)
  37. Store (1, PMES)
  38. }
  39. }
  40. OperationRegion (PMEB, PCI_Config, 0x74, 0x04) // Power Management Control/Status
  41. Field (PMEB, WordAcc, NoLock, Preserve)
  42. {
  43. , 8,
  44. PMEE, 1, //bit8 PME_En
  45. , 6,
  46. PMES, 1 //bit15 PME_Status
  47. }
  48. Method(_STA, 0)
  49. {
  50. If(LNotEqual(XHCI, 0)) //NVS variable controls present of XHCI controller
  51. {
  52. Return (0xF)
  53. } Else
  54. {
  55. Return (0x0)
  56. }
  57. }
  58. OperationRegion(XPRT,PCI_Config,0xD0,0x10)
  59. Field(XPRT,DWordAcc,NoLock,Preserve) //usbx_top.doc.xml
  60. {
  61. PR2, 32, //bit[8:0] USB2HCSEL
  62. PR2M, 32, //bit[8:0] USB2HCSELM
  63. PR3, 32, //bit[3:0] USB3SSEN
  64. PR3M, 32 //bit[3:0] USB3SSENM
  65. }
  66. Device(RHUB)
  67. {
  68. Name(_ADR, Zero) //address 0 is reserved for root hub
  69. //
  70. // Super Speed Ports - must match _UPC declarations of the coresponding Full Speed Ports.
  71. // Paired with Port 1
  72. Device(SSP1)
  73. {
  74. Name(_ADR, 0x07)
  75. Method(_UPC,0,Serialized)
  76. {
  77. Name(UPCP, Package()
  78. {
  79. 0xFF, // Port is connectable if non-zero
  80. 0x06, // USB3 uAB connector
  81. 0x00,
  82. 0x00
  83. })
  84. Return(UPCP)
  85. }
  86. Method(_PLD,0,Serialized)
  87. {
  88. Name(PLDP, Package() //pls check ACPI 5.0 section 6.1.8
  89. {
  90. Buffer(0x14)
  91. {
  92. //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
  93. 0x82, 0x00, 0x00, 0x00,
  94. //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000
  95. 0x00, 0x00, 0x00, 0x00,
  96. //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center
  97. // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
  98. 0x4B, 0x19, 0x00, 0x00,
  99. //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number
  100. // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
  101. 0x03, 0x00, 0x00, 0x00,
  102. //159:128 Vert. and Horiz. Offsets not supplied
  103. 0xFF, 0xFF, 0xFF, 0xFF
  104. }
  105. })
  106. Return (PLDP)
  107. }
  108. }
  109. //
  110. // High Speed Ports
  111. // pair port with port 7 (SS)
  112. // The UPC declarations for LS/FS/HS and SS ports that are paired to form a USB3.0 compatible connector.
  113. // A "pair" is defined by two ports that declare _PLDs with identical Panel, Vertical Position, Horizontal Postion, Shape, Group Orientation
  114. // and Group Token
  115. Device(HS01)
  116. {
  117. Name(_ADR, 0x01)
  118. Method(_UPC,0,Serialized)
  119. {
  120. Name(UPCP, Package() { 0xFF,0x06,0x00,0x00 })
  121. Return(UPCP)
  122. }
  123. Method(_PLD,0,Serialized)
  124. {
  125. Name(PLDP, Package() //pls check ACPI 5.0 section 6.1.8
  126. {
  127. Buffer(0x14)
  128. {
  129. //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
  130. 0x82, 0x00, 0x00, 0x00,
  131. //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000
  132. 0x00, 0x00, 0x00, 0x00,
  133. //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center
  134. // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
  135. 0x4B, 0x19, 0x00, 0x00,
  136. //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number
  137. // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
  138. 0x03, 0x00, 0x00, 0x00,
  139. //159:128 Vert. and Horiz. Offsets not supplied
  140. 0xFF, 0xFF, 0xFF, 0xFF
  141. }
  142. })
  143. Return (PLDP)
  144. }
  145. }//end of HS01
  146. // USB2 Type-A/USB2 only
  147. // EHCI debug capable
  148. Device(HS02)
  149. {
  150. Name(_ADR, 0x02) // 0 is for root hub so physical port index starts from 1 (it is port1 in schematic)
  151. Method(_UPC,0,Serialized)
  152. {
  153. Name(UPCP, Package()
  154. {
  155. 0xFF, // connectable
  156. 0xFF, //
  157. 0x00,
  158. 0x00
  159. })
  160. Return(UPCP)
  161. }
  162. Method(_PLD,0,Serialized)
  163. {
  164. Name(PLDP, Package()
  165. {
  166. Buffer(0x14)
  167. {
  168. //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
  169. 0x82, 0x00, 0x00, 0x00,
  170. //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000
  171. 0x00, 0x00, 0x00, 0x00,
  172. //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'00 Left
  173. // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
  174. 0x4B, 0x08, 0x00, 0x00,
  175. //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number
  176. // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
  177. 0x03, 0x00, 0x00, 0x00,
  178. //159:128 Vert. and Horiz. Offsets not supplied
  179. 0xFF, 0xFF, 0xFF, 0xFF
  180. }
  181. })
  182. Return (PLDP)
  183. }
  184. }//end of HS02
  185. // high speed port 3
  186. Device(HS03)
  187. {
  188. Name(_ADR, 0x03)
  189. Method(_UPC,0,Serialized)
  190. {
  191. Name(UPCP, Package()
  192. {
  193. 0xFF, // connectable
  194. 0xFF,
  195. 0x00,
  196. 0x00
  197. })
  198. Return(UPCP)
  199. }
  200. Method(_RMV, 0) // for XHCICV debug purpose
  201. {
  202. Return(0x0)
  203. }
  204. Method(_PLD,0,Serialized)
  205. {
  206. Name(PLDP, Package()
  207. {
  208. Buffer(0x14)
  209. {
  210. //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
  211. 0x82, 0x00, 0x00, 0x00,
  212. //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000
  213. 0x00, 0x00, 0x00, 0x00,
  214. //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored)
  215. // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
  216. // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
  217. 0x30, 0x08, 0x00, 0x00,
  218. //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
  219. // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
  220. 0x00, 0x00, 0x00, 0x00,
  221. //159:128 Vert. and Horiz. Offsets not supplied
  222. 0xFF, 0xFF, 0xFF, 0xFF
  223. }
  224. })
  225. Return (PLDP)
  226. }
  227. }
  228. Device(HS04)
  229. {
  230. Name(_ADR, 0x04)
  231. Method(_UPC,0,Serialized)
  232. {
  233. Name(UPCP, Package()
  234. {
  235. 0xFF, //connectable
  236. 0xFF, //Proprietary connector (FPC connector)
  237. 0x00,
  238. 0x00
  239. })
  240. Return(UPCP)
  241. }
  242. Method(_PLD,0,Serialized)
  243. {
  244. Name(PLDP, Package()
  245. {
  246. Buffer(0x14)
  247. {
  248. //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
  249. 0x82, 0x00, 0x00, 0x00,
  250. //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000
  251. 0x00, 0x00, 0x00, 0x00,
  252. //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored)
  253. // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
  254. // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
  255. 0x30, 0x08, 0x00, 0x00,
  256. //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
  257. // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
  258. 0x00, 0x00, 0x00, 0x00,
  259. //159:128 Vert. and Horiz. Offsets not supplied
  260. 0xFF, 0xFF, 0xFF, 0xFF
  261. }
  262. })
  263. Return (PLDP)
  264. }
  265. }
  266. Device(HSC1) // USB2 HSIC 01
  267. {
  268. Name(_ADR, 0x05)
  269. Method(_UPC,0,Serialized)
  270. {
  271. Name(UPCP, Package()
  272. {
  273. 0xFF, //connectable
  274. 0xFF, //Proprietary connector (FPC connector)
  275. 0x00,
  276. 0x00
  277. })
  278. Return(UPCP)
  279. }
  280. Method(_PLD,0,Serialized)
  281. {
  282. Name(PLDP, Package()
  283. {
  284. Buffer(0x14)
  285. {
  286. //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
  287. 0x82, 0x00, 0x00, 0x00,
  288. //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000
  289. 0x00, 0x00, 0x00, 0x00,
  290. //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored)
  291. // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
  292. // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
  293. 0x30, 0x08, 0x00, 0x00,
  294. //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
  295. // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
  296. 0x00, 0x00, 0x00, 0x00,
  297. //159:128 Vert. and Horiz. Offsets not supplied
  298. 0xFF, 0xFF, 0xFF, 0xFF
  299. }
  300. })
  301. Return (PLDP)
  302. }
  303. }
  304. Device(HSC2) // USB2 HSIC 02
  305. {
  306. Name(_ADR, 0x06)
  307. Method(_UPC,0,Serialized)
  308. {
  309. Name(UPCP, Package()
  310. {
  311. 0xFF, //connectable
  312. 0xFF, //Proprietary connector (FPC connector)
  313. 0x00,
  314. 0x00
  315. })
  316. Return(UPCP)
  317. }
  318. Method(_PLD,0,Serialized)
  319. {
  320. Name(PLDP, Package()
  321. {
  322. Buffer(0x14)
  323. {
  324. //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
  325. 0x82, 0x00, 0x00, 0x00,
  326. //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000
  327. 0x00, 0x00, 0x00, 0x00,
  328. //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored)
  329. // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
  330. // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
  331. 0x30, 0x08, 0x00, 0x00,
  332. //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
  333. // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
  334. 0x00, 0x00, 0x00, 0x00,
  335. //159:128 Vert. and Horiz. Offsets not supplied
  336. 0xFF, 0xFF, 0xFF, 0xFF
  337. }
  338. })
  339. Return (PLDP)
  340. }
  341. }
  342. } //end of root hub
  343. } // end of XHC1