Pch.asl 17 KB

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  1. /**************************************************************************;
  2. ;* *;
  3. ;* *;
  4. ;* Intel Corporation - ACPI Reference Code for the Baytrail *;
  5. ;* Family of Customer Reference Boards. *;
  6. ;* *;
  7. ;* *;
  8. ;* Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved *;
  9. ;
  10. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11. ;
  12. ;* *;
  13. ;* *;
  14. ;**************************************************************************/
  15. Scope(\)
  16. {
  17. //
  18. // Define VLV ABASE I/O as an ACPI operating region. The base address
  19. // can be found in Device 31, Registers 40-43h.
  20. //
  21. OperationRegion(PMIO, SystemIo, \PMBS, 0x46)
  22. Field(PMIO, ByteAcc, NoLock, Preserve)
  23. {
  24. , 8,
  25. PWBS, 1, // Power Button Status
  26. Offset(0x20),
  27. , 13,
  28. PMEB, 1, // PME_B0_STS
  29. Offset(0x42), // General Purpose Control
  30. , 1,
  31. GPEC, 1
  32. }
  33. Field(PMIO, ByteAcc, NoLock, WriteAsZeros)
  34. {
  35. Offset(0x20), // GPE0 Status
  36. , 4,
  37. PSCI, 1, // PUNIT SCI Status
  38. SCIS, 1 // GUNIT SCI Status
  39. }
  40. //
  41. // Define a Memory Region that will allow access to the PMC
  42. // Register Block. Note that in the Intel Reference Solution, the PMC
  43. // will get fixed up dynamically during POST.
  44. //
  45. OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register
  46. Field(PMCR,DWordAcc,Lock,Preserve)
  47. {
  48. Offset(0x00), // Function Disable Register
  49. L10D, 1, // (0) LPIO1 DMA Disable
  50. L11D, 1, // (1) LPIO1 PWM #1 Disable
  51. L12D, 1, // (2) LPIO1 PWM #2 Disable
  52. L13D, 1, // (3) LPIO1 HS-UART #1 Disable
  53. L14D, 1, // (4) LPIO1 HS-UART #2 Disable
  54. L15D, 1, // (5) LPIO1 SPI Disable
  55. , 2, // (6:7) Reserved
  56. SD1D, 1, // (8) SCC SDIO #1 Disable
  57. SD2D, 1, // (9) SCC SDIO #2 Disable
  58. SD3D, 1, // (10) SCC SDIO #3 Disable
  59. HSID, 1, // (11)
  60. HDAD, 1, // (12) Azalia Disable
  61. LPED, 1, // (13) LPE Disable
  62. OTGD, 1, // (14) USB OTG Disable
  63. , 1, // (15) USH Disable
  64. , 1, // (16)
  65. , 1, // (17)
  66. , 1, // (18) USB Disable
  67. , 1, // (19) SEC Disable
  68. RP1D, 1, // (20) Root Port 0 Disable
  69. RP2D, 1, // (21) Root Port 1 Disable
  70. RP3D, 1, // (22) Root Port 2 Disable
  71. RP4D, 1, // (23) Root Port 3 Disable
  72. L20D, 1, // (24) LPIO2 DMA Disable
  73. L21D, 1, // (25) LPIO2 I2C #1 Disable
  74. L22D, 1, // (26) LPIO2 I2C #2 Disable
  75. L23D, 1, // (27) LPIO2 I2C #3 Disable
  76. L24D, 1, // (28) LPIO2 I2C #4 Disable
  77. L25D, 1, // (29) LPIO2 I2C #5 Disable
  78. L26D, 1, // (30) LPIO2 I2C #6 Disable
  79. L27D, 1 // (31) LPIO2 I2C #7 Disable
  80. }
  81. OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers
  82. Field(CLKC,DWordAcc,Lock,Preserve)
  83. {
  84. Offset(0x00), // PLT_CLK_CTL_0
  85. CKC0, 2,
  86. CKF0, 1,
  87. , 29,
  88. Offset(0x04), // PLT_CLK_CTL_1
  89. CKC1, 2,
  90. CKF1, 1,
  91. , 29,
  92. Offset(0x08), // PLT_CLK_CTL_2
  93. CKC2, 2,
  94. CKF2, 1,
  95. , 29,
  96. Offset(0x0C), // PLT_CLK_CTL_3
  97. CKC3, 2,
  98. CKF3, 1,
  99. , 29,
  100. Offset(0x10), // PLT_CLK_CTL_4
  101. CKC4, 2,
  102. CKF4, 1,
  103. , 29,
  104. Offset(0x14), // PLT_CLK_CTL_5
  105. CKC5, 2,
  106. CKF5, 1,
  107. , 29,
  108. }
  109. } //end Scope(\)
  110. scope (\_SB)
  111. {
  112. Device(LPEA)
  113. {
  114. Name (_ADR, 0)
  115. Name (_HID, "80860F28")
  116. Name (_CID, "80860F28")
  117. //Name (_CLS, Package (3) {0x04, 0x01, 0x00})
  118. Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")
  119. Name (_SUB, "80867270")
  120. Name (_UID, 1)
  121. Name (_DEP, Package() {\_SB.I2C2.RTEK})
  122. Name(_PR0,Package() {PLPE})
  123. Method (_STA, 0x0, NotSerialized)
  124. {
  125. If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))
  126. {
  127. If(LEqual(LPAD, 1))
  128. {
  129. Return (0xF)
  130. }
  131. }
  132. Return (0x0)
  133. }
  134. Method (_DIS, 0x0, NotSerialized)
  135. {
  136. //Add a dummy disable function
  137. }
  138. Name (RBUF, ResourceTemplate ()
  139. {
  140. Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO
  141. Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space
  142. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post
  143. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
  144. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}
  145. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}
  146. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}
  147. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}
  148. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
  149. GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} // Audio jack interrupt
  150. }
  151. )
  152. Method (_CRS, 0x0, NotSerialized)
  153. {
  154. CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
  155. Store(LPE0, B0BA)
  156. CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
  157. Store(LPE1, B1BA)
  158. CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
  159. Store(LPE2, B2BA)
  160. Return (RBUF)
  161. }
  162. OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
  163. Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
  164. {
  165. Offset (0x84),
  166. PSAT, 32
  167. }
  168. PowerResource(PLPE, 0, 0) // Power Resource for LPEA
  169. {
  170. Method (_STA)
  171. {
  172. Return (1) // Power Resource is always available.
  173. }
  174. Method (_ON)
  175. {
  176. And(PSAT, 0xfffffffC, PSAT)
  177. OR(PSAT, 0X00000000, PSAT)
  178. }
  179. Method (_OFF)
  180. {
  181. OR(PSAT, 0x00000003, PSAT)
  182. OR(PSAT, 0X00000000, PSAT)
  183. }
  184. } // End PLPE
  185. } // End "Low Power Engine Audio"
  186. Device(LPA2)
  187. {
  188. Name (_ADR, 0)
  189. Name (_HID, "LPE0F28") // _HID: Hardware ID
  190. Name (_CID, "LPE0F28") // _CID: Compatible ID
  191. Name (_DDN, "Intel(R) SST Audio - LPE0F28") // _DDN: DOS Device Name
  192. Name (_SUB, "80867270")
  193. Name (_UID, 1)
  194. Name (_DEP, Package() {\_SB.I2C2.RTEK})
  195. Name(_PR0,Package() {PLPE})
  196. Method (_STA, 0x0, NotSerialized)
  197. {
  198. If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))
  199. {
  200. If(LEqual(LPAD, 1))
  201. {
  202. Return (0xF)
  203. }
  204. }
  205. Return (0x0)
  206. }
  207. Method (_DIS, 0x0, NotSerialized)
  208. {
  209. //Add a dummy disable function
  210. }
  211. Name (RBUF, ResourceTemplate ()
  212. {
  213. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post
  214. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)
  215. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)
  216. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)
  217. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)
  218. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
  219. Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space
  220. }
  221. )
  222. Method (_CRS, 0x0, NotSerialized)
  223. {
  224. CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
  225. Add(LPE0, 0x140000, SHBA)
  226. CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)
  227. Add(LPE0, 0x144000, MBBA)
  228. CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)
  229. Add(LPE0, 0xC0000, IRBA)
  230. CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)
  231. Add(LPE0, 0x100000, DRBA)
  232. CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
  233. Store(LPE1, B1BA)
  234. CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
  235. Store(LPE2, B2BA)
  236. Return (RBUF)
  237. }
  238. OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
  239. Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
  240. {
  241. Offset (0x84),
  242. PSAT, 32
  243. }
  244. PowerResource(PLPE, 0, 0) // Power Resource for LPEA
  245. {
  246. Method (_STA)
  247. {
  248. Return (1) // Power Resource is always available.
  249. }
  250. Method (_ON)
  251. {
  252. And(PSAT, 0xfffffffC, PSAT)
  253. OR(PSAT, 0X00000000, PSAT)
  254. }
  255. Method (_OFF)
  256. {
  257. OR(PSAT, 0x00000003, PSAT)
  258. OR(PSAT, 0X00000000, PSAT)
  259. }
  260. } // End PLPE
  261. Device (ADMA)
  262. {
  263. Name (_ADR, Zero) // _ADR: Address
  264. Name (_HID, "DMA0F28") // _HID: Hardware ID
  265. Name (_CID, "DMA0F28") // _CID: Compatible ID
  266. Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name
  267. Name (_UID, One) // _UID: Unique ID
  268. Name (RBUF, ResourceTemplate ()
  269. {
  270. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0) // LPE BASE + LPE DMA0 offset
  271. Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM) // LPE BASE + LPE SHIM offset
  272. Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
  273. })
  274. Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
  275. {
  276. CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)
  277. Add(LPE0, 0x98000, D0BA)
  278. CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
  279. Add(LPE0, 0x140000, SHBA)
  280. Return (RBUF)
  281. }
  282. }
  283. } // End "Low Power Engine Audio" for Android
  284. }
  285. scope (\_SB.PCI0)
  286. {
  287. //
  288. // Serial ATA Host Controller - Device 19, Function 0
  289. //
  290. Device(SATA)
  291. {
  292. Name(_ADR,0x00130000)
  293. //
  294. // SATA Methods pulled in via SSDT.
  295. //
  296. OperationRegion(SATR, PCI_Config, 0x74,0x4)
  297. Field(SATR,WordAcc,NoLock,Preserve)
  298. {
  299. Offset(0x00), // 0x74, PMCR
  300. , 8,
  301. PMEE, 1, //PME_EN
  302. , 6,
  303. PMES, 1 //PME_STS
  304. }
  305. Method (_STA, 0x0, NotSerialized)
  306. {
  307. Return(0xf)
  308. }
  309. Method(_DSW, 3)
  310. {
  311. } // End _DSW
  312. }
  313. //
  314. // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment
  315. //
  316. Device(EM41)
  317. {
  318. Name(_ADR,0x00100000)
  319. OperationRegion(SDIO, PCI_Config, 0x84,0x4)
  320. Field(SDIO,WordAcc,NoLock,Preserve)
  321. {
  322. Offset(0x00), // 0x84, PMCR
  323. , 8,
  324. PMEE, 1, //PME_EN
  325. , 6,
  326. PMES, 1 //PME_STS
  327. }
  328. Method (_STA, 0x0, NotSerialized)
  329. {
  330. If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))
  331. {
  332. Return(0xF)
  333. }
  334. Else
  335. {
  336. Return(0x0)
  337. }
  338. }
  339. Method(_DSW, 3)
  340. {
  341. } // End _DSW
  342. Device (CARD)
  343. {
  344. Name (_ADR, 0x00000008)
  345. Method(_RMV, 0x0, NotSerialized)
  346. {
  347. Return (0)
  348. } // End _DSW
  349. }
  350. }
  351. //
  352. // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment
  353. //
  354. Device(EM45)
  355. {
  356. Name(_ADR,0x00170000)
  357. OperationRegion(SDIO, PCI_Config, 0x84,0x4)
  358. Field(SDIO,WordAcc,NoLock,Preserve)
  359. {
  360. Offset(0x00), // 0x84, PMCR
  361. , 8,
  362. PMEE, 1, //PME_EN
  363. , 6,
  364. PMES, 1 //PME_STS
  365. }
  366. Method (_STA, 0x0, NotSerialized)
  367. {
  368. If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))
  369. {
  370. Return(0xF)
  371. }
  372. Else
  373. {
  374. Return(0x0)
  375. }
  376. }
  377. Method(_DSW, 3)
  378. {
  379. } // End _DSW
  380. Device (CARD)
  381. {
  382. Name (_ADR, 0x00000008)
  383. Method(_RMV, 0x0, NotSerialized)
  384. {
  385. Return (0)
  386. } // End _DSW
  387. }
  388. }
  389. //
  390. // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment
  391. //
  392. Device(SD12)
  393. {
  394. Name(_ADR,0x00120000)
  395. Method (_STA, 0x0, NotSerialized)
  396. {
  397. //
  398. // PCIM>> 0:ACPI mode 1:PCI mode
  399. //
  400. If (LEqual(PCIM, 0)) {
  401. Return (0x0)
  402. }
  403. //
  404. // If device is disabled.
  405. //
  406. If (LEqual(SD3D, 1))
  407. {
  408. Return (0x0)
  409. }
  410. Return (0xF)
  411. }
  412. Device (CARD)
  413. {
  414. Name (_ADR, 0x00000008)
  415. Method(_RMV, 0x0, NotSerialized)
  416. {
  417. // SDRM = 0 non-removable;
  418. If (LEqual(SDRM, 0))
  419. {
  420. Return (0)
  421. }
  422. Return (1)
  423. }
  424. }
  425. }
  426. // xHCI Controller - Device 20, Function 0
  427. include("PchXhci.asl")
  428. //
  429. // High Definition Audio Controller - Device 27, Function 0
  430. //
  431. Device(HDEF)
  432. {
  433. Name(_ADR, 0x001B0000)
  434. include("PchAudio.asl")
  435. Method (_STA, 0x0, NotSerialized)
  436. {
  437. If (LEqual(HDAD, 0))
  438. {
  439. Return(0xf)
  440. }
  441. Return(0x0)
  442. }
  443. Method(_DSW, 3)
  444. {
  445. } // End _DSW
  446. } // end "High Definition Audio Controller"
  447. //
  448. // PCIE Root Port #1
  449. //
  450. Device(RP01)
  451. {
  452. Name(_ADR, 0x001C0000)
  453. include("PchPcie.asl")
  454. Name(_PRW, Package() {9, 4})
  455. Method(_PRT,0)
  456. {
  457. If(PICM) { Return(AR04) }// APIC mode
  458. Return (PR04) // PIC Mode
  459. } // end _PRT
  460. } // end "PCIE Root Port #1"
  461. //
  462. // PCIE Root Port #2
  463. //
  464. Device(RP02)
  465. {
  466. Name(_ADR, 0x001C0001)
  467. include("PchPcie.asl")
  468. Name(_PRW, Package() {9, 4})
  469. Method(_PRT,0)
  470. {
  471. If(PICM) { Return(AR05) }// APIC mode
  472. Return (PR05) // PIC Mode
  473. } // end _PRT
  474. } // end "PCIE Root Port #2"
  475. //
  476. // PCIE Root Port #3
  477. //
  478. Device(RP03)
  479. {
  480. Name(_ADR, 0x001C0002)
  481. include("PchPcie.asl")
  482. Name(_PRW, Package() {9, 4})
  483. Method(_PRT,0)
  484. {
  485. If(PICM) { Return(AR06) }// APIC mode
  486. Return (PR06) // PIC Mode
  487. } // end _PRT
  488. } // end "PCIE Root Port #3"
  489. //
  490. // PCIE Root Port #4
  491. //
  492. Device(RP04)
  493. {
  494. Name(_ADR, 0x001C0003)
  495. include("PchPcie.asl")
  496. Name(_PRW, Package() {9, 4})
  497. Method(_PRT,0)
  498. {
  499. If(PICM) { Return(AR07) }// APIC mode
  500. Return (PR07) // PIC Mode
  501. } // end _PRT
  502. } // end "PCIE Root Port #4"
  503. Scope(\_SB)
  504. {
  505. //
  506. // Dummy power resource for USB D3 cold support
  507. //
  508. PowerResource(USBC, 0, 0)
  509. {
  510. Method(_STA) { Return (0xF) }
  511. Method(_ON) {}
  512. Method(_OFF) {}
  513. }
  514. }
  515. //
  516. // EHCI Controller - Device 29, Function 0
  517. //
  518. Device(EHC1)
  519. {
  520. Name(_ADR, 0x001D0000)
  521. Name(_DEP, Package(0x1)
  522. {
  523. PEPD
  524. })
  525. include("PchEhci.asl")
  526. Name(_PRW, Package() {0x0D, 4})
  527. OperationRegion(USBR, PCI_Config, 0x54,0x4)
  528. Field(USBR,WordAcc,NoLock,Preserve)
  529. {
  530. Offset(0x00), // 0x54, PMCR
  531. , 8,
  532. PMEE, 1, //PME_EN
  533. , 6,
  534. PMES, 1 //PME_STS
  535. }
  536. Method (_STA, 0x0, NotSerialized)
  537. {
  538. If(LEqual(XHCI, 0)) //XHCI is not present. It means EHCI is there
  539. {
  540. Return (0xF)
  541. } Else
  542. {
  543. Return (0x0)
  544. }
  545. }
  546. Method (_RMV, 0, NotSerialized)
  547. {
  548. Return (0x0)
  549. }
  550. //
  551. // Create a dummy PR3 method to indicate to the PCI driver
  552. // that the device is capable of D3 cold
  553. //
  554. Method(_PR3, 0x0, NotSerialized)
  555. {
  556. return (Package() {\_SB.USBC})
  557. }
  558. } // end "EHCI Controller"
  559. //
  560. // SMBus Controller - Device 31, Function 3
  561. //
  562. Device(SBUS)
  563. {
  564. Name(_ADR,0x001F0003)
  565. Include("PchSmb.asl")
  566. }
  567. Device(SEC0)
  568. {
  569. Name (_ADR, 0x001a0000) // Device 0x1a, Function 0
  570. Name(_DEP, Package(0x1)
  571. {
  572. PEPD
  573. })
  574. OperationRegion (PMEB, PCI_Config, 0x84, 0x04) //PMECTRLSTATUS
  575. Field (PMEB, WordAcc, NoLock, Preserve)
  576. {
  577. , 8,
  578. PMEE, 1, //bit8 PMEENABLE
  579. , 6,
  580. PMES, 1 //bit15 PMESTATUS
  581. }
  582. // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)
  583. // Arg1 -- integer that contains target system state (0-4)
  584. // Arg2 -- integer that contains the target device state
  585. Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake
  586. {
  587. }
  588. Method (_CRS, 0, NotSerialized)
  589. {
  590. Name (RBUF, ResourceTemplate ()
  591. {
  592. Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)
  593. })
  594. If (LEqual(PAVP, 2))
  595. {
  596. Return (RBUF)
  597. }
  598. Return (ResourceTemplate() {})
  599. }
  600. Method (_STA)
  601. {
  602. If (LNotEqual(PAVP, 0))
  603. {
  604. Return (0xF)
  605. }
  606. Return (0x0)
  607. }
  608. } // Device(SEC0)
  609. } // End scope (\_SB.PCI0)