PCI_DRC.ASL 3.1 KB

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  1. /**************************************************************************;
  2. ;* *;
  3. ;* *;
  4. ;* Intel Corporation - ACPI Reference Code for the Baytrail *;
  5. ;* Family of Customer Reference Boards. *;
  6. ;* *;
  7. ;* *;
  8. ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
  9. ;
  10. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11. ;
  12. ;* *;
  13. ;* *;
  14. ;**************************************************************************/
  15. Scope (\_SB.PCI0)
  16. {
  17. Device(PDRC) // PCI Device Resource Consumption
  18. {
  19. Name(_HID,EISAID("PNP0C02"))
  20. Name(_UID,1)
  21. Name(BUF0,ResourceTemplate()
  22. {
  23. //
  24. // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
  25. // Forced hard code at the moment.
  26. //
  27. //Memory32Fixed(ReadWrite,0,0,PCIX) // PCIEX BAR
  28. Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)
  29. //
  30. // SPI BAR. Check if the hard code meets the real configuration.
  31. // If not, dynamically update it like the _CRS method below.
  32. //
  33. Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR
  34. //
  35. // PMC BAR. Check if the hard code meets the real configuration.
  36. // If not, dynamically update it like the _CRS method below.
  37. //
  38. Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR
  39. //
  40. // SMB BAR. Check if the hard code meets the real configuration.
  41. // If not, dynamically update it like the _CRS method below.
  42. //
  43. Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR
  44. //
  45. // IO BAR. Check if the hard code meets the real configuration.
  46. // If not, dynamically update it like the _CRS method below.
  47. //
  48. Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR
  49. //
  50. // ILB BAR. Check if the hard code meets the real configuration.
  51. // If not, dynamically update it like the _CRS method below.
  52. //
  53. Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR
  54. //
  55. // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h
  56. //
  57. Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR
  58. //
  59. // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
  60. //
  61. Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)
  62. //
  63. // MPHY BAR. Check if the hard code meets the real configuration.
  64. // If not, dynamically update it like the _CRS method below.
  65. //
  66. Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB) // MPHY BAR
  67. })
  68. Method(_CRS,0,Serialized)
  69. {
  70. Return(BUF0)
  71. }
  72. }
  73. }