GloblNvs.asl 13 KB

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  1. /**************************************************************************;
  2. ;* *;
  3. ;* *;
  4. ;* Intel Corporation - ACPI Reference Code for the Baytrail *;
  5. ;* Family of Customer Reference Boards. *;
  6. ;* *;
  7. ;* *;
  8. ;* Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved *;
  9. ;
  10. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11. ;
  12. ;* *;
  13. ;* *;
  14. ;**************************************************************************/
  15. // Define a Global region of ACPI NVS Region that may be used for any
  16. // type of implementation. The starting offset and size will be fixed
  17. // up by the System BIOS during POST. Note that the Size must be a word
  18. // in size to be fixed up correctly.
  19. OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
  20. Field(GNVS,AnyAcc,Lock,Preserve)
  21. {
  22. Offset(0), // Miscellaneous Dynamic Registers:
  23. OSYS, 16, // (00) Operating System
  24. , 8, // (02)
  25. , 8, // (03)
  26. , 8, // (04)
  27. , 8, // (05)
  28. , 8, // (06)
  29. , 8, // (07)
  30. , 8, // (08)
  31. , 8, // (09)
  32. , 8, // (10)
  33. P80D, 32, // (11) Port 80 Debug Port Value
  34. LIDS, 8, // (15) Lid State (Lid Open = 1)
  35. , 8, // (16)
  36. , 8, // (17)
  37. Offset(18), // Thermal Policy Registers:
  38. , 8, // (18)
  39. , 8, // (19)
  40. ACTT, 8, // (20) Active Trip Point
  41. PSVT, 8, // (21) Passive Trip Point
  42. TC1V, 8, // (22) Passive Trip Point TC1 Value
  43. TC2V, 8, // (23) Passive Trip Point TC2 Value
  44. TSPV, 8, // (24) Passive Trip Point TSP Value
  45. CRTT, 8, // (25) Critical Trip Point
  46. DTSE, 8, // (26) Digital Thermal Sensor Enable
  47. DTS1, 8, // (27) Digital Thermal Sensor 1 Reading
  48. DTS2, 8, // (28) Digital Thermal Sensor 2 Reading
  49. DTSF, 8, // (29) DTS SMI Function Call
  50. Offset(30), // Battery Support Registers:
  51. , 8, // (30)
  52. , 8, // (31)
  53. , 8, // (32)
  54. , 8, // (33)
  55. , 8, // (34)
  56. , 8, // (35)
  57. , 8, // (36)
  58. Offset(40), // CPU Identification Registers:
  59. APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1)
  60. MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0
  61. , 8, // (42)
  62. , 8, // (43)
  63. , 8, // (44)
  64. , 32, // (45)
  65. Offset(50), // SIO CMOS Configuration Registers:
  66. , 8, // (50)
  67. , 8, // (51)
  68. , 8, // (52)
  69. , 8, // (53)
  70. , 8, // (54)
  71. , 8, // (55)
  72. , 8, // (56)
  73. , 8, // (57)
  74. , 8, // (58)
  75. Offset(60), // Internal Graphics Registers:
  76. , 8, // (60)
  77. , 8, // (61)
  78. CADL, 8, // (62) Current Attached Device List
  79. , 8, // (63)
  80. CSTE, 16, // (64) Current Display State
  81. NSTE, 16, // (66) Next Display State
  82. , 16, // (68)
  83. NDID, 8, // (70) Number of Valid Device IDs
  84. DID1, 32, // (71) Device ID 1
  85. DID2, 32, // (75) Device ID 2
  86. DID3, 32, // (79) Device ID 3
  87. DID4, 32, // (83) Device ID 4
  88. DID5, 32, // (87) Device ID 5
  89. , 32, // (91)
  90. , 8, // (95) Fifth byte of AKSV (mannufacturing mode)
  91. Offset(103), // Backlight Control Registers:
  92. , 8, // (103)
  93. BRTL, 8, // (104) Brightness Level Percentage
  94. Offset(105), // Ambiant Light Sensor Registers:
  95. , 8, // (105)
  96. , 8, // (106)
  97. LLOW, 8, // (107) LUX Low Value
  98. , 8, // (108)
  99. Offset(110), // EMA Registers:
  100. , 8, // (110)
  101. , 16, // (111)
  102. , 16, // (113)
  103. Offset(116), // MEF Registers:
  104. , 8, // (116) MEF Enable
  105. Offset(117), // PCIe Dock:
  106. , 8, // (117)
  107. Offset(120), // TPM Registers:
  108. , 8, // (120)
  109. , 8, // (121)
  110. , 8, // (122)
  111. , 8, // (123)
  112. , 32, // (124)
  113. , 8, // (125)
  114. , 8, // (129)
  115. Offset(130), //
  116. , 56, // (130)
  117. , 56, // (137)
  118. , 8, // (144)
  119. , 56, // (145)
  120. Offset(170), // IGD OpRegion/Software SCI base address
  121. ASLB, 32, // (170) IGD OpRegion base address
  122. Offset(174), // IGD OpRegion/Software SCI shared data
  123. IBTT, 8, // (174) IGD Boot Display Device
  124. IPAT, 8, // (175) IGD Panel Type CMOs option
  125. ITVF, 8, // (176) IGD TV Format CMOS option
  126. ITVM, 8, // (177) IGD TV Minor Format CMOS option
  127. IPSC, 8, // (178) IGD Panel Scaling
  128. IBLC, 8, // (179) IGD BLC Configuration
  129. IBIA, 8, // (180) IGD BIA Configuration
  130. ISSC, 8, // (181) IGD SSC Configuration
  131. I409, 8, // (182) IGD 0409 Modified Settings Flag
  132. I509, 8, // (183) IGD 0509 Modified Settings Flag
  133. I609, 8, // (184) IGD 0609 Modified Settings Flag
  134. I709, 8, // (185) IGD 0709 Modified Settings Flag
  135. IDMM, 8, // (186) IGD DVMT Mode
  136. IDMS, 8, // (187) IGD DVMT Memory Size
  137. IF1E, 8, // (188) IGD Function 1 Enable
  138. HVCO, 8, // (189) HPLL VCO
  139. NXD1, 32, // (190) Next state DID1 for _DGS
  140. NXD2, 32, // (194) Next state DID2 for _DGS
  141. NXD3, 32, // (198) Next state DID3 for _DGS
  142. NXD4, 32, // (202) Next state DID4 for _DGS
  143. NXD5, 32, // (206) Next state DID5 for _DGS
  144. NXD6, 32, // (210) Next state DID6 for _DGS
  145. NXD7, 32, // (214) Next state DID7 for _DGS
  146. NXD8, 32, // (218) Next state DID8 for _DGS
  147. GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI)
  148. PAVP, 8, // (223) IGD PAVP data
  149. Offset(225),
  150. OSCC, 8, // (225) PCIE OSC Control
  151. NEXP, 8, // (226) Native PCIE Setup Value
  152. Offset(235), // Global Variables
  153. DSEN, 8, // (235) _DOS Display Support Flag.
  154. ECON, 8, // (236) Embedded Controller Availability Flag.
  155. GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag.
  156. CTYP, 8, // (238) Global Cooling Type Flag.
  157. L01C, 8, // (239) Global L01 Counter.
  158. VFN0, 8, // (240) Virtual Fan0 Status.
  159. VFN1, 8, // (241) Virtual Fan1 Status.
  160. Offset(256),
  161. NVGA, 32, // (256) NVIG opregion address
  162. NVHA, 32, // (260) NVHM opregion address
  163. AMDA, 32, // (264) AMDA opregion address
  164. DID6, 32, // (268) Device ID 6
  165. DID7, 32, // (272) Device ID 7
  166. DID8, 32, // (276) Device ID 8
  167. Offset(332),
  168. USEL, 8, // (332) UART Selection
  169. PU1E, 8, // (333) PCU UART 1 Enabled
  170. PU2E, 8, // (334) PCU UART 2 Enabled
  171. LPE0, 32, // (335) LPE Bar0
  172. LPE1, 32, // (339) LPE Bar1
  173. LPE2, 32, // (343) LPE Bar2
  174. Offset(347),
  175. , 8, // (347)
  176. , 8, // (348)
  177. PFLV, 8, // (349) Platform Flavor
  178. Offset(351),
  179. ICNF, 8, // (351) ISCT / AOAC Configuration
  180. XHCI, 8, // (352) xHCI controller mode
  181. PMEN, 8, // (353) PMIC enable/disable
  182. LPEE, 8, // (354) LPE enable/disable
  183. ISPA, 32, // (355) ISP Base Addr
  184. ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
  185. offset(360), // ((4+8+6)*4+2)*4=296
  186. //
  187. // Lpss controllers
  188. //
  189. PCIB, 32,
  190. PCIT, 32,
  191. D10A, 32, //DMA1
  192. D10L, 32,
  193. D11A, 32,
  194. D11L, 32,
  195. P10A, 32, // PWM1
  196. P10L, 32,
  197. P11A, 32,
  198. P11L, 32,
  199. P20A, 32, // PWM2
  200. P20L, 32,
  201. P21A, 32,
  202. P21L, 32,
  203. U10A, 32, // UART1
  204. U10L, 32,
  205. U11A, 32,
  206. U11L, 32,
  207. U20A, 32, // UART2
  208. U20L, 32,
  209. U21A, 32,
  210. U21L, 32,
  211. SP0A, 32, // SPI
  212. SP0L, 32,
  213. SP1A, 32,
  214. SP1L, 32,
  215. D20A, 32, //DMA2
  216. D20L, 32,
  217. D21A, 32,
  218. D21L, 32,
  219. I10A, 32, // I2C1
  220. I10L, 32,
  221. I11A, 32,
  222. I11L, 32,
  223. I20A, 32, // I2C2
  224. I20L, 32,
  225. I21A, 32,
  226. I21L, 32,
  227. I30A, 32, // I2C3
  228. I30L, 32,
  229. I31A, 32,
  230. I31L, 32,
  231. I40A, 32, // I2C4
  232. I40L, 32,
  233. I41A, 32,
  234. I41L, 32,
  235. I50A, 32, // I2C5
  236. I50L, 32,
  237. I51A, 32,
  238. I51L, 32,
  239. I60A, 32, // I2C6
  240. I60L, 32,
  241. I61A, 32,
  242. I61L, 32,
  243. I70A, 32, // I2C7
  244. I70L, 32,
  245. I71A, 32,
  246. I71L, 32,
  247. //
  248. // Scc controllers
  249. //
  250. eM0A, 32, // EMMC
  251. eM0L, 32,
  252. eM1A, 32,
  253. eM1L, 32,
  254. SI0A, 32, // SDIO
  255. SI0L, 32,
  256. SI1A, 32,
  257. SI1L, 32,
  258. SD0A, 32, // SDCard
  259. SD0L, 32,
  260. SD1A, 32,
  261. SD1L, 32,
  262. MH0A, 32, //
  263. MH0L, 32,
  264. MH1A, 32,
  265. MH1L, 32,
  266. offset(656),
  267. SDRM, 8,
  268. offset(657),
  269. HLPS, 8, //(657) Hide Devices
  270. offset(658),
  271. OSEL, 8, //(658) OS Seletion - Windows/Android
  272. offset(659), // VLV1 DPTF
  273. SDP1, 8, //(659) An enumerated value corresponding to SKU
  274. DPTE, 8, //(660) DPTF Enable
  275. THM0, 8, //(661) System Thermal 0
  276. THM1, 8, //(662) System Thermal 1
  277. THM2, 8, //(663) System Thermal 2
  278. THM3, 8, //(664) System Thermal 3
  279. THM4, 8, //(665) System Thermal 3
  280. CHGR, 8, //(666) DPTF Changer Device
  281. DDSP, 8, //(667) DPTF Display Device
  282. DSOC, 8, //(668) DPTF SoC device
  283. DPSR, 8, //(669) DPTF Processor device
  284. DPCT, 32, //(670) DPTF Processor participant critical temperature
  285. DPPT, 32, //(674) DPTF Processor participant passive temperature
  286. DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature
  287. DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature
  288. DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature
  289. DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature
  290. DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature
  291. DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature
  292. DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature
  293. DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature
  294. DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature
  295. DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature
  296. DLPM, 8, //(718) DPTF Current low power mode setting
  297. DSC0, 32, //(719) DPTF Critical threshold0 for SCU
  298. DSC1, 32, //(723) DPTF Critical threshold1 for SCU
  299. DSC2, 32, //(727) DPTF Critical threshold2 for SCU
  300. DSC3, 32, //(731) DPTF Critical threshold3 for SCU
  301. DSC4, 32, //(735) DPTF Critical threshold3 for SCU
  302. DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled
  303. LPOE, 32, //(740) DPTF LPO Enable
  304. LPPS, 32, //(744) P-State start index
  305. LPST, 32, //(748) Step size
  306. LPPC, 32, //(752) Power control setting
  307. LPPF, 32, //(756) Performance control setting
  308. DPME, 8, //(760) DPTF DPPM enable/disable
  309. BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC
  310. NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2
  311. PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode
  312. TPMA, 32, //(764)
  313. TPML, 32, //(768)
  314. ITSA, 8, //(772) I2C Touch Screen Address
  315. S0IX, 8, //(773) S0ix status
  316. SDMD, 8, //(774) SDIO Mode
  317. EMVR, 8, //(775) eMMC controller version
  318. BMBD, 32, //(776) BM Bound
  319. FSAS, 8, //(780) FSA Status
  320. BDID, 8, //(781) Board ID
  321. FBID, 8, //(782) FAB ID
  322. OTGM, 8, //(783) OTG mode
  323. STEP, 8, //(784) Stepping ID
  324. WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test.
  325. SOCS, 8, //(786) provide the SoC stepping infomation
  326. AMTE, 8, //(787) Ambient Trip point change
  327. UTS, 8, //(788) Enable Test Device connected to URT for WHCK test.
  328. SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable
  329. Offset(792),
  330. EDPV, 8, //(792) Check for eDP display device
  331. DIDX, 32, //(793) Device ID for eDP device
  332. IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.
  333. BATT, 8, //(795) The Flag of RTC Battery Prensent.
  334. LPAD, 8, //(796)
  335. }