Mmu.S 3.7 KB

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  1. #------------------------------------------------------------------------------
  2. #
  3. # LoongArch for LoongArch
  4. #
  5. # Copyright (c) 2022 Loongson Technology Corporation Limited. All rights reserved.<BR>
  6. #
  7. # SPDX-License-Identifier: BSD-2-Clause-Patent
  8. #
  9. #-----------------------------------------------------------------------------
  10. #ifndef __ASSEMBLY__
  11. #define __ASSEMBLY__
  12. #endif
  13. #include "Library/Cpu.h"
  14. #include "mmu.h"
  15. ASM_GLOBAL ASM_PFX(HandleTlbRefill)
  16. ASM_GLOBAL HandleTlbRefillEnd
  17. ASM_GLOBAL ASM_PFX(LoongarchInvalidTlb)
  18. ASM_GLOBAL ASM_PFX(SetTlbRefillFuncBase)
  19. ASM_GLOBAL ASM_PFX(WriteCsrPageSize)
  20. ASM_GLOBAL ASM_PFX(WriteCsrTlbRefillPageSize)
  21. ASM_GLOBAL ASM_PFX(WriteCsrStlbPageSize)
  22. ASM_GLOBAL ASM_PFX(LoongArchWriteqCsrPwctl0)
  23. ASM_GLOBAL ASM_PFX(LoongArchWriteqCsrPwctl1)
  24. ASM_GLOBAL ASM_PFX(LoongArchWriteqCsrPgdl)
  25. ASM_GLOBAL ASM_PFX(LoongArchWriteqCsrPgdh)
  26. ASM_GLOBAL ASM_PFX(LoongArchXchgCsrCrmd)
  27. #
  28. # Refill the page table.
  29. # @param VOID
  30. # @retval VOID
  31. #
  32. ASM_PFX(HandleTlbRefill):
  33. csrwr T0, LOONGARCH_CSR_TLBRSAVE
  34. csrrd T0, LOONGARCH_CSR_PGD
  35. lddir T0, T0, 3 #Put pud BaseAddress into T0
  36. lddir T0, T0, 2 #Put pmd BaseAddress into T0
  37. lddir T0, T0, 1 #Put pte BaseAddress into T0
  38. ldpte T0, 0
  39. ldpte T0, 1
  40. tlbfill
  41. csrrd T0, LOONGARCH_CSR_TLBRSAVE
  42. ertn
  43. HandleTlbRefillEnd:
  44. #
  45. # Invalid corresponding TLB entries are based on the address given
  46. # @param A0 The address corresponding to the invalid page table entry
  47. # @retval none
  48. #
  49. ASM_PFX(LoongarchInvalidTlb):
  50. invtlb INVTLB_ADDR_GTRUE_OR_ASID, ZERO, A0
  51. jirl ZERO, RA, 0
  52. #
  53. # Set Tlb Refill function to hardware
  54. # @param A0 The address of tlb refill function
  55. # @retval none
  56. #
  57. ASM_PFX(SetTlbRefillFuncBase):
  58. csrwr A0, LOONGARCH_CSR_TLBREBASE
  59. jirl ZERO, RA,0
  60. #
  61. # Set Cpu Status Register Page Size.
  62. # @param A0 Page Size.
  63. # @retval none
  64. #
  65. ASM_PFX(WriteCsrPageSize):
  66. li.d T0, CSR_TLBIDX_SIZE
  67. sll.d A0, A0, T0
  68. li.d T0, CSR_TLBIDX_SIZE_MASK
  69. csrxchg A0, T0, LOONGARCH_CSR_TLBIDX
  70. jirl ZERO, RA,0
  71. #
  72. # Set Cpu Status Register TLBREFILL Page Size.
  73. # @param A0 Page Size.
  74. # @retval none
  75. #
  76. ASM_PFX(WriteCsrTlbRefillPageSize):
  77. li.d T0, CSR_TLBREHI_PS_SHIFT
  78. sll.d A0, A0, T0
  79. li.d T0, CSR_TLBREHI_PS
  80. csrxchg A0, T0, LOONGARCH_CSR_TLBREHI
  81. jirl ZERO, RA,0
  82. #
  83. # Set Cpu Status Register STLB Page Size.
  84. # @param val Page Size.
  85. # @retval VOID
  86. #
  87. ASM_PFX(WriteCsrStlbPageSize):
  88. csrwr A0, LOONGARCH_CSR_STLBPGSIZE
  89. jirl ZERO, RA,0
  90. #
  91. # Write Csr PWCTL0 register.
  92. # @param A0 The value used to write to the PWCTL0 register
  93. # @retval none
  94. #
  95. ASM_PFX(LoongArchWriteqCsrPwctl0):
  96. csrwr A0, LOONGARCH_CSR_PWCTL0
  97. jirl ZERO, RA,0
  98. #
  99. # Write Csr PWCTL1 register.
  100. # @param A0 The value used to write to the PWCTL1 register
  101. # @retval none
  102. #
  103. ASM_PFX(LoongArchWriteqCsrPwctl1):
  104. csrwr A0, LOONGARCH_CSR_PWCTL1
  105. jirl ZERO, RA,0
  106. #
  107. # Write Csr PGDL register.
  108. # @param A0 The value used to write to the PGDL register
  109. # @retval none
  110. #
  111. ASM_PFX(LoongArchWriteqCsrPgdl):
  112. csrwr A0, LOONGARCH_CSR_PGDL
  113. jirl ZERO, RA,0
  114. #
  115. # Write Csr PGDH register.
  116. # @param A0 The value used to write to the PGDH register
  117. # @retval none
  118. #
  119. ASM_PFX(LoongArchWriteqCsrPgdh):
  120. csrwr A0, LOONGARCH_CSR_PGDH
  121. jirl ZERO, RA,0
  122. #
  123. # Exchange specified bit data with the Csr CRMD register.
  124. # @param[IN] A0 The value Exchanged with the CSR CRMD register.
  125. # @param[IN] A1 Specifies the mask for swapping bits
  126. # @retval VOID
  127. #
  128. ASM_PFX(LoongArchXchgCsrCrmd):
  129. csrxchg A0, A1, LOONGARCH_CSR_CRMD
  130. jirl ZERO, RA,0