SiliconPolicyUpdateLibFsp.c 33 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770
  1. /** @file
  2. This file is SampleCode of the library for Intel PCH PEI Policy initialzation.
  3. @copyright
  4. Copyright 2004 - 2021 Intel Corporation. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <PiPei.h>
  8. #include "Guid/SetupVariable.h"
  9. #include <PchSetupVariable.h>
  10. #include <Library/DebugLib.h>
  11. #include <Library/IoLib.h>
  12. #include <Ppi/ReadOnlyVariable2.h>
  13. #include <Library/PeiServicesLib.h>
  14. #include <PchAccess.h>
  15. #include <Ppi/PchPolicy.h>
  16. #include <Register/PchRegsSata.h>
  17. #include <Library/HobLib.h>
  18. #include <Platform.h>
  19. #include <Library/BaseMemoryLib.h>
  20. #include <Library/MemoryAllocationLib.h>
  21. #include <Library/HobLib.h>
  22. #include <Guid/GlobalVariable.h>
  23. #include <Ppi/PchPcieDeviceTable.h>
  24. #include <Guid/SocketVariable.h>
  25. #include <Library/PcdLib.h>
  26. #include <Library/PchInfoLib.h>
  27. #include <Library/UbaUsbOcUpdateLib.h>
  28. #include <Library/UbaHsioPtssTableConfigLib.h>
  29. #include <Ppi/DynamicSiLibraryPpi.h>
  30. #include <FspmUpd.h>
  31. //
  32. // Haddock Creek
  33. //
  34. #define DIMM_SMB_SPD_P0C0D0_HC 0xA2
  35. #define DIMM_SMB_SPD_P0C0D1_HC 0xA0
  36. #define DIMM_SMB_SPD_P0C1D0_HC 0xA6
  37. #define DIMM_SMB_SPD_P0C1D1_HC 0xA4
  38. #define DIMM_SMB_SPD_P0C0D2_HC 0xAA
  39. #define DIMM_SMB_SPD_P0C1D2_HC 0xA8
  40. //
  41. // Sawtooth Peak
  42. // Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
  43. //
  44. #define DIMM_SMB_SPD_P0C0D0_STP 0xA2
  45. #define DIMM_SMB_SPD_P0C0D1_STP 0xA0
  46. #define DIMM_SMB_SPD_P0C1D0_STP 0xA2
  47. #define DIMM_SMB_SPD_P0C1D1_STP 0xA0
  48. //
  49. // Aden Hills
  50. // DDR4 System (1DPC)
  51. //
  52. #define DIMM_SMB_SPD_P0C0D0_AH 0xA0
  53. #define DIMM_SMB_SPD_P0C0D1_AH 0xA4
  54. #define DIMM_SMB_SPD_P0C1D0_AH 0xA2
  55. #define DIMM_SMB_SPD_P0C1D1_AH 0xA6
  56. GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] = {
  57. DIMM_SMB_SPD_P0C0D0_HC,
  58. DIMM_SMB_SPD_P0C0D1_HC,
  59. DIMM_SMB_SPD_P0C1D0_HC,
  60. DIMM_SMB_SPD_P0C1D1_HC
  61. };
  62. GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] = {
  63. DIMM_SMB_SPD_P0C0D0_STP,
  64. DIMM_SMB_SPD_P0C0D1_STP,
  65. DIMM_SMB_SPD_P0C1D0_STP,
  66. DIMM_SMB_SPD_P0C1D1_STP
  67. };
  68. GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] = {
  69. DIMM_SMB_SPD_P0C0D0_AH,
  70. DIMM_SMB_SPD_P0C0D1_AH,
  71. DIMM_SMB_SPD_P0C1D0_AH,
  72. DIMM_SMB_SPD_P0C1D1_AH
  73. };
  74. #define PCI_CLASS_NETWORK 0x02
  75. #define PCI_CLASS_NETWORK_ETHERNET 0x00
  76. #define PCI_CLASS_NETWORK_OTHER 0x80
  77. GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
  78. //
  79. // Intel PRO/Wireless
  80. //
  81. { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  82. { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  83. { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  84. { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  85. //
  86. // Intel WiMAX/WiFi Link
  87. //
  88. { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  89. { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  90. { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  91. { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  92. { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  93. { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  94. { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  95. { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  96. { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  97. { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  98. //
  99. // Intel Crane Peak WLAN NIC
  100. //
  101. { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  102. { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  103. //
  104. // Intel Crane Peak w/BT WLAN NIC
  105. //
  106. { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  107. { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  108. //
  109. // Intel Kelsey Peak WiFi, WiMax
  110. //
  111. { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  112. { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  113. //
  114. // Intel Centrino Wireless-N 105
  115. //
  116. { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  117. { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  118. //
  119. // Intel Centrino Wireless-N 135
  120. //
  121. { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  122. { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  123. //
  124. // Intel Centrino Wireless-N 2200
  125. //
  126. { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  127. { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  128. //
  129. // Intel Centrino Wireless-N 2230
  130. //
  131. { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  132. { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  133. //
  134. // Intel Centrino Wireless-N 6235
  135. //
  136. { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  137. { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  138. //
  139. // Intel CampPeak 2 Wifi
  140. //
  141. { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  142. { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  143. //
  144. // Intel WilkinsPeak 1 Wifi
  145. //
  146. { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  147. { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  148. { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  149. { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  150. //
  151. // Intel Wilkins Peak 2 Wifi
  152. //
  153. { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  154. { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  155. { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  156. { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  157. //
  158. // Intel Wilkins Peak PF Wifi
  159. //
  160. { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  161. //
  162. // End of Table
  163. //
  164. { 0 }
  165. };
  166. STATIC
  167. EFI_STATUS
  168. InstallPcieDeviceTable (
  169. IN PCH_PCIE_DEVICE_OVERRIDE *DeviceTable
  170. )
  171. {
  172. EFI_PEI_PPI_DESCRIPTOR *DeviceTablePpiDesc;
  173. EFI_STATUS Status;
  174. DeviceTablePpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
  175. ASSERT (DeviceTablePpiDesc != NULL);
  176. if (DeviceTablePpiDesc == NULL) {
  177. return EFI_OUT_OF_RESOURCES;
  178. }
  179. DeviceTablePpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
  180. DeviceTablePpiDesc->Guid = &gPchPcieDeviceTablePpiGuid;
  181. DeviceTablePpiDesc->Ppi = DeviceTable;
  182. Status = PeiServicesInstallPpi (DeviceTablePpiDesc);
  183. ASSERT_EFI_ERROR (Status);
  184. return Status;
  185. }
  186. VOID
  187. UpdatePchUsbConfig (
  188. IN PCH_USB_CONFIG *PchUsbConfig,
  189. IN SYSTEM_CONFIGURATION *SetupVariables,
  190. IN PCH_SETUP *PchRcVariables,
  191. IN VOID *Usb20OverCurrentMappings,
  192. IN VOID *Usb30OverCurrentMappings,
  193. IN VOID *Usb20AfeParams
  194. );
  195. static
  196. VOID
  197. InstallPlatformVerbTables (
  198. IN UINTN CodecType
  199. )
  200. {
  201. }
  202. EFI_STATUS
  203. EFIAPI
  204. UpdatePeiPchPolicy (
  205. IN OUT PCH_POLICY_PPI *PchPolicy
  206. )
  207. /*++
  208. Routine Description:
  209. This function performs PCH PEI Policy initialzation.
  210. Arguments:
  211. PchPolicy The PCH Policy PPI instance
  212. Returns:
  213. EFI_SUCCESS The PPI is installed and initialized.
  214. EFI ERRORS The PPI is not successfully installed.
  215. EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
  216. --*/
  217. {
  218. UINT8 Index;
  219. UINTN LpcBaseAddress;
  220. UINT8 MaxSataPorts;
  221. UINT8 BmcRootPort;
  222. UINT8 *SmBusReservedTable;
  223. UINT8 SmBusReservedNum;
  224. USB_OVERCURRENT_PIN *Usb20OverCurrentMappings=NULL;
  225. USB_OVERCURRENT_PIN *Usb30OverCurrentMappings=NULL;
  226. USB2_PHY_PARAMETERS *Usb20AfeParams = NULL;
  227. UINT8 VTdSupport;
  228. SYSTEM_CONFIGURATION *SetupVariables;
  229. PCH_SETUP *PchRcVariables;
  230. FSPM_UPD *FspmUpd;
  231. EFI_STATUS Status = EFI_SUCCESS;
  232. DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
  233. DEBUG((DEBUG_INFO, "platform common UpdatePeiPchPolicy entry\n"));
  234. Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, (VOID **) &DynamicSiLibraryPpi);
  235. if (EFI_ERROR (Status)) {
  236. ASSERT_EFI_ERROR (Status);
  237. return Status;
  238. }
  239. FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
  240. ASSERT (FspmUpd != NULL);
  241. SetupVariables = PcdGetPtr(PcdSetup);
  242. PchRcVariables = PcdGetPtr(PcdPchSetup);
  243. LpcBaseAddress = DynamicSiLibraryPpi->MmPciBase (
  244. DEFAULT_PCI_BUS_NUMBER_PCH,
  245. PCI_DEVICE_NUMBER_PCH_LPC,
  246. PCI_FUNCTION_NUMBER_PCH_LPC
  247. );
  248. PchPolicy->Port80Route = PchRcVariables->IchPort80Route;
  249. //
  250. // DeviceEnables
  251. //
  252. if (DynamicSiLibraryPpi->PchIsGbeAvailable ()) {
  253. PchPolicy->LanConfig.Enable = TRUE;
  254. PchPolicy->LanConfig.K1OffEnable = PchRcVariables->PchLanK1Off;
  255. } else {
  256. PchPolicy->LanConfig.Enable = FALSE;
  257. }
  258. PchPolicy->SataConfig.Enable = PchRcVariables->PchSata;
  259. PchPolicy->sSataConfig.Enable = PchRcVariables->PchsSata;
  260. PchPolicy->SmbusConfig.Enable = TRUE;
  261. //
  262. // CLOCKRUN in LPC has to be disabled:
  263. // - if a device is connected to LPC0
  264. // - for LBG A0 stepping
  265. //
  266. PchPolicy->PmConfig.PciClockRun = FALSE;
  267. PchPolicy->PchConfig.Crid = PchRcVariables->PchCrid;
  268. PchPolicy->PchConfig.Serm = PchRcVariables->PchSerm;
  269. //
  270. // SMBUS reserved addresses
  271. //
  272. SmBusReservedTable = NULL;
  273. SmBusReservedNum = 0;
  274. PchPolicy->SmbusConfig.SmbusIoBase = PCH_SMBUS_BASE_ADDRESS;
  275. SmBusReservedTable = mSmbusSTPRsvdAddresses;
  276. SmBusReservedNum = sizeof (mSmbusSTPRsvdAddresses);
  277. if (SmBusReservedTable != NULL) {
  278. PchPolicy->SmbusConfig.NumRsvdSmbusAddresses = SmBusReservedNum;
  279. CopyMem (
  280. PchPolicy->SmbusConfig.RsvdSmbusAddressTable,
  281. SmBusReservedTable,
  282. SmBusReservedNum
  283. );
  284. }
  285. //
  286. // SATA Config
  287. //
  288. PchPolicy->SataConfig.SataMode = PchRcVariables->SataInterfaceMode;
  289. MaxSataPorts = DynamicSiLibraryPpi->GetPchMaxSataPortNum ();
  290. for (Index = 0; Index < MaxSataPorts; Index++) {
  291. if (PchRcVariables->SataTestMode == TRUE)
  292. {
  293. PchPolicy->SataConfig.PortSettings[Index].Enable = TRUE;
  294. } else {
  295. PchPolicy->SataConfig.PortSettings[Index].Enable = PchRcVariables->SataPort[Index];
  296. }
  297. PchPolicy->SataConfig.PortSettings[Index].HotPlug = PchRcVariables->SataHotPlug[Index];
  298. PchPolicy->SataConfig.PortSettings[Index].SpinUp = PchRcVariables->SataSpinUp[Index];
  299. PchPolicy->SataConfig.PortSettings[Index].External = PchRcVariables->SataExternal[Index];
  300. PchPolicy->SataConfig.PortSettings[Index].DevSlp = PchRcVariables->PxDevSlp[Index];
  301. PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->EnableDitoConfig[Index];
  302. PchPolicy->SataConfig.PortSettings[Index].DmVal = PchRcVariables->DmVal[Index];
  303. PchPolicy->SataConfig.PortSettings[Index].DitoVal = PchRcVariables->DitoVal[Index];
  304. PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->SataType[Index];
  305. }
  306. if (PchPolicy->SataConfig.SataMode == PchSataModeRaid) {
  307. PchPolicy->SataConfig.Rst.RaidAlternateId = PchRcVariables->SataAlternateId;
  308. PchPolicy->SataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->SataRaidLoadEfiDriver[0];
  309. }
  310. PchPolicy->SataConfig.Rst.Raid0 = PchRcVariables->SataRaidR0;
  311. PchPolicy->SataConfig.Rst.Raid1 = PchRcVariables->SataRaidR1;
  312. PchPolicy->SataConfig.Rst.Raid10 = PchRcVariables->SataRaidR10;
  313. PchPolicy->SataConfig.Rst.Raid5 = PchRcVariables->SataRaidR5;
  314. PchPolicy->SataConfig.Rst.Irrt = PchRcVariables->SataRaidIrrt;
  315. PchPolicy->SataConfig.Rst.OromUiBanner = PchRcVariables->SataRaidOub;
  316. PchPolicy->SataConfig.Rst.HddUnlock = PchRcVariables->SataHddlk;
  317. PchPolicy->SataConfig.Rst.LedLocate = PchRcVariables->SataLedl;
  318. PchPolicy->SataConfig.Rst.IrrtOnly = PchRcVariables->SataRaidIooe;
  319. PchPolicy->SataConfig.Rst.SmartStorage = PchRcVariables->SataRaidSrt;
  320. PchPolicy->SataConfig.Rst.OromUiDelay = PchRcVariables->SataRaidOromDelay;
  321. PchPolicy->SataConfig.EnclosureSupport = TRUE;
  322. PchPolicy->SataConfig.SalpSupport = PchRcVariables->SataSalp;
  323. PchPolicy->SataConfig.TestMode = PchRcVariables->SataTestMode;
  324. for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
  325. if ((PchRcVariables->PchSata == TRUE) && (PchRcVariables->SataInterfaceMode == PchSataModeRaid)) {
  326. PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = PchRcVariables->RstPcieStorageRemap[Index];
  327. PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = PchRcVariables->RstPcieStorageRemapPort[Index];
  328. } else {
  329. PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = FALSE;
  330. }
  331. }
  332. //
  333. // sSATA Config
  334. //
  335. PchPolicy->sSataConfig.SataMode = PchRcVariables->sSataInterfaceMode;
  336. MaxSataPorts = DynamicSiLibraryPpi->GetPchMaxsSataPortNum ();
  337. for (Index = 0; Index < MaxSataPorts; Index++) {
  338. if (PchRcVariables->sSataTestMode == TRUE)
  339. {
  340. PchPolicy->sSataConfig.PortSettings[Index].Enable = TRUE;
  341. } else {
  342. PchPolicy->sSataConfig.PortSettings[Index].Enable = PchRcVariables->sSataPort[Index];
  343. }
  344. PchPolicy->sSataConfig.PortSettings[Index].HotPlug = PchRcVariables->sSataHotPlug[Index];
  345. PchPolicy->sSataConfig.PortSettings[Index].SpinUp = PchRcVariables->sSataSpinUp[Index];
  346. PchPolicy->sSataConfig.PortSettings[Index].External = PchRcVariables->sSataExternal[Index];
  347. PchPolicy->sSataConfig.PortSettings[Index].DevSlp = PchRcVariables->sPxDevSlp[Index];
  348. PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->sEnableDitoConfig[Index];
  349. PchPolicy->sSataConfig.PortSettings[Index].DmVal = PchRcVariables->sDmVal[Index];
  350. PchPolicy->sSataConfig.PortSettings[Index].DitoVal = PchRcVariables->sDitoVal[Index];
  351. PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->sSataType[Index];
  352. }
  353. if (PchPolicy->sSataConfig.SataMode == PchSataModeRaid) {
  354. PchPolicy->sSataConfig.Rst.RaidAlternateId = PchRcVariables->sSataAlternateId;
  355. PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->SataRaidLoadEfiDriver[0];;
  356. }
  357. PchPolicy->sSataConfig.Rst.Raid0 = PchRcVariables->sSataRaidR0;
  358. PchPolicy->sSataConfig.Rst.Raid1 = PchRcVariables->sSataRaidR1;
  359. PchPolicy->sSataConfig.Rst.Raid10 = PchRcVariables->sSataRaidR10;
  360. PchPolicy->sSataConfig.Rst.Raid5 = PchRcVariables->sSataRaidR5;
  361. PchPolicy->sSataConfig.Rst.Irrt = PchRcVariables->sSataRaidIrrt;
  362. PchPolicy->sSataConfig.Rst.OromUiBanner = PchRcVariables->sSataRaidOub;
  363. PchPolicy->sSataConfig.Rst.HddUnlock = PchRcVariables->sSataHddlk;
  364. PchPolicy->sSataConfig.Rst.LedLocate = PchRcVariables->sSataLedl;
  365. PchPolicy->sSataConfig.Rst.IrrtOnly = PchRcVariables->sSataRaidIooe;
  366. PchPolicy->sSataConfig.Rst.SmartStorage = PchRcVariables->sSataRaidSrt;
  367. PchPolicy->sSataConfig.Rst.OromUiDelay = PchRcVariables->sSataRaidOromDelay;
  368. PchPolicy->sSataConfig.EnclosureSupport = TRUE;
  369. PchPolicy->sSataConfig.SalpSupport = PchRcVariables->sSataSalp;
  370. PchPolicy->sSataConfig.TestMode = PchRcVariables->sSataTestMode;
  371. //
  372. // Initiate DMI Configuration
  373. //
  374. if (SetupVariables->PcieDmiAspm != PLATFORM_POR) {
  375. if (SetupVariables->PcieDmiAspm != 0xFF) {
  376. PchPolicy->DmiConfig.DmiAspm = TRUE;
  377. } else {
  378. PchPolicy->DmiConfig.DmiAspm = FALSE;
  379. }
  380. }
  381. DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =%x\n", PchPolicy->DmiConfig.DmiAspm));
  382. //
  383. // PCI express config
  384. //
  385. PchPolicy->PcieConfig.DisableRootPortClockGating = SetupVariables->PcieClockGatingDisabled;
  386. PchPolicy->PcieConfig.EnablePort8xhDecode = PchRcVariables->PcieRootPort8xhDecode;
  387. PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex = PchRcVariables->Pcie8xhDecodePortIndex;
  388. PchPolicy->PcieConfig.EnablePeerMemoryWrite = PchRcVariables->PcieRootPortPeerMemoryWriteEnable;
  389. PchPolicy->PcieConfig.ComplianceTestMode = PchRcVariables->PcieComplianceTestMode;
  390. ///
  391. /// Temporary WA: Force Link speed on BMC board to GEN1
  392. /// TODO: remove this WA together with Purley platforms support
  393. ///
  394. BmcRootPort = PcdGet8(PcdOemSkuBmcPciePortNumber);
  395. if ((BmcRootPort != 0xFF) && (BmcRootPort < ARRAY_SIZE(PchRcVariables->PcieRootPortSpeed))) {
  396. DEBUG ((DEBUG_INFO, "WA Force Link Speed to GEN1: PciePort: %d", BmcRootPort));
  397. PchRcVariables->PcieRootPortSpeed[BmcRootPort] = 1;
  398. }
  399. for (Index = 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); Index++) {
  400. PchPolicy->PcieConfig.RootPort[Index].Enable = PchRcVariables->PcieRootPortEn[Index];
  401. PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = (UINT8) Index;
  402. if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) {
  403. // Disabled a.k.a. Per individual port
  404. PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PchPcieGlobalAspm;
  405. } else {
  406. PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PcieRootPortAspm[Index];
  407. }
  408. PchPolicy->PcieConfig.RootPort[Index].L1Substates = PchRcVariables->PcieRootPortL1SubStates[Index];
  409. PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = PchRcVariables->PcieRootPortACS[Index];
  410. PchPolicy->PcieConfig.RootPort[Index].PmSci = PchRcVariables->PcieRootPortPMCE[Index];
  411. PchPolicy->PcieConfig.RootPort[Index].HotPlug = PchRcVariables->PcieRootPortHPE[Index];
  412. PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = PchRcVariables->PcieRootPortAER[Index];
  413. PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = PchRcVariables->PcieRootPortURE[Index];
  414. PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = PchRcVariables->PcieRootPortFEE[Index];
  415. PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = PchRcVariables->PcieRootPortNFE[Index];
  416. PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = PchRcVariables->PcieRootPortCEE[Index];
  417. PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = PchRcVariables->PcieRootPortSFE[Index];
  418. PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = PchRcVariables->PcieRootPortSNE[Index];
  419. PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = PchRcVariables->PcieRootPortSCE[Index];
  420. PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = PchRcVariables->PcieRootPortTHS[Index];
  421. PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = PchRcVariables->PcieRootPortCompletionTimeout[Index];
  422. PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = PchRcVariables->PcieRootPortSpeed[Index];
  423. PchPolicy->PcieConfig.RootPort[Index].MaxPayload = PchRcVariables->PcieRootPortMaxPayLoadSize[Index];
  424. PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = PchRcVariables->PcieRootPortEqPh3Method[Index];
  425. PchPolicy->PcieConfig.RootPort[Index].SlotImplemented = TRUE;
  426. }
  427. PchPolicy->PcieConfig.RootPort[BmcRootPort].SlotImplemented = FALSE;
  428. for (Index = 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); ++Index) {
  429. PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm = PchRcVariables->PcieLaneCm[Index];
  430. PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp = PchRcVariables->PcieLaneCp[Index];
  431. }
  432. if (PchRcVariables->PcieSwEqOverride) {
  433. for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) {
  434. PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm = PchRcVariables->PcieSwEqCoeffCm[Index];
  435. PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp = PchRcVariables->PcieSwEqCoeffCp[Index];
  436. }
  437. }
  438. PchPolicy->PcieConfig.MaxReadRequestSize = PchRcVariables->PcieRootPortMaxReadRequestSize;
  439. ///
  440. /// Update Competion Timeout settings for Upling ports for Server PCH
  441. ///
  442. PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = PchRcVariables->PchPcieUX16CompletionTimeout;
  443. PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = PchRcVariables->PchPcieUX8CompletionTimeout;
  444. ///
  445. /// Update Max Payload Size settings for Upling ports for Server PCH
  446. ///
  447. PchPolicy->PcieConfig.PchPcieUX16MaxPayload = PchRcVariables->PchPcieUX16MaxPayloadSize;
  448. PchPolicy->PcieConfig.PchPcieUX8MaxPayload = PchRcVariables->PchPcieUX8MaxPayloadSize;
  449. CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfig) + OFFSET_OF(SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport));
  450. PchPolicy->PcieConfig.VTdSupport = VTdSupport;
  451. ///
  452. /// Assign ClkReq signal to root port. (Base 0)
  453. /// For LP, Set 0 - 5
  454. /// For H, Set 0 - 15
  455. /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port. (TODO for Purley)
  456. ///
  457. //
  458. // HdAudioConfig
  459. //
  460. PchPolicy->HdAudioConfig.Enable = PchRcVariables->PchHdAudio;
  461. PchPolicy->HdAudioConfig.DspEnable = FALSE;
  462. PchPolicy->HdAudioConfig.Pme = PchRcVariables->PchHdAudioPme;
  463. PchPolicy->HdAudioConfig.IoBufferOwnership = PchRcVariables->PchHdAudioIoBufferOwnership;
  464. PchPolicy->HdAudioConfig.IoBufferVoltage = PchRcVariables->PchHdAudioIoBufferVoltage;
  465. PchPolicy->HdAudioConfig.ResetWaitTimer = 300;
  466. PchPolicy->HdAudioConfig.IDispCodecDisconnect = TRUE; //iDisp is permanently disabled
  467. for(Index = 0; Index < HDAUDIO_FEATURES; Index++) {
  468. PchPolicy->HdAudioConfig.DspFeatureMask |= (UINT32)(PchRcVariables->PchHdAudioFeature[Index] ? (1 << Index) : 0);
  469. }
  470. for(Index = 0; Index < HDAUDIO_PP_MODULES; Index++) {
  471. PchPolicy->HdAudioConfig.DspPpModuleMask |= (UINT32)(PchRcVariables->PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0);
  472. }
  473. if (PchPolicy->HdAudioConfig.Enable) {
  474. InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect);
  475. }
  476. PchPolicy->HdAudioConfig.VcType = PchRcVariables->DfxHdaVcType;
  477. //
  478. // LockDown
  479. //
  480. PchPolicy->LockDownConfig.RtcLock = PchRcVariables->PchRtcLock;
  481. PchPolicy->LockDownConfig.SpiEiss = TRUE;
  482. PchPolicy->LockDownConfig.GlobalSmi = TRUE;
  483. PchPolicy->LockDownConfig.BiosInterface = TRUE;
  484. PchPolicy->LockDownConfig.GpioLockDown = PchRcVariables->PchGpioLockDown;
  485. PchPolicy->LockDownConfig.TcoLock = TRUE;
  486. if(PchRcVariables->PchP2sbUnlock) {
  487. PchPolicy->P2sbConfig.SbiUnlock = TRUE;
  488. PchPolicy->P2sbConfig.PsfUnlock = TRUE;
  489. } else {
  490. PchPolicy->P2sbConfig.SbiUnlock = FALSE;
  491. PchPolicy->P2sbConfig.PsfUnlock = FALSE;
  492. }
  493. PchPolicy->P2sbConfig.P2SbReveal = PchRcVariables->PchP2sbDevReveal;
  494. //
  495. // Update SPI policies
  496. //
  497. PchPolicy->SpiConfig.ShowSpiController = TRUE;
  498. PchPolicy->PmConfig.PmcReadDisable = TRUE;
  499. if (PchRcVariables->PchAdrEn != PLATFORM_POR) {
  500. PchPolicy->AdrConfig.PchAdrEn = PchRcVariables->PchAdrEn;
  501. }
  502. PchPolicy->AdrConfig.AdrGpioSel = PchRcVariables->AdrGpioSel;
  503. if (PchRcVariables->AdrHostPartitionReset != PLATFORM_POR) {
  504. PchPolicy->AdrConfig.AdrHostPartitionReset = PchRcVariables->AdrHostPartitionReset;
  505. }
  506. if (PchRcVariables->AdrTimerEn != PLATFORM_POR) {
  507. PchPolicy->AdrConfig.AdrTimerEn = PchRcVariables->AdrTimerEn;
  508. }
  509. if (PchRcVariables->AdrTimerVal != ADR_TMR_SETUP_DEFAULT_POR) {
  510. PchPolicy->AdrConfig.AdrTimerVal = PchRcVariables->AdrTimerVal;
  511. }
  512. if (PchRcVariables->AdrMultiplierVal != ADR_MULT_SETUP_DEFAULT_POR) {
  513. PchPolicy->AdrConfig.AdrMultiplierVal = PchRcVariables->AdrMultiplierVal;
  514. }
  515. //
  516. // Thermal Config
  517. //
  518. if ((PchRcVariables->MemoryThermalManagement != FALSE) &&
  519. ((PchRcVariables->ExttsViaTsOnBoard != FALSE) || (PchRcVariables->ExttsViaTsOnDimm != FALSE)))
  520. {
  521. PchPolicy->ThermalConfig.MemoryThrottling.Enable = TRUE;
  522. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE;
  523. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE;
  524. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE;
  525. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE;
  526. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PinSelection = 1;
  527. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PinSelection = 0;
  528. } else {
  529. PchPolicy->ThermalConfig.MemoryThrottling.Enable = FALSE;
  530. }
  531. //
  532. // IOAPIC Config
  533. //
  534. PchPolicy->IoApicConfig.IoApicEntry24_119 = PchRcVariables->PchIoApic24119Entries;
  535. PchPolicy->IoApicConfig.BdfValid = 1;
  536. PchPolicy->IoApicConfig.BusNumber = PCI_BUS_NUMBER_PCH_IOAPIC;
  537. PchPolicy->IoApicConfig.DeviceNumber = PCI_DEVICE_NUMBER_PCH_IOAPIC;
  538. PchPolicy->IoApicConfig.FunctionNumber = PCI_FUNCTION_NUMBER_PCH_IOAPIC;
  539. //
  540. // Misc PM Config
  541. //
  542. PchPolicy->PmConfig.PchDeepSxPol = PchRcVariables->DeepSxMode;
  543. PchPolicy->PmConfig.WakeConfig.WolEnableOverride = PchRcVariables->PchWakeOnLan;
  544. PchPolicy->PmConfig.WakeConfig.WoWlanEnable = PchRcVariables->PchWakeOnWlan;
  545. PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable = PchRcVariables->PchWakeOnWlanDeepSx;
  546. PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx = PchRcVariables->Gp27WakeFromDeepSx;
  547. PchPolicy->PmConfig.SlpLanLowDc = PchRcVariables->PchSlpLanLowDc;
  548. PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts = TRUE;
  549. PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts = TRUE;
  550. PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts = TRUE;
  551. PchPolicy->PmConfig.PciePllSsc = PchRcVariables->PciePllSsc;
  552. PchPolicy->PmConfig.Dwr_BmcRootPort = PchRcVariables->Dwr_BmcRootPort;
  553. PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL = PchRcVariables->DwrEn_PMCGBL;
  554. PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT = PchRcVariables->DwrEn_MEWDT;
  555. PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT = PchRcVariables->DwrEn_IEWDT;
  556. //
  557. // DefaultSvidSid Config
  558. //
  559. PchPolicy->PchConfig.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
  560. PchPolicy->PchConfig.SubSystemId = V_PCH_DEFAULT_SID;
  561. PchPolicy->PchConfig.EnableClockSpreadSpec = PchRcVariables->EnableClockSpreadSpec;
  562. //
  563. // Thermal Config
  564. //
  565. PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = PchRcVariables->PchCrossThrottling;
  566. PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = TRUE;
  567. if (PchRcVariables->ThermalDeviceEnable == PchThermalDeviceAuto) {
  568. PchPolicy->ThermalConfig.ThermalDeviceEnable = PchThermalDeviceEnabledPci;
  569. } else {
  570. PchPolicy->ThermalConfig.ThermalDeviceEnable = PchRcVariables->ThermalDeviceEnable;
  571. }
  572. PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = TRUE;
  573. PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = TRUE;
  574. PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = TRUE;
  575. //
  576. // DCI (EXI)
  577. //
  578. PchPolicy->DciConfig.DciEn = DCI_DISABLE;
  579. PchPolicy->DciConfig.DciAutoDetect = DCI_DISABLE;
  580. //
  581. // Initialize Serial IRQ Config
  582. //
  583. PchPolicy->SerialIrqConfig.SirqEnable = TRUE;
  584. PchPolicy->SerialIrqConfig.StartFramePulse = PchSfpw4Clk;
  585. if (PchRcVariables->PchSirqMode == 0) {
  586. PchPolicy->SerialIrqConfig.SirqMode = PchQuietMode;
  587. } else {
  588. PchPolicy->SerialIrqConfig.SirqMode = PchContinuousMode;
  589. }
  590. //
  591. // Port 61h emulation
  592. //
  593. PchPolicy->Port61hSmmConfig.Enable = TRUE;
  594. //
  595. // DMI configuration
  596. //
  597. PchPolicy->DmiConfig.DmiLinkDownHangBypass = PchRcVariables->DmiLinkDownHangBypass;
  598. PchPolicy->DmiConfig.DmiStopAndScreamEnable = PchRcVariables->PcieDmiStopAndScreamEnable;
  599. //
  600. // Update Pch Usb Config
  601. //
  602. PlatformGetUsbOcMappings (
  603. (USB_OVERCURRENT_PIN **) &Usb20OverCurrentMappings,
  604. (USB_OVERCURRENT_PIN **) &Usb30OverCurrentMappings,
  605. (USB2_PHY_PARAMETERS **) &Usb20AfeParams
  606. );
  607. UpdatePchUsbConfig (
  608. &PchPolicy->UsbConfig,
  609. SetupVariables,
  610. PchRcVariables,
  611. Usb20OverCurrentMappings,
  612. Usb30OverCurrentMappings,
  613. Usb20AfeParams
  614. );
  615. //
  616. // Install PCIe device override table
  617. //
  618. InstallPcieDeviceTable (mPcieDeviceTable);
  619. //
  620. // Initialize PTSS board specyfic HSIO settings
  621. //
  622. InstallPlatformHsioPtssTable (PchRcVariables, PchPolicy);
  623. PchPolicy->PchTraceHubConfig.PchTraceHubHide = TRUE;
  624. return EFI_SUCCESS;
  625. }
  626. /**
  627. Performs silicon pre-mem policy update.
  628. The meaning of Policy is defined by silicon code.
  629. It could be the raw data, a handle, a PPI, etc.
  630. The input Policy must be returned by SiliconPolicyDonePreMem().
  631. 1) In FSP path, the input Policy should be FspmUpd.
  632. A platform may use this API to update the FSPM UPD policy initialized
  633. by the silicon module or the default UPD data.
  634. The output of FSPM UPD data from this API is the final UPD data.
  635. 2) In non-FSP path, the board may use additional way to get
  636. the silicon policy data field based upon the input Policy.
  637. @param[in, out] Policy Pointer to policy.
  638. @return the updated policy.
  639. **/
  640. VOID *
  641. EFIAPI
  642. SiliconPolicyUpdatePreMem (
  643. IN OUT VOID *Policy
  644. )
  645. {
  646. UpdatePeiPchPolicy (Policy);
  647. return Policy;
  648. }
  649. /**
  650. Performs silicon post-mem policy update.
  651. The meaning of Policy is defined by silicon code.
  652. It could be the raw data, a handle, a PPI, etc.
  653. The input Policy must be returned by SiliconPolicyDonePostMem().
  654. 1) In FSP path, the input Policy should be FspsUpd.
  655. A platform may use this API to update the FSPS UPD policy initialized
  656. by the silicon module or the default UPD data.
  657. The output of FSPS UPD data from this API is the final UPD data.
  658. 2) In non-FSP path, the board may use additional way to get
  659. the silicon policy data field based upon the input Policy.
  660. @param[in, out] Policy Pointer to policy.
  661. @return the updated policy.
  662. **/
  663. VOID *
  664. EFIAPI
  665. SiliconPolicyUpdatePostMem (
  666. IN OUT VOID *Policy
  667. )
  668. {
  669. return Policy;
  670. }