SiliconPolicyUpdateLib.c 33 KB

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  1. /** @file
  2. This file is SampleCode of the library for Intel PCH PEI Policy initialzation.
  3. @copyright
  4. Copyright 2004 - 2021 Intel Corporation. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <PiPei.h>
  8. #include "Guid/SetupVariable.h"
  9. #include <PchSetupVariable.h>
  10. #include <Library/DebugLib.h>
  11. #include <Library/IoLib.h>
  12. #include <Ppi/ReadOnlyVariable2.h>
  13. #include <Library/PeiServicesLib.h>
  14. #include <PchAccess.h>
  15. #include <Ppi/PchPolicy.h>
  16. #include <Register/PchRegsSata.h>
  17. #include <Library/HobLib.h>
  18. #include <Platform.h>
  19. #include <Library/BaseMemoryLib.h>
  20. #include <Library/MemoryAllocationLib.h>
  21. #include <Library/HobLib.h>
  22. #include <Guid/GlobalVariable.h>
  23. #include <Ppi/PchPcieDeviceTable.h>
  24. #include <Guid/SocketVariable.h>
  25. #include <Library/PcdLib.h>
  26. #include <Library/PchInfoLib.h>
  27. #include <Library/UbaUsbOcUpdateLib.h>
  28. #include <Library/UbaHsioPtssTableConfigLib.h>
  29. #include <Ppi/DynamicSiLibraryPpi.h>
  30. //
  31. // Haddock Creek
  32. //
  33. #define DIMM_SMB_SPD_P0C0D0_HC 0xA2
  34. #define DIMM_SMB_SPD_P0C0D1_HC 0xA0
  35. #define DIMM_SMB_SPD_P0C1D0_HC 0xA6
  36. #define DIMM_SMB_SPD_P0C1D1_HC 0xA4
  37. #define DIMM_SMB_SPD_P0C0D2_HC 0xAA
  38. #define DIMM_SMB_SPD_P0C1D2_HC 0xA8
  39. //
  40. // Sawtooth Peak
  41. // Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
  42. //
  43. #define DIMM_SMB_SPD_P0C0D0_STP 0xA2
  44. #define DIMM_SMB_SPD_P0C0D1_STP 0xA0
  45. #define DIMM_SMB_SPD_P0C1D0_STP 0xA2
  46. #define DIMM_SMB_SPD_P0C1D1_STP 0xA0
  47. //
  48. // Aden Hills
  49. // DDR4 System (1DPC)
  50. //
  51. #define DIMM_SMB_SPD_P0C0D0_AH 0xA0
  52. #define DIMM_SMB_SPD_P0C0D1_AH 0xA4
  53. #define DIMM_SMB_SPD_P0C1D0_AH 0xA2
  54. #define DIMM_SMB_SPD_P0C1D1_AH 0xA6
  55. GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] = {
  56. DIMM_SMB_SPD_P0C0D0_HC,
  57. DIMM_SMB_SPD_P0C0D1_HC,
  58. DIMM_SMB_SPD_P0C1D0_HC,
  59. DIMM_SMB_SPD_P0C1D1_HC
  60. };
  61. GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] = {
  62. DIMM_SMB_SPD_P0C0D0_STP,
  63. DIMM_SMB_SPD_P0C0D1_STP,
  64. DIMM_SMB_SPD_P0C1D0_STP,
  65. DIMM_SMB_SPD_P0C1D1_STP
  66. };
  67. GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] = {
  68. DIMM_SMB_SPD_P0C0D0_AH,
  69. DIMM_SMB_SPD_P0C0D1_AH,
  70. DIMM_SMB_SPD_P0C1D0_AH,
  71. DIMM_SMB_SPD_P0C1D1_AH
  72. };
  73. #define PCI_CLASS_NETWORK 0x02
  74. #define PCI_CLASS_NETWORK_ETHERNET 0x00
  75. #define PCI_CLASS_NETWORK_OTHER 0x80
  76. GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
  77. //
  78. // Intel PRO/Wireless
  79. //
  80. { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  81. { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  82. { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  83. { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  84. //
  85. // Intel WiMAX/WiFi Link
  86. //
  87. { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  88. { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  89. { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  90. { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  91. { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  92. { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  93. { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  94. { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  95. { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  96. { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  97. //
  98. // Intel Crane Peak WLAN NIC
  99. //
  100. { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  101. { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  102. //
  103. // Intel Crane Peak w/BT WLAN NIC
  104. //
  105. { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  106. { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  107. //
  108. // Intel Kelsey Peak WiFi, WiMax
  109. //
  110. { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  111. { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  112. //
  113. // Intel Centrino Wireless-N 105
  114. //
  115. { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  116. { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  117. //
  118. // Intel Centrino Wireless-N 135
  119. //
  120. { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  121. { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  122. //
  123. // Intel Centrino Wireless-N 2200
  124. //
  125. { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  126. { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  127. //
  128. // Intel Centrino Wireless-N 2230
  129. //
  130. { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  131. { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  132. //
  133. // Intel Centrino Wireless-N 6235
  134. //
  135. { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  136. { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  137. //
  138. // Intel CampPeak 2 Wifi
  139. //
  140. { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  141. { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  142. //
  143. // Intel WilkinsPeak 1 Wifi
  144. //
  145. { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  146. { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  147. { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  148. { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  149. //
  150. // Intel Wilkins Peak 2 Wifi
  151. //
  152. { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  153. { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  154. { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
  155. { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
  156. //
  157. // Intel Wilkins Peak PF Wifi
  158. //
  159. { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
  160. //
  161. // End of Table
  162. //
  163. { 0 }
  164. };
  165. STATIC
  166. EFI_STATUS
  167. InstallPcieDeviceTable (
  168. IN PCH_PCIE_DEVICE_OVERRIDE *DeviceTable
  169. )
  170. {
  171. EFI_PEI_PPI_DESCRIPTOR *DeviceTablePpiDesc;
  172. EFI_STATUS Status;
  173. DeviceTablePpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
  174. ASSERT (DeviceTablePpiDesc != NULL);
  175. if (DeviceTablePpiDesc == NULL) {
  176. return EFI_OUT_OF_RESOURCES;
  177. }
  178. DeviceTablePpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
  179. DeviceTablePpiDesc->Guid = &gPchPcieDeviceTablePpiGuid;
  180. DeviceTablePpiDesc->Ppi = DeviceTable;
  181. Status = PeiServicesInstallPpi (DeviceTablePpiDesc);
  182. ASSERT_EFI_ERROR (Status);
  183. return Status;
  184. }
  185. VOID
  186. UpdatePchUsbConfig (
  187. IN PCH_USB_CONFIG *PchUsbConfig,
  188. IN SYSTEM_CONFIGURATION *SetupVariables,
  189. IN PCH_SETUP *PchRcVariables,
  190. IN VOID *Usb20OverCurrentMappings,
  191. IN VOID *Usb30OverCurrentMappings,
  192. IN VOID *Usb20AfeParams
  193. );
  194. static
  195. VOID
  196. InstallPlatformVerbTables (
  197. IN UINTN CodecType
  198. )
  199. {
  200. }
  201. EFI_STATUS
  202. EFIAPI
  203. UpdatePeiPchPolicy (
  204. IN OUT PCH_POLICY_PPI *PchPolicy
  205. )
  206. /*++
  207. Routine Description:
  208. This function performs PCH PEI Policy initialzation.
  209. Arguments:
  210. PchPolicy The PCH Policy PPI instance
  211. Returns:
  212. EFI_SUCCESS The PPI is installed and initialized.
  213. EFI ERRORS The PPI is not successfully installed.
  214. EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
  215. --*/
  216. {
  217. UINT8 Index;
  218. UINTN LpcBaseAddress;
  219. UINT8 MaxSataPorts;
  220. UINT8 BmcRootPort;
  221. UINT8 *SmBusReservedTable;
  222. UINT8 SmBusReservedNum;
  223. USB_OVERCURRENT_PIN *Usb20OverCurrentMappings = NULL;
  224. USB_OVERCURRENT_PIN *Usb30OverCurrentMappings = NULL;
  225. USB2_PHY_PARAMETERS *Usb20AfeParams = NULL;
  226. UINT8 VTdSupport;
  227. SYSTEM_CONFIGURATION *SetupVariables;
  228. PCH_SETUP *PchRcVariables;
  229. EFI_STATUS Status = EFI_SUCCESS;
  230. DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
  231. DEBUG((DEBUG_INFO, "platform common UpdatePeiPchPolicy entry\n"));
  232. Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, (VOID **) &DynamicSiLibraryPpi);
  233. if (EFI_ERROR (Status)) {
  234. ASSERT_EFI_ERROR (Status);
  235. return Status;
  236. }
  237. SetupVariables = PcdGetPtr(PcdSetup);
  238. PchRcVariables = PcdGetPtr(PcdPchSetup);
  239. LpcBaseAddress = DynamicSiLibraryPpi->MmPciBase (
  240. DEFAULT_PCI_BUS_NUMBER_PCH,
  241. PCI_DEVICE_NUMBER_PCH_LPC,
  242. PCI_FUNCTION_NUMBER_PCH_LPC
  243. );
  244. PchPolicy->Port80Route = PchRcVariables->IchPort80Route;
  245. //
  246. // DeviceEnables
  247. //
  248. if (DynamicSiLibraryPpi->PchIsGbeAvailable ()) {
  249. PchPolicy->LanConfig.Enable = TRUE;
  250. PchPolicy->LanConfig.K1OffEnable = PchRcVariables->PchLanK1Off;
  251. } else {
  252. PchPolicy->LanConfig.Enable = FALSE;
  253. }
  254. PchPolicy->SataConfig.Enable = PchRcVariables->PchSata;
  255. PchPolicy->sSataConfig.Enable = PchRcVariables->PchsSata;
  256. PchPolicy->SmbusConfig.Enable = TRUE;
  257. //
  258. // CLOCKRUN in LPC has to be disabled:
  259. // - if a device is connected to LPC0
  260. // - for LBG A0 stepping
  261. //
  262. PchPolicy->PmConfig.PciClockRun = FALSE;
  263. PchPolicy->PchConfig.Crid = PchRcVariables->PchCrid;
  264. PchPolicy->PchConfig.Serm = PchRcVariables->PchSerm;
  265. //
  266. // SMBUS reserved addresses
  267. //
  268. SmBusReservedTable = NULL;
  269. SmBusReservedNum = 0;
  270. PchPolicy->SmbusConfig.SmbusIoBase = PCH_SMBUS_BASE_ADDRESS;
  271. SmBusReservedTable = mSmbusSTPRsvdAddresses;
  272. SmBusReservedNum = sizeof (mSmbusSTPRsvdAddresses);
  273. if (SmBusReservedTable != NULL) {
  274. PchPolicy->SmbusConfig.NumRsvdSmbusAddresses = SmBusReservedNum;
  275. CopyMem (
  276. PchPolicy->SmbusConfig.RsvdSmbusAddressTable,
  277. SmBusReservedTable,
  278. SmBusReservedNum
  279. );
  280. }
  281. //
  282. // SATA Config
  283. //
  284. PchPolicy->SataConfig.SataMode = PchRcVariables->SataInterfaceMode;
  285. MaxSataPorts = DynamicSiLibraryPpi->GetPchMaxSataPortNum ();
  286. for (Index = 0; Index < MaxSataPorts; Index++) {
  287. if (PchRcVariables->SataTestMode == TRUE)
  288. {
  289. PchPolicy->SataConfig.PortSettings[Index].Enable = TRUE;
  290. } else {
  291. PchPolicy->SataConfig.PortSettings[Index].Enable = PchRcVariables->SataPort[Index];
  292. }
  293. PchPolicy->SataConfig.PortSettings[Index].HotPlug = PchRcVariables->SataHotPlug[Index];
  294. PchPolicy->SataConfig.PortSettings[Index].SpinUp = PchRcVariables->SataSpinUp[Index];
  295. PchPolicy->SataConfig.PortSettings[Index].External = PchRcVariables->SataExternal[Index];
  296. PchPolicy->SataConfig.PortSettings[Index].InterlockSw = PchRcVariables->SataMechanicalSw[Index];
  297. PchPolicy->SataConfig.PortSettings[Index].DevSlp = PchRcVariables->PxDevSlp[Index];
  298. PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->EnableDitoConfig[Index];
  299. PchPolicy->SataConfig.PortSettings[Index].DmVal = PchRcVariables->DmVal[Index];
  300. PchPolicy->SataConfig.PortSettings[Index].DitoVal = PchRcVariables->DitoVal[Index];
  301. PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->SataType[Index];
  302. }
  303. if (PchPolicy->SataConfig.SataMode == PchSataModeRaid) {
  304. PchPolicy->SataConfig.Rst.RaidAlternateId = PchRcVariables->SataAlternateId;
  305. PchPolicy->SataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->SataRaidLoadEfiDriver[0];
  306. }
  307. PchPolicy->SataConfig.Rst.Raid0 = PchRcVariables->SataRaidR0;
  308. PchPolicy->SataConfig.Rst.Raid1 = PchRcVariables->SataRaidR1;
  309. PchPolicy->SataConfig.Rst.Raid10 = PchRcVariables->SataRaidR10;
  310. PchPolicy->SataConfig.Rst.Raid5 = PchRcVariables->SataRaidR5;
  311. PchPolicy->SataConfig.Rst.Irrt = PchRcVariables->SataRaidIrrt;
  312. PchPolicy->SataConfig.Rst.OromUiBanner = PchRcVariables->SataRaidOub;
  313. PchPolicy->SataConfig.Rst.HddUnlock = PchRcVariables->SataHddlk;
  314. PchPolicy->SataConfig.Rst.LedLocate = PchRcVariables->SataLedl;
  315. PchPolicy->SataConfig.Rst.IrrtOnly = PchRcVariables->SataRaidIooe;
  316. PchPolicy->SataConfig.Rst.SmartStorage = PchRcVariables->SataRaidSrt;
  317. PchPolicy->SataConfig.Rst.OromUiDelay = PchRcVariables->SataRaidOromDelay;
  318. PchPolicy->SataConfig.EnclosureSupport = TRUE;
  319. PchPolicy->SataConfig.SalpSupport = PchRcVariables->SataSalp;
  320. PchPolicy->SataConfig.TestMode = PchRcVariables->SataTestMode;
  321. for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
  322. if ((PchRcVariables->PchSata == TRUE) && (PchRcVariables->SataInterfaceMode == PchSataModeRaid)) {
  323. PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = PchRcVariables->RstPcieStorageRemap[Index];
  324. PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = PchRcVariables->RstPcieStorageRemapPort[Index];
  325. } else {
  326. PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = FALSE;
  327. }
  328. }
  329. //
  330. // sSATA Config
  331. //
  332. PchPolicy->sSataConfig.SataMode = PchRcVariables->sSataInterfaceMode;
  333. MaxSataPorts = DynamicSiLibraryPpi->GetPchMaxsSataPortNum ();
  334. for (Index = 0; Index < MaxSataPorts; Index++) {
  335. if (PchRcVariables->sSataTestMode == TRUE)
  336. {
  337. PchPolicy->sSataConfig.PortSettings[Index].Enable = TRUE;
  338. } else {
  339. PchPolicy->sSataConfig.PortSettings[Index].Enable = PchRcVariables->sSataPort[Index];
  340. }
  341. PchPolicy->sSataConfig.PortSettings[Index].HotPlug = PchRcVariables->sSataHotPlug[Index];
  342. PchPolicy->sSataConfig.PortSettings[Index].SpinUp = PchRcVariables->sSataSpinUp[Index];
  343. PchPolicy->sSataConfig.PortSettings[Index].External = PchRcVariables->sSataExternal[Index];
  344. PchPolicy->sSataConfig.PortSettings[Index].DevSlp = PchRcVariables->sPxDevSlp[Index];
  345. PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->sEnableDitoConfig[Index];
  346. PchPolicy->sSataConfig.PortSettings[Index].DmVal = PchRcVariables->sDmVal[Index];
  347. PchPolicy->sSataConfig.PortSettings[Index].DitoVal = PchRcVariables->sDitoVal[Index];
  348. PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->sSataType[Index];
  349. }
  350. if (PchPolicy->sSataConfig.SataMode == PchSataModeRaid) {
  351. PchPolicy->sSataConfig.Rst.RaidAlternateId = PchRcVariables->sSataAlternateId;
  352. PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->SataRaidLoadEfiDriver[1];
  353. }
  354. PchPolicy->sSataConfig.Rst.Raid0 = PchRcVariables->sSataRaidR0;
  355. PchPolicy->sSataConfig.Rst.Raid1 = PchRcVariables->sSataRaidR1;
  356. PchPolicy->sSataConfig.Rst.Raid10 = PchRcVariables->sSataRaidR10;
  357. PchPolicy->sSataConfig.Rst.Raid5 = PchRcVariables->sSataRaidR5;
  358. PchPolicy->sSataConfig.Rst.Irrt = PchRcVariables->sSataRaidIrrt;
  359. PchPolicy->sSataConfig.Rst.OromUiBanner = PchRcVariables->sSataRaidOub;
  360. PchPolicy->sSataConfig.Rst.HddUnlock = PchRcVariables->sSataHddlk;
  361. PchPolicy->sSataConfig.Rst.LedLocate = PchRcVariables->sSataLedl;
  362. PchPolicy->sSataConfig.Rst.IrrtOnly = PchRcVariables->sSataRaidIooe;
  363. PchPolicy->sSataConfig.Rst.SmartStorage = PchRcVariables->sSataRaidSrt;
  364. PchPolicy->sSataConfig.Rst.OromUiDelay = PchRcVariables->sSataRaidOromDelay;
  365. PchPolicy->sSataConfig.EnclosureSupport = TRUE;
  366. PchPolicy->sSataConfig.SalpSupport = PchRcVariables->sSataSalp;
  367. PchPolicy->sSataConfig.TestMode = PchRcVariables->sSataTestMode;
  368. //
  369. // Initiate DMI Configuration
  370. //
  371. if (SetupVariables->PcieDmiAspm != PLATFORM_POR) {
  372. if (SetupVariables->PcieDmiAspm != 0xFF) {
  373. PchPolicy->DmiConfig.DmiAspm = TRUE;
  374. } else {
  375. PchPolicy->DmiConfig.DmiAspm = FALSE;
  376. }
  377. }
  378. DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =%x\n", PchPolicy->DmiConfig.DmiAspm));
  379. //
  380. // PCI express config
  381. //
  382. PchPolicy->PcieConfig.DisableRootPortClockGating = SetupVariables->PcieClockGatingDisabled;
  383. PchPolicy->PcieConfig.EnablePort8xhDecode = PchRcVariables->PcieRootPort8xhDecode;
  384. PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex = PchRcVariables->Pcie8xhDecodePortIndex;
  385. PchPolicy->PcieConfig.EnablePeerMemoryWrite = PchRcVariables->PcieRootPortPeerMemoryWriteEnable;
  386. PchPolicy->PcieConfig.ComplianceTestMode = PchRcVariables->PcieComplianceTestMode;
  387. ///
  388. /// Temporary WA: Force Link speed on BMC board to GEN1
  389. /// TODO: remove this WA together with Purley platforms support
  390. ///
  391. BmcRootPort = PcdGet8 (PcdOemSkuBmcPciePortNumber);
  392. if ((BmcRootPort != 0xFF) && (BmcRootPort < ARRAY_SIZE(PchRcVariables->PcieRootPortSpeed))) {
  393. DEBUG ((DEBUG_INFO, "WA Force Link Speed to GEN1: PciePort: %d", BmcRootPort));
  394. PchRcVariables->PcieRootPortSpeed[BmcRootPort] = 1;
  395. }
  396. for (Index = 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); Index++) {
  397. PchPolicy->PcieConfig.RootPort[Index].Enable = PchRcVariables->PcieRootPortEn[Index];
  398. PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = (UINT8) Index;
  399. if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) {
  400. // Disabled a.k.a. Per individual port
  401. PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PchPcieGlobalAspm;
  402. } else {
  403. PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PcieRootPortAspm[Index];
  404. }
  405. PchPolicy->PcieConfig.RootPort[Index].L1Substates = PchRcVariables->PcieRootPortL1SubStates[Index];
  406. PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = PchRcVariables->PcieRootPortACS[Index];
  407. PchPolicy->PcieConfig.RootPort[Index].PmSci = PchRcVariables->PcieRootPortPMCE[Index];
  408. PchPolicy->PcieConfig.RootPort[Index].HotPlug = PchRcVariables->PcieRootPortHPE[Index];
  409. PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = PchRcVariables->PcieRootPortAER[Index];
  410. PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = PchRcVariables->PcieRootPortURE[Index];
  411. PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = PchRcVariables->PcieRootPortFEE[Index];
  412. PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = PchRcVariables->PcieRootPortNFE[Index];
  413. PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = PchRcVariables->PcieRootPortCEE[Index];
  414. PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = PchRcVariables->PcieRootPortSFE[Index];
  415. PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = PchRcVariables->PcieRootPortSNE[Index];
  416. PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = PchRcVariables->PcieRootPortSCE[Index];
  417. PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = PchRcVariables->PcieRootPortTHS[Index];
  418. PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = PchRcVariables->PcieRootPortCompletionTimeout[Index];
  419. PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = PchRcVariables->PcieRootPortSpeed[Index];
  420. PchPolicy->PcieConfig.RootPort[Index].MaxPayload = PchRcVariables->PcieRootPortMaxPayLoadSize[Index];
  421. PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = PchRcVariables->PcieRootPortEqPh3Method[Index];
  422. PchPolicy->PcieConfig.RootPort[Index].SlotImplemented = TRUE;
  423. }
  424. PchPolicy->PcieConfig.RootPort[BmcRootPort].SlotImplemented = FALSE;
  425. for (Index = 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); ++Index) {
  426. PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm = PchRcVariables->PcieLaneCm[Index];
  427. PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp = PchRcVariables->PcieLaneCp[Index];
  428. }
  429. if (PchRcVariables->PcieSwEqOverride) {
  430. for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) {
  431. PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm = PchRcVariables->PcieSwEqCoeffCm[Index];
  432. PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp = PchRcVariables->PcieSwEqCoeffCp[Index];
  433. }
  434. }
  435. PchPolicy->PcieConfig.MaxReadRequestSize = PchRcVariables->PcieRootPortMaxReadRequestSize;
  436. ///
  437. /// Update Competion Timeout settings for Upling ports for Server PCH
  438. ///
  439. PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = PchRcVariables->PchPcieUX16CompletionTimeout;
  440. PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = PchRcVariables->PchPcieUX8CompletionTimeout;
  441. ///
  442. /// Update Max Payload Size settings for Upling ports for Server PCH
  443. ///
  444. PchPolicy->PcieConfig.PchPcieUX16MaxPayload = PchRcVariables->PchPcieUX16MaxPayloadSize;
  445. PchPolicy->PcieConfig.PchPcieUX8MaxPayload = PchRcVariables->PchPcieUX8MaxPayloadSize;
  446. CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfig) + OFFSET_OF(SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport));
  447. PchPolicy->PcieConfig.VTdSupport = VTdSupport;
  448. if (DynamicSiLibraryPpi->X2ApicIdDetect (NULL)) {
  449. PchPolicy->PcieConfig.VTdSupport = TRUE;
  450. }
  451. ///
  452. /// Assign ClkReq signal to root port. (Base 0)
  453. /// For LP, Set 0 - 5
  454. /// For H, Set 0 - 15
  455. /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port. (TODO for Purley)
  456. ///
  457. //
  458. // HdAudioConfig
  459. //
  460. PchPolicy->HdAudioConfig.Enable = PchRcVariables->PchHdAudio;
  461. PchPolicy->HdAudioConfig.DspEnable = FALSE;
  462. PchPolicy->HdAudioConfig.Pme = PchRcVariables->PchHdAudioPme;
  463. PchPolicy->HdAudioConfig.IoBufferOwnership = PchRcVariables->PchHdAudioIoBufferOwnership;
  464. PchPolicy->HdAudioConfig.IoBufferVoltage = PchRcVariables->PchHdAudioIoBufferVoltage;
  465. PchPolicy->HdAudioConfig.ResetWaitTimer = 300;
  466. PchPolicy->HdAudioConfig.IDispCodecDisconnect = TRUE; //iDisp is permanently disabled
  467. for(Index = 0; Index < HDAUDIO_FEATURES; Index++) {
  468. PchPolicy->HdAudioConfig.DspFeatureMask |= (UINT32)(PchRcVariables->PchHdAudioFeature[Index] ? (1 << Index) : 0);
  469. }
  470. for(Index = 0; Index < HDAUDIO_PP_MODULES; Index++) {
  471. PchPolicy->HdAudioConfig.DspPpModuleMask |= (UINT32)(PchRcVariables->PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0);
  472. }
  473. if (PchPolicy->HdAudioConfig.Enable) {
  474. InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect);
  475. }
  476. PchPolicy->HdAudioConfig.VcType = PchRcVariables->DfxHdaVcType;
  477. //
  478. // LockDown
  479. //
  480. PchPolicy->LockDownConfig.RtcLock = PchRcVariables->PchRtcLock;
  481. PchPolicy->LockDownConfig.SpiEiss = TRUE;
  482. PchPolicy->LockDownConfig.GlobalSmi = TRUE;
  483. PchPolicy->LockDownConfig.BiosInterface = TRUE;
  484. PchPolicy->LockDownConfig.GpioLockDown = PchRcVariables->PchGpioLockDown;
  485. PchPolicy->LockDownConfig.TcoLock = TRUE;
  486. if(PchRcVariables->PchP2sbUnlock) {
  487. PchPolicy->P2sbConfig.SbiUnlock = TRUE;
  488. PchPolicy->P2sbConfig.PsfUnlock = TRUE;
  489. } else {
  490. PchPolicy->P2sbConfig.SbiUnlock = FALSE;
  491. PchPolicy->P2sbConfig.PsfUnlock = FALSE;
  492. }
  493. PchPolicy->P2sbConfig.P2SbReveal = PchRcVariables->PchP2sbDevReveal;
  494. //
  495. // Update SPI policies
  496. //
  497. PchPolicy->SpiConfig.ShowSpiController = TRUE;
  498. PchPolicy->PmConfig.PmcReadDisable = TRUE;
  499. if (PchRcVariables->PchAdrEn != PLATFORM_POR) {
  500. PchPolicy->AdrConfig.PchAdrEn = PchRcVariables->PchAdrEn;
  501. }
  502. PchPolicy->AdrConfig.AdrGpioSel = PchRcVariables->AdrGpioSel;
  503. if (PchRcVariables->AdrHostPartitionReset != PLATFORM_POR) {
  504. PchPolicy->AdrConfig.AdrHostPartitionReset = PchRcVariables->AdrHostPartitionReset;
  505. }
  506. if (PchRcVariables->AdrTimerEn != PLATFORM_POR) {
  507. PchPolicy->AdrConfig.AdrTimerEn = PchRcVariables->AdrTimerEn;
  508. }
  509. if (PchRcVariables->AdrTimerVal != ADR_TMR_SETUP_DEFAULT_POR) {
  510. PchPolicy->AdrConfig.AdrTimerVal = PchRcVariables->AdrTimerVal;
  511. }
  512. if (PchRcVariables->AdrMultiplierVal != ADR_MULT_SETUP_DEFAULT_POR) {
  513. PchPolicy->AdrConfig.AdrMultiplierVal = PchRcVariables->AdrMultiplierVal;
  514. }
  515. //
  516. // Thermal Config
  517. //
  518. if ((PchRcVariables->MemoryThermalManagement != FALSE) &&
  519. ((PchRcVariables->ExttsViaTsOnBoard != FALSE) || (PchRcVariables->ExttsViaTsOnDimm != FALSE)))
  520. {
  521. PchPolicy->ThermalConfig.MemoryThrottling.Enable = TRUE;
  522. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE;
  523. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE;
  524. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE;
  525. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE;
  526. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PinSelection = 1;
  527. PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PinSelection = 0;
  528. } else {
  529. PchPolicy->ThermalConfig.MemoryThrottling.Enable = FALSE;
  530. }
  531. //
  532. // IOAPIC Config
  533. //
  534. PchPolicy->IoApicConfig.IoApicEntry24_119 = PchRcVariables->PchIoApic24119Entries;
  535. PchPolicy->IoApicConfig.BdfValid = 1;
  536. PchPolicy->IoApicConfig.BusNumber = PCI_BUS_NUMBER_PCH_IOAPIC;
  537. PchPolicy->IoApicConfig.DeviceNumber = PCI_DEVICE_NUMBER_PCH_IOAPIC;
  538. PchPolicy->IoApicConfig.FunctionNumber = PCI_FUNCTION_NUMBER_PCH_IOAPIC;
  539. PchPolicy->HpetConfig.BdfValid = 1;
  540. PchPolicy->HpetConfig.BusNumber = PCI_BUS_NUMBER_PCH_HPET;
  541. PchPolicy->HpetConfig.DeviceNumber = PCI_DEVICE_NUMBER_PCH_HPET;
  542. PchPolicy->HpetConfig.FunctionNumber = PCI_FUNCTION_NUMBER_PCH_HPET0;
  543. PchPolicy->PchInterruptConfig.ShutdownPolicySelect = PchRcVariables->ShutdownPolicySelect;
  544. //
  545. // Misc PM Config
  546. //
  547. PchPolicy->PmConfig.PchDeepSxPol = PchRcVariables->DeepSxMode;
  548. PchPolicy->PmConfig.WakeConfig.WolEnableOverride = PchRcVariables->PchWakeOnLan;
  549. PchPolicy->PmConfig.WakeConfig.WoWlanEnable = PchRcVariables->PchWakeOnWlan;
  550. PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable = PchRcVariables->PchWakeOnWlanDeepSx;
  551. PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx = PchRcVariables->Gp27WakeFromDeepSx;
  552. PchPolicy->PmConfig.SlpLanLowDc = PchRcVariables->PchSlpLanLowDc;
  553. PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts = TRUE;
  554. PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts = TRUE;
  555. PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts = TRUE;
  556. PchPolicy->PmConfig.PciePllSsc = PchRcVariables->PciePllSsc;
  557. PchPolicy->PmConfig.Dwr_BmcRootPort = PchRcVariables->Dwr_BmcRootPort;
  558. PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL = PchRcVariables->DwrEn_PMCGBL;
  559. PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT = PchRcVariables->DwrEn_MEWDT;
  560. PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT = PchRcVariables->DwrEn_IEWDT;
  561. //
  562. // DefaultSvidSid Config
  563. //
  564. PchPolicy->PchConfig.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
  565. PchPolicy->PchConfig.SubSystemId = V_PCH_DEFAULT_SID;
  566. PchPolicy->PchConfig.EnableClockSpreadSpec = PchRcVariables->EnableClockSpreadSpec;
  567. //
  568. // Thermal Config
  569. //
  570. PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = PchRcVariables->PchCrossThrottling;
  571. PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = TRUE;
  572. if (PchRcVariables->ThermalDeviceEnable == PchThermalDeviceAuto) {
  573. PchPolicy->ThermalConfig.ThermalDeviceEnable = PchThermalDeviceEnabledPci;
  574. } else {
  575. PchPolicy->ThermalConfig.ThermalDeviceEnable = PchRcVariables->ThermalDeviceEnable;
  576. }
  577. PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = TRUE;
  578. PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = TRUE;
  579. PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = TRUE;
  580. ///
  581. ///Set PCHHOT# to 85C.
  582. ///
  583. PchPolicy->ThermalConfig.PchHotLevel = 0x10E;
  584. // DCI (EXI)
  585. //
  586. PchPolicy->DciConfig.DciEn = DCI_DISABLE;
  587. PchPolicy->DciConfig.DciAutoDetect = DCI_DISABLE;
  588. //
  589. // Initialize Serial IRQ Config
  590. //
  591. PchPolicy->SerialIrqConfig.SirqEnable = TRUE;
  592. PchPolicy->SerialIrqConfig.StartFramePulse = PchSfpw4Clk;
  593. if (PchRcVariables->PchSirqMode == 0) {
  594. PchPolicy->SerialIrqConfig.SirqMode = PchQuietMode;
  595. } else {
  596. PchPolicy->SerialIrqConfig.SirqMode = PchContinuousMode;
  597. }
  598. //
  599. // Port 61h emulation
  600. //
  601. PchPolicy->Port61hSmmConfig.Enable = TRUE;
  602. //
  603. // DMI configuration
  604. //
  605. PchPolicy->DmiConfig.DmiLinkDownHangBypass = PchRcVariables->DmiLinkDownHangBypass;
  606. PchPolicy->DmiConfig.DmiStopAndScreamEnable = PchRcVariables->PcieDmiStopAndScreamEnable;
  607. //
  608. // Update Pch Usb Config
  609. //
  610. PlatformGetUsbOcMappings (
  611. (USB_OVERCURRENT_PIN **) &Usb20OverCurrentMappings,
  612. (USB_OVERCURRENT_PIN **) &Usb30OverCurrentMappings,
  613. (USB2_PHY_PARAMETERS **) &Usb20AfeParams
  614. );
  615. UpdatePchUsbConfig (
  616. &PchPolicy->UsbConfig,
  617. SetupVariables,
  618. PchRcVariables,
  619. Usb20OverCurrentMappings,
  620. Usb30OverCurrentMappings,
  621. Usb20AfeParams
  622. );
  623. //
  624. // Install PCIe device override table
  625. //
  626. InstallPcieDeviceTable (mPcieDeviceTable);
  627. //
  628. // Initialize PTSS board specyfic HSIO settings
  629. //
  630. InstallPlatformHsioPtssTable (PchRcVariables, PchPolicy);
  631. PchPolicy->PchTraceHubConfig.PchTraceHubHide = TRUE;
  632. return EFI_SUCCESS;
  633. }
  634. /**
  635. Performs silicon pre-mem policy update.
  636. The meaning of Policy is defined by silicon code.
  637. It could be the raw data, a handle, a PPI, etc.
  638. The input Policy must be returned by SiliconPolicyDonePreMem().
  639. 1) In FSP path, the input Policy should be FspmUpd.
  640. A platform may use this API to update the FSPM UPD policy initialized
  641. by the silicon module or the default UPD data.
  642. The output of FSPM UPD data from this API is the final UPD data.
  643. 2) In non-FSP path, the board may use additional way to get
  644. the silicon policy data field based upon the input Policy.
  645. @param[in, out] Policy Pointer to policy.
  646. @return the updated policy.
  647. **/
  648. VOID *
  649. EFIAPI
  650. SiliconPolicyUpdatePreMem (
  651. IN OUT VOID *Policy
  652. )
  653. {
  654. UpdatePeiPchPolicy (Policy);
  655. return Policy;
  656. }
  657. /**
  658. Performs silicon post-mem policy update.
  659. The meaning of Policy is defined by silicon code.
  660. It could be the raw data, a handle, a PPI, etc.
  661. The input Policy must be returned by SiliconPolicyDonePostMem().
  662. 1) In FSP path, the input Policy should be FspsUpd.
  663. A platform may use this API to update the FSPS UPD policy initialized
  664. by the silicon module or the default UPD data.
  665. The output of FSPS UPD data from this API is the final UPD data.
  666. 2) In non-FSP path, the board may use additional way to get
  667. the silicon policy data field based upon the input Policy.
  668. @param[in, out] Policy Pointer to policy.
  669. @return the updated policy.
  670. **/
  671. VOID *
  672. EFIAPI
  673. SiliconPolicyUpdatePostMem (
  674. IN OUT VOID *Policy
  675. )
  676. {
  677. return Policy;
  678. }