Fadt.h 7.3 KB

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  1. /** @file
  2. This file describes the contents of the ACPI Fixed ACPI Description Table
  3. FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
  4. All changes to the FADT contents should be done in this file.
  5. @copyright
  6. Copyright 1996 - 2020 Intel Corporation. <BR>
  7. SPDX-License-Identifier: BSD-2-Clause-Patent
  8. **/
  9. #ifndef _FADT_H_
  10. #define _FADT_H_
  11. //
  12. // Statements that include other files
  13. //
  14. #include <IndustryStandard/Acpi.h>
  15. #include "Platform.h"
  16. #include <Library/PcdLib.h>
  17. //
  18. // FADT Definitions
  19. //
  20. #define EFI_ACPI_OEM_FADT_REVISION 0x00000000
  21. //
  22. // For ACPI 1.0 supprt
  23. // Harwich sets this to #define EFI_ACPI_INT_MODEL 0x01
  24. //
  25. /*
  26. INT_MODEL Field
  27. The FADT defines the fixed ACPI information that is needed by the operating system as
  28. defined in section 5.2.5 of the ACPI 1.0 specification. Currently, this table provides a field
  29. for INT_MODEL, which was intended to be used to report the interrupt mode of the machine.
  30. This field is ignored by the Microsoft?Windows?2000 and later operating system because the
  31. Microsoft Windows 98 operating system only supports programmable interrupt controller (PIC) mode.
  32. This forces system manufacturers (OEMs) who want to support Windows 98 to enter a "0" in the INT_MODEL field.
  33. This would then preclude using multiple processors on Windows 2000 and later versions.
  34. Because the INT_MODEL field in the FADT cannot be dynamically updated while the machine is running,
  35. it cannot be used to report the interrupt mode, and therefore it is ignored by Windows 98,
  36. and Windows 2000 and later versions.
  37. http://www.microsoft.com/whdc/system/CEC/ACPI-MP.mspx
  38. For Watson Creek we set this to 0 and then dynamically update this to 1 in the DSDT tables _PIC method and GPIC field.
  39. */
  40. #define EFI_ACPI_INT_MODEL 0x0
  41. #define EFI_ACPI_PREFERRED_PM_PROFILE 0x04
  42. #define EFI_ACPI_SCI_INT 0x0009
  43. #define EFI_ACPI_SMI_CMD 0x0
  44. #define EFI_ACPI_ACPI_ENABLE 0x00
  45. #define EFI_ACPI_ACPI_DISABLE 0x00
  46. #define EFI_ACPI_S4_BIOS_REQ 0x00
  47. #define EFI_ACPI_CST_CNT 0x00
  48. #define EFI_ACPI_PSTATE_CNT 0x00
  49. #define EFI_ACPI_GPE1_BASE (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 2)
  50. #define EFI_ACPI_P_LVL2_LAT 0x0065
  51. #define EFI_ACPI_P_LVL3_LAT 0x03E9
  52. //
  53. // #define EFI_ACPI_FLUSH_SIZE 0x0400
  54. //
  55. #define EFI_ACPI_FLUSH_SIZE 0x0000
  56. //
  57. // #define EFI_ACPI_FLUSH_STRIDE 0x0010
  58. //
  59. #define EFI_ACPI_FLUSH_STRIDE 0x0000
  60. #define EFI_ACPI_DUTY_OFFSET 0x01
  61. //
  62. // #define EFI_ACPI_DUTY_OFFSET 0x00
  63. //
  64. #define EFI_ACPI_DUTY_WIDTH 0x00
  65. #define EFI_ACPI_DAY_ALRM 0x0D
  66. #define EFI_ACPI_MON_ALRM 0x00
  67. #define EFI_ACPI_CENTURY 0x32
  68. //
  69. // IA-PC Boot Architecture Flags, see ACPI 2.0 table specification and Acpi6_2.h
  70. // No legacy KBC and legcay devices other reported in ASL code
  71. //
  72. // #define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_2_LEGACY_DEVICES | EFI_ACPI_6_2_8042)
  73. //
  74. //#define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042
  75. #define EFI_ACPI_OS_ASPM_DISABLE (1 << 4)
  76. #define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042 | EFI_ACPI_OS_ASPM_DISABLE
  77. //
  78. // Fixed Feature Flags, see ACPI 6.2 table specification and Acpi6_2.h
  79. //
  80. #define EFI_ACPI_FIXED_FEATURE_FLAGS (EFI_ACPI_6_2_RESET_REG_SUP | \
  81. EFI_ACPI_6_2_RTC_S4 | \
  82. EFI_ACPI_6_2_SLP_BUTTON | \
  83. EFI_ACPI_6_2_WBINVD | \
  84. EFI_ACPI_6_2_PROC_C1 \
  85. )
  86. //
  87. // PM1A Event Register Block Generic Address Information
  88. //
  89. #define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  90. #define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
  91. #define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
  92. #define EFI_ACPI_PM1A_EVT_BLK_ADDRESS (FixedPcdGet32 (PcdEfiAcpiPm1aEvtBlkAddress))
  93. //
  94. // PM1B Event Register Block Generic Address Information
  95. //
  96. #define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  97. #define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
  98. #define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
  99. #define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x00000000
  100. //
  101. // PM1A Control Register Block Generic Address Information
  102. //
  103. #define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  104. #define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
  105. #define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
  106. #define EFI_ACPI_PM1A_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
  107. //
  108. // PM1B Control Register Block Generic Address Information
  109. //
  110. #define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  111. #define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
  112. #define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
  113. #define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x00
  114. //
  115. // PM2 Control Register Block Generic Address Information
  116. //
  117. #define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  118. #define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
  119. #define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
  120. #define EFI_ACPI_PM2_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50)
  121. //
  122. // Power Management Timer Control Register Block Generic Address
  123. // Information
  124. //
  125. #define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  126. #define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
  127. #define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
  128. #define EFI_ACPI_PM_TMR_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
  129. //
  130. // General Purpose Event 0 Register Block Generic Address
  131. // Information
  132. //
  133. #define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  134. #define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0 // size of R_PCH_ACPI_GPE0_STS_127_96 + R_PCH_ACPI_GPE0_EN_127_96
  135. #define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
  136. #define EFI_ACPI_GPE0_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x80)
  137. //
  138. // General Purpose Event 1 Register Block Generic Address
  139. // Information
  140. //
  141. #define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  142. #define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x0
  143. #define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x0
  144. #define EFI_ACPI_GPE1_BLK_ADDRESS 0x0
  145. //
  146. // Reset Register Generic Address Information
  147. //
  148. #define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
  149. #define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
  150. #define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
  151. #define EFI_ACPI_RESET_REG_ADDRESS 0x00000CF9
  152. #define EFI_ACPI_RESET_VALUE 0x06
  153. //
  154. // Number of bytes decoded by PM1 event blocks (a and b)
  155. //
  156. #define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
  157. //
  158. // Number of bytes decoded by PM1 control blocks (a and b)
  159. //
  160. #define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
  161. //
  162. // Number of bytes decoded by PM2 control block
  163. //
  164. #define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)
  165. //
  166. // Number of bytes decoded by PM timer block
  167. //
  168. #define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
  169. //
  170. // Number of bytes decoded by GPE0 block
  171. //
  172. #define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)
  173. //
  174. // Number of bytes decoded by GPE1 block
  175. //
  176. #define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)
  177. #endif