PciHostBridgeSupport.c 3.7 KB

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  1. /** @file
  2. Do platform initialization for PCI bridge.
  3. @copyright
  4. Copyright 1999 - 2021 Intel Corporation. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include "PciHostBridge.h"
  8. //
  9. // The default latency for controllers
  10. //
  11. #define DEFAULT_PCI_LATENCY 0x20
  12. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
  13. /**
  14. This function is called for all the PCI controllers that the PCI
  15. bus driver finds. Can be used to Preprogram the controller.
  16. @param This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
  17. @param RootBridgeHandle -- The PCI Root Bridge handle
  18. @param PciBusAddress -- Address of the controller on the PCI bus
  19. @param Phase -- The Phase during resource allocation
  20. @retval EFI_SUCCESS
  21. **/
  22. EFI_STATUS
  23. ChipsetPreprocessController (
  24. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  25. IN EFI_HANDLE RootBridgeHandle,
  26. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
  27. IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
  28. )
  29. {
  30. EFI_STATUS Status;
  31. UINT8 Latency;
  32. UINT8 CacheLineSize;
  33. if (mPciRootBridgeIo == NULL) {
  34. //
  35. // Get root bridge in the system.
  36. //
  37. Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo);
  38. ASSERT_EFI_ERROR (Status);
  39. }
  40. if (Phase == EfiPciBeforeResourceCollection) {
  41. //
  42. // Program the latency register, CLS register
  43. //
  44. PciAddress.Register = PCI_LATENCY_TIMER_OFFSET;
  45. mPciRootBridgeIo->Pci.Read (
  46. mPciRootBridgeIo,
  47. EfiPciWidthUint8,
  48. *((UINT64 *) &PciAddress),
  49. 1,
  50. &Latency
  51. );
  52. //
  53. // PCI-x cards come up with a default latency of 0x40. Don't touch them.
  54. //
  55. if (Latency == 0) {
  56. Latency = DEFAULT_PCI_LATENCY;
  57. mPciRootBridgeIo->Pci.Write (
  58. mPciRootBridgeIo,
  59. EfiPciWidthUint8,
  60. *((UINT64 *) &PciAddress),
  61. 1,
  62. &Latency
  63. );
  64. }
  65. //
  66. // Program Cache Line Size as 64bytes
  67. // 16 of DWORDs = 64bytes (0x10)
  68. //
  69. PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;
  70. CacheLineSize = 0x10;
  71. mPciRootBridgeIo->Pci.Write (
  72. mPciRootBridgeIo,
  73. EfiPciWidthUint8,
  74. *((UINT64 *) &PciAddress),
  75. 1,
  76. &CacheLineSize
  77. );
  78. }
  79. return EFI_SUCCESS;
  80. }
  81. /**
  82. Returns the Allocation attributes for the BNB Root Bridge.
  83. @param RootBridgeIndex - The root bridge number. 0 based.
  84. @retval EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE
  85. **/
  86. UINT64
  87. GetAllocAttributes (
  88. IN UINTN RootBridgeIndex
  89. )
  90. {
  91. //
  92. // Cannot have more than one Root bridge
  93. //
  94. //ASSERT (RootBridgeIndex == 0);
  95. //
  96. // PCI Root Bridge does not support separate windows for Non-prefetchable
  97. // and Prefetchable memory. A PCI bus driver needs to include requests for
  98. // Prefetchable memory in the Non-prefetchable memory pool.
  99. // Further TNB does not support 64 bit memory apertures for PCI. BNB
  100. // can only have system memory above 4 GB,
  101. //
  102. return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
  103. }