IchRegTable.c 3.7 KB

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  1. /** @file
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. IchRegTable.c
  6. Abstract:
  7. Register initialization table for Ich.
  8. --*/
  9. #include <Library/EfiRegTableLib.h>
  10. #include "PlatformDxe.h"
  11. extern EFI_PLATFORM_INFO_HOB mPlatformInfo;
  12. #define R_EFI_PCI_SVID 0x2C
  13. EFI_REG_TABLE mSubsystemIdRegs [] = {
  14. //
  15. // Program SVID and SID for PCI devices.
  16. // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance
  17. //
  18. PCI_WRITE (
  19. MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
  20. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  21. ),
  22. PCI_WRITE (
  23. IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
  24. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  25. ),
  26. PCI_WRITE(
  27. DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,
  28. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  29. ),
  30. PCI_WRITE (
  31. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,
  32. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  33. ),
  34. PCI_WRITE (
  35. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,
  36. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  37. ),
  38. PCI_WRITE (
  39. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,
  40. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  41. ),
  42. PCI_WRITE (
  43. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,
  44. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  45. ),
  46. PCI_WRITE (
  47. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,
  48. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  49. ),
  50. PCI_WRITE (
  51. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,
  52. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  53. ),
  54. PCI_WRITE (
  55. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,
  56. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  57. ),
  58. PCI_WRITE (
  59. DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,
  60. V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
  61. ),
  62. TERMINATE_TABLE
  63. };
  64. /**
  65. Updates the mSubsystemIdRegs table, and processes it. This should program
  66. the Subsystem Vendor and Device IDs.
  67. @retval Returns VOID
  68. **/
  69. VOID
  70. InitializeSubsystemIds (
  71. )
  72. {
  73. EFI_REG_TABLE *RegTablePtr;
  74. UINT32 SubsystemVidDid;
  75. SubsystemVidDid = mPlatformInfo.SsidSvid;
  76. RegTablePtr = mSubsystemIdRegs;
  77. //
  78. // While we are not at the end of the table
  79. //
  80. while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {
  81. //
  82. // If the data to write is the original SSID
  83. //
  84. if (RegTablePtr->PciWrite.Data ==
  85. ((V_PCH_DEFAULT_SID << 16) |
  86. V_PCH_INTEL_VENDOR_ID)
  87. ) {
  88. //
  89. // Then overwrite it to use the alternate SSID
  90. //
  91. RegTablePtr->PciWrite.Data = SubsystemVidDid;
  92. }
  93. //
  94. // Go to next table entry
  95. //
  96. RegTablePtr++;
  97. }
  98. RegTablePtr = mSubsystemIdRegs;
  99. //
  100. // Program the SSVID/SSDID
  101. //
  102. ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo);
  103. }