EfiRegTableLib.h 5.2 KB

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  1. /*++
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. EfiRegTableLib.h
  6. Abstract:
  7. Definitions and macros for building register tables for chipset
  8. initialization..
  9. Components linking this lib must include PciRootBridgeIo and
  10. BootScriptSave protocols in their DPX.
  11. --*/
  12. #ifndef EFI_REG_TABLE_H
  13. #define EFI_REG_TABLE_H
  14. #include <PiDxe.h>
  15. #include <Library/BaseLib.h>
  16. #include <Library/DebugLib.h>
  17. #include <Library/UefiLib.h>
  18. #include <Protocol/PciRootBridgeIo.h>
  19. #define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF))
  20. #define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF))
  21. #define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))
  22. //
  23. // RegTable Base OpCodes
  24. //
  25. #define OP_TERMINATE_TABLE 0
  26. #define OP_MEM_WRITE 1
  27. #define OP_MEM_READ_MODIFY_WRITE 2
  28. #define OP_IO_WRITE 3
  29. #define OP_IO_READ_MODIFY_WRITE 4
  30. #define OP_PCI_WRITE 5
  31. #define OP_PCI_READ_MODIFY_WRITE 6
  32. #define OP_STALL 7
  33. //
  34. // RegTable OpCode Flags
  35. //
  36. #define OPCODE_FLAG_S3SAVE 1
  37. #define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }
  38. //
  39. // REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode
  40. // as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values
  41. //
  42. typedef struct {
  43. UINT32 OpCode;
  44. UINT32 PciAddress;
  45. UINT32 Data;
  46. } EFI_REG_TABLE_PCI_WRITE;
  47. #define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \
  48. { \
  49. (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
  50. (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
  51. (UINT32) (Data), \
  52. (UINT32) (0) \
  53. }
  54. typedef struct {
  55. UINT32 OpCode;
  56. UINT32 MemAddress;
  57. UINT32 Data;
  58. } EFI_REG_TABLE_MEM_WRITE;
  59. typedef struct {
  60. UINT32 OpCode;
  61. UINT32 PciAddress;
  62. UINT32 OrMask;
  63. UINT32 AndMask;
  64. } EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;
  65. #define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \
  66. { \
  67. (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
  68. (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \
  69. (UINT32) (OrMask), \
  70. (UINT32) (AndMask) \
  71. }
  72. typedef struct {
  73. UINT32 OpCode;
  74. UINT32 MemAddress;
  75. UINT32 OrMask;
  76. UINT32 AndMask;
  77. } EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;
  78. #define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \
  79. { \
  80. (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \
  81. (UINT32) (Address), \
  82. (UINT32) (OrMask), \
  83. (UINT32) (AndMask) \
  84. }
  85. typedef struct {
  86. UINT32 OpCode;
  87. UINT32 Field2;
  88. UINT32 Field3;
  89. UINT32 Field4;
  90. } EFI_REG_TABLE_GENERIC;
  91. typedef union {
  92. EFI_REG_TABLE_GENERIC Generic;
  93. EFI_REG_TABLE_PCI_WRITE PciWrite;
  94. EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite;
  95. EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite;
  96. } EFI_REG_TABLE;
  97. /**
  98. Processes register table assuming which may contain PCI, IO, MEM, and STALL
  99. entries.
  100. No parameter checking is done so the caller must be careful about omitting
  101. values for PciRootBridgeIo parameters. If the regtable does
  102. not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
  103. NULL).
  104. The RegTableEntry parameter is not checked, but is required.
  105. gBS is assumed to have been defined and is used when processing stalls.
  106. The function processes each entry sequentially until an OP_TERMINATE_TABLE
  107. entry is encountered.
  108. @param[in] RegTableEntry A pointer to the register table to process
  109. @param[in] PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used
  110. when processing PCI table entries
  111. @retval Nothing.
  112. **/
  113. VOID
  114. ProcessRegTablePci (
  115. EFI_REG_TABLE * RegTableEntry,
  116. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo
  117. );
  118. #endif