styx-overdrive1000.dts 11 KB

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  1. /*
  2. * DTS file for SoftIron Overdrive 1000, based on AMD Seattle (Rev.B1)
  3. *
  4. * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. */
  9. /dts-v1/;
  10. / {
  11. model = "SoftIron Overdrive 1000 (AMD Seattle (Rev.B1))";
  12. compatible = "amd,seattle-overdrive", "amd,seattle";
  13. interrupt-parent = <0x1>;
  14. #address-cells = <0x2>;
  15. #size-cells = <0x2>;
  16. interrupt-controller@e1101000 {
  17. compatible = "arm,gic-400", "arm,cortex-a15-gic";
  18. interrupt-controller;
  19. #interrupt-cells = <0x3>;
  20. #address-cells = <0x2>;
  21. #size-cells = <0x2>;
  22. reg = <0x0 0xe1110000 0x0 0x1000>,
  23. <0x0 0xe112f000 0x0 0x2000>,
  24. <0x0 0xe1140000 0x0 0x10000>,
  25. <0x0 0xe1160000 0x0 0x10000>;
  26. interrupts = <0x1 0x9 0xf04>;
  27. ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
  28. linux,phandle = <0x1>;
  29. phandle = <0x1>;
  30. v2m@e0080000 {
  31. compatible = "arm,gic-v2m-frame";
  32. msi-controller;
  33. reg = <0x0 0x80000 0x0 0x1000>;
  34. linux,phandle = <0x4>;
  35. phandle = <0x4>;
  36. };
  37. };
  38. timer {
  39. compatible = "arm,armv8-timer";
  40. interrupts = <0x1 0xd 0xff04>,
  41. <0x1 0xe 0xff04>,
  42. <0x1 0xb 0xff04>,
  43. <0x1 0xa 0xff04>;
  44. };
  45. smb {
  46. compatible = "simple-bus";
  47. #address-cells = <0x2>;
  48. #size-cells = <0x2>;
  49. ranges;
  50. /*
  51. * dma-ranges is 40-bit address space containing:
  52. * - GICv2m MSI register is at 0xe0080000
  53. * - DRAM range [0x8000000000 to 0xffffffffff]
  54. */
  55. dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
  56. clk100mhz_0 {
  57. compatible = "fixed-clock";
  58. #clock-cells = <0x0>;
  59. clock-frequency = <100000000>;
  60. clock-output-names = "adl3clk_100mhz";
  61. };
  62. clk375mhz {
  63. compatible = "fixed-clock";
  64. #clock-cells = <0x0>;
  65. clock-frequency = <375000000>;
  66. clock-output-names = "ccpclk_375mhz";
  67. };
  68. clk333mhz {
  69. compatible = "fixed-clock";
  70. #clock-cells = <0x0>;
  71. clock-frequency = <333000000>;
  72. clock-output-names = "sataclk_333mhz";
  73. linux,phandle = <0x2>;
  74. phandle = <0x2>;
  75. };
  76. clk500mhz_0 {
  77. compatible = "fixed-clock";
  78. #clock-cells = <0x0>;
  79. clock-frequency = <500000000>;
  80. clock-output-names = "pcieclk_500mhz";
  81. };
  82. clk500mhz_1 {
  83. compatible = "fixed-clock";
  84. #clock-cells = <0x0>;
  85. clock-frequency = <500000000>;
  86. clock-output-names = "dmaclk_500mhz";
  87. };
  88. clk250mhz_4 {
  89. compatible = "fixed-clock";
  90. #clock-cells = <0x0>;
  91. clock-frequency = <250000000>;
  92. clock-output-names = "miscclk_250mhz";
  93. linux,phandle = <0xd>;
  94. phandle = <0xd>;
  95. };
  96. clk100mhz_1 {
  97. compatible = "fixed-clock";
  98. #clock-cells = <0x0>;
  99. clock-frequency = <100000000>;
  100. clock-output-names = "uartspiclk_100mhz";
  101. linux,phandle = <0x3>;
  102. phandle = <0x3>;
  103. };
  104. sata@e0300000 {
  105. compatible = "snps,dwc-ahci";
  106. reg = <0x0 0xe0300000 0x0 0xf0000>;
  107. interrupts = <0x0 0x163 0x4>;
  108. clocks = <0x2>;
  109. dma-coherent;
  110. };
  111. sata@e0d00000 {
  112. status = "disabled";
  113. compatible = "snps,dwc-ahci";
  114. reg = <0x0 0xe0d00000 0x0 0xf0000>;
  115. interrupts = <0x0 0x162 0x4>;
  116. clocks = <0x2>;
  117. dma-coherent;
  118. };
  119. i2c@e1000000 {
  120. compatible = "snps,designware-i2c";
  121. reg = <0x0 0xe1000000 0x0 0x1000>;
  122. interrupts = <0x0 0x165 0x4>;
  123. clocks = <0xd>;
  124. };
  125. i2c@e0050000 {
  126. compatible = "snps,designware-i2c";
  127. reg = <0x0 0xe0050000 0x0 0x1000>;
  128. interrupts = <0x0 0x154 0x4>;
  129. clocks = <0xd>;
  130. };
  131. serial@e1010000 {
  132. compatible = "arm,pl011", "arm,primecell";
  133. reg = <0x0 0xe1010000 0x0 0x1000>;
  134. interrupts = <0x0 0x148 0x4>;
  135. clocks = <0x3 0x3>;
  136. clock-names = "uartclk", "apb_pclk";
  137. };
  138. ssp@e1020000 {
  139. compatible = "arm,pl022", "arm,primecell";
  140. reg = <0x0 0xe1020000 0x0 0x1000>;
  141. spi-controller;
  142. interrupts = <0x0 0x14a 0x4>;
  143. clocks = <0x3>;
  144. clock-names = "apb_pclk";
  145. };
  146. ssp@e1030000 {
  147. compatible = "arm,pl022", "arm,primecell";
  148. reg = <0x0 0xe1030000 0x0 0x1000>;
  149. spi-controller;
  150. interrupts = <0x0 0x149 0x4>;
  151. clocks = <0x3>;
  152. clock-names = "apb_pclk";
  153. num-cs = <0x1>;
  154. #address-cells = <0x1>;
  155. #size-cells = <0x0>;
  156. sdcard@0 {
  157. compatible = "mmc-spi-slot";
  158. reg = <0x0>;
  159. spi-max-frequency = <20000000>;
  160. voltage-ranges = <3200 3400>;
  161. pl022,hierarchy = <0x0>;
  162. pl022,interface = <0x0>;
  163. pl022,com-mode = <0x0>;
  164. pl022,rx-level-trig = <0x0>;
  165. pl022,tx-level-trig = <0x0>;
  166. };
  167. };
  168. gpio@e1050000 { /* [0 : 7] */
  169. compatible = "arm,pl061", "arm,primecell";
  170. #gpio-cells = <0x2>;
  171. reg = <0x0 0xe1050000 0x0 0x1000>;
  172. gpio-controller;
  173. interrupt-controller;
  174. #interrupt-cells = <0x2>;
  175. interrupts = <0x0 0x166 0x4>;
  176. clocks = <0x3>;
  177. clock-names = "apb_pclk";
  178. };
  179. gpio@e0020000 { /* [8 : 15] */
  180. status = "disabled";
  181. compatible = "arm,pl061", "arm,primecell";
  182. #gpio-cells = <0x2>;
  183. reg = <0x0 0xe0020000 0x0 0x1000>;
  184. gpio-controller;
  185. interrupt-controller;
  186. #interrupt-cells = <0x2>;
  187. interrupts = <0x0 0x16e 0x4>;
  188. clocks = <0x3>;
  189. clock-names = "apb_pclk";
  190. };
  191. gpio@e0030000 { /* [16 : 23] */
  192. status = "disabled";
  193. compatible = "arm,pl061", "arm,primecell";
  194. #gpio-cells = <0x2>;
  195. reg = <0x0 0xe0030000 0x0 0x1000>;
  196. gpio-controller;
  197. interrupt-controller;
  198. #interrupt-cells = <0x2>;
  199. interrupts = <0x0 0x16d 0x4>;
  200. clocks = <0x3>;
  201. clock-names = "apb_pclk";
  202. };
  203. gpio@e0080000 { /* [24] */
  204. compatible = "arm,pl061", "arm,primecell";
  205. #gpio-cells = <0x2>;
  206. reg = <0x0 0xe0080000 0x0 0x1000>;
  207. gpio-controller;
  208. interrupt-controller;
  209. #interrupt-cells = <0x2>;
  210. interrupts = <0x0 0x169 0x4>;
  211. clocks = <0x3>;
  212. clock-names = "apb_pclk";
  213. };
  214. ccp: ccp@e0100000 {
  215. compatible = "amd,ccp-seattle-v1a";
  216. reg = <0x0 0xe0100000 0x0 0x10000>;
  217. interrupts = <0x0 0x3 0x4>;
  218. dma-coherent;
  219. amd,zlib-support = <0x1>;
  220. };
  221. pcie: pcie@f0000000 {
  222. compatible = "pci-host-ecam-generic";
  223. #address-cells = <0x3>;
  224. #size-cells = <0x2>;
  225. #interrupt-cells = <0x1>;
  226. device_type = "pci";
  227. bus-range = <0x0 0x7f>;
  228. msi-parent = <0x4>;
  229. reg = <0x0 0xf0000000 0x0 0x10000000>;
  230. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  231. interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,
  232. <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,
  233. <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>,
  234. <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>;
  235. dma-coherent;
  236. dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
  237. ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
  238. <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
  239. <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
  240. };
  241. ccn@0xe8000000 {
  242. compatible = "arm,ccn-504";
  243. reg = <0x0 0xe8000000 0x0 0x1000000>;
  244. interrupts = <0x0 0x17c 0x4>;
  245. };
  246. gwdt@e0bb0000 {
  247. status = "disabled";
  248. compatible = "arm,sbsa-gwdt";
  249. reg = <0x0 0xe0bb0000 0x0 0x10000
  250. 0x0 0xe0bc0000 0x0 0x10000>;
  251. reg-names = "refresh", "control";
  252. interrupts = <0x0 0x151 0x4>;
  253. interrupt-names = "ws0";
  254. };
  255. kcs@e0010000 {
  256. status = "disabled";
  257. compatible = "ipmi-kcs";
  258. device_type = "ipmi";
  259. reg = <0x0 0xe0010000 0 0x8>;
  260. interrupts = <0 389 4>;
  261. interrupt-names = "ipmi_kcs";
  262. reg-size = <1>;
  263. reg-spacing = <4>;
  264. };
  265. clk250mhz_0 {
  266. compatible = "fixed-clock";
  267. #clock-cells = <0x0>;
  268. clock-frequency = <250000000>;
  269. clock-output-names = "xgmacclk0_dma_250mhz";
  270. linux,phandle = <0x5>;
  271. phandle = <0x5>;
  272. };
  273. clk250mhz_1 {
  274. compatible = "fixed-clock";
  275. #clock-cells = <0x0>;
  276. clock-frequency = <250000000>;
  277. clock-output-names = "xgmacclk0_ptp_250mhz";
  278. linux,phandle = <0x6>;
  279. phandle = <0x6>;
  280. };
  281. clk250mhz_2 {
  282. compatible = "fixed-clock";
  283. #clock-cells = <0x0>;
  284. clock-frequency = <250000000>;
  285. clock-output-names = "xgmacclk1_dma_250mhz";
  286. linux,phandle = <0x7>;
  287. phandle = <0x7>;
  288. };
  289. clk250mhz_3 {
  290. compatible = "fixed-clock";
  291. #clock-cells = <0x0>;
  292. clock-frequency = <250000000>;
  293. clock-output-names = "xgmacclk1_ptp_250mhz";
  294. linux,phandle = <0x8>;
  295. phandle = <0x8>;
  296. };
  297. phy@e1240800 {
  298. status = "disabled";
  299. compatible = "amd,xgbe-phy-seattle-v1a";
  300. reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
  301. <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
  302. <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
  303. interrupts = <0x0 0x143 0x4>;
  304. amd,speed-set = <0x0>;
  305. amd,serdes-blwc = <0x1 0x1 0x0>;
  306. amd,serdes-cdr-rate = <0x2 0x2 0x7>;
  307. amd,serdes-pq-skew = <0xa 0xa 0x12>;
  308. amd,serdes-tx-amp = <0xf 0xf 0xa>;
  309. amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
  310. amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
  311. linux,phandle = <0x9>;
  312. phandle = <0x9>;
  313. };
  314. phy@e1240c00 {
  315. status = "disabled";
  316. compatible = "amd,xgbe-phy-seattle-v1a";
  317. reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
  318. <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
  319. <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
  320. interrupts = <0x0 0x142 0x4>;
  321. amd,speed-set = <0x0>;
  322. amd,serdes-blwc = <0x1 0x1 0x0>;
  323. amd,serdes-cdr-rate = <0x2 0x2 0x7>;
  324. amd,serdes-pq-skew = <0xa 0xa 0x12>;
  325. amd,serdes-tx-amp = <0xf 0xf 0xa>;
  326. amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
  327. amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
  328. linux,phandle = <0xa>;
  329. phandle = <0xa>;
  330. };
  331. xgmac@e0700000 {
  332. status = "disabled";
  333. compatible = "amd,xgbe-seattle-v1a";
  334. reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
  335. interrupts = <0x0 0x145 0x4>,
  336. <0x0 0x15a 0x1>,
  337. <0x0 0x15b 0x1>,
  338. <0x0 0x15c 0x1>,
  339. <0x0 0x15d 0x1>;
  340. amd,per-channel-interrupt;
  341. mac-address = [02 a1 a2 a3 a4 a5];
  342. clocks = <0x5 0x6>;
  343. clock-names = "dma_clk", "ptp_clk";
  344. phy-handle = <0x9>;
  345. phy-mode = "xgmii";
  346. #stream-id-cells = <0x18>;
  347. dma-coherent;
  348. linux,phandle = <0xb>;
  349. phandle = <0xb>;
  350. };
  351. xgmac@e0900000 {
  352. status = "disabled";
  353. compatible = "amd,xgbe-seattle-v1a";
  354. reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
  355. interrupts = <0x0 0x144 0x4>,
  356. <0x0 0x155 0x1>,
  357. <0x0 0x156 0x1>,
  358. <0x0 0x157 0x1>,
  359. <0x0 0x158 0x1>;
  360. amd,per-channel-interrupt;
  361. mac-address = [02 b1 b2 b3 b4 b5];
  362. clocks = <0x7 0x8>;
  363. clock-names = "dma_clk", "ptp_clk";
  364. phy-handle = <0xa>;
  365. phy-mode = "xgmii";
  366. #stream-id-cells = <0x18>;
  367. dma-coherent;
  368. linux,phandle = <0xc>;
  369. phandle = <0xc>;
  370. };
  371. };
  372. chosen {
  373. stdout-path = "/smb/serial@e1010000";
  374. /* Note:
  375. * Linux support for pci-probe-only DT is not
  376. * stable. Disable this for now and let Linux
  377. * take care of the resource assignment.
  378. */
  379. // linux,pci-probe-only;
  380. };
  381. psci {
  382. compatible = "arm,psci-0.2", "arm,psci";
  383. method = "smc";
  384. };
  385. };