/** @file
Header file for BDS Platform specific code
Copyright (c) 2017, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _BDS_PLATFORM_H
#define _BDS_PLATFORM_H
#include
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///
/// ConnectType
///
#define CONSOLE_OUT 0x00000001
#define STD_ERROR 0x00000002
#define CONSOLE_IN 0x00000004
#define CONSOLE_ALL (CONSOLE_OUT | CONSOLE_IN | STD_ERROR)
extern EFI_GUID gUefiShellFileGuid;
extern EFI_BOOT_MODE gBootMode;
#define PCI_DEVICE_PATH_NODE(Func, Dev) \
{ \
HARDWARE_DEVICE_PATH, \
HW_PCI_DP, \
{ \
(UINT8) (sizeof (PCI_DEVICE_PATH)), \
(UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
}, \
(Func), \
(Dev) \
}
#define PNPID_DEVICE_PATH_NODE(PnpId) \
{ \
{ \
ACPI_DEVICE_PATH, \
ACPI_DP, \
{ \
(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
} \
}, \
EISA_PNP_ID((PnpId)), \
0 \
}
#define gPciRootBridge \
{ \
{ \
ACPI_DEVICE_PATH, \
ACPI_DP, \
{ \
(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
}, \
}, \
EISA_PNP_ID (0x0A03), \
0 \
}
#define gPciIsaBridge \
PCI_DEVICE_PATH_NODE(0, 0x1f)
#define gPnp16550ComPort \
PNPID_DEVICE_PATH_NODE(0x0501)
#define gUart(BaudRate, DataBits, Parity, StopBits) \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_UART_DP, \
{ \
(UINT8) (sizeof (UART_DEVICE_PATH)), \
(UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
} \
}, \
0, \
(BaudRate), \
(DataBits), \
(Parity), \
(StopBits) \
}
#define gPcAnsiTerminal \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_VENDOR_DP, \
{ \
(UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
} \
}, \
DEVICE_PATH_MESSAGING_PC_ANSI \
}
#define gEndEntire \
{ \
END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \
}
typedef struct {
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ConnectType;
} BDS_CONSOLE_CONNECT_ENTRY;
//
// Platform Root Bridge
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
//
// Below is the platform console device path
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH IsaBridge;
ACPI_HID_DEVICE_PATH Keyboard;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_KEYBOARD_DEVICE_PATH;
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH PciDevice;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ONBOARD_CONTROLLER_DEVICE_PATH;
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH Pci0Device;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_PEG_ROOT_CONTROLLER_DEVICE_PATH;
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH PciBridge;
PCI_DEVICE_PATH PciDevice;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_PCI_CONTROLLER_DEVICE_PATH;
//
// Below is the boot option device path
//
#define CLASS_HID 3
#define SUBCLASS_BOOT 1
#define PROTOCOL_KEYBOARD 1
typedef struct {
USB_CLASS_DEVICE_PATH UsbClass;
EFI_DEVICE_PATH_PROTOCOL End;
} USB_CLASS_FORMAT_DEVICE_PATH;
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
PCI_DEVICE_PATH IsaBridge;
ACPI_HID_DEVICE_PATH IsaSerial;
UART_DEVICE_PATH Uart;
VENDOR_DEVICE_PATH TerminalType;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ISA_SERIAL_DEVICE_PATH;
//
// Platform BDS Functions
//
/**
Perform the memory test base on the memory test intensive level,
and update the memory resource.
@param Level The memory test intensive level.
@retval EFI_STATUS Success test all the system memory and update
the memory resource
**/
EFI_STATUS
MemoryTest (
IN EXTENDMEM_COVERAGE_LEVEL Level
);
VOID
ConnectSequence (
IN EFI_BOOT_MODE BootMode
);
INTN
EFIAPI
CompareBootOption (
CONST VOID *Left,
CONST VOID *Right
);
VOID
RegisterStaticHotkey (
VOID
);
VOID
RegisterDefaultBootOption (
VOID
);
#endif