Pārlūkot izejas kodu

Add KabylakeOpenBoardPkg

reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com>
reviewed-by: Amy Chan <amy.chan@intel.com>
reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Jiewen Yao 7 gadi atpakaļ
vecāks
revīzija
d6bd444f04
92 mainītis faili ar 13986 papildinājumiem un 0 dzēšanām
  1. 101 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
  2. 313 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
  3. 75 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  4. 43 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL
  5. 27 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
  6. 252 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl
  7. 130 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
  8. 845 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
  9. 39 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
  10. 205 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL
  11. 94 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl
  12. 122 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL
  13. 312 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
  14. 1135 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
  15. 14 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl
  16. 35 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl
  17. 782 0
      Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c
  18. 218 0
      Platform/Intel/KabylakeOpenBoardPkg/Contributions.txt
  19. 121 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PcieDeviceTable.c
  20. 83 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspMiscUpdUpdateLib.c
  21. 148 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.c
  22. 144 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf
  23. 159 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.c
  24. 34 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.h
  25. 254 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
  26. 90 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.c
  27. 37 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.h
  28. 74 0
      Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
  29. 120 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
  30. 123 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
  31. 48 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf
  32. 73 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/IoExpander.h
  33. 128 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/Library/GpioExpanderLib.h
  34. 39 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/Library/I2cAccessLib.h
  35. 57 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/PchHsioPtssTables.h
  36. 53 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
  37. 163 0
      Platform/Intel/KabylakeOpenBoardPkg/Include/SioRegs.h
  38. 66 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat
  39. 21 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/KabylakeRvp3Id.h
  40. 668 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.c
  41. 57 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
  42. 42 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
  43. 53 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
  44. 80 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c
  45. 49 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c
  46. 54 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
  47. 68 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
  48. 53 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
  49. 45 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c
  50. 87 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
  51. 54 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
  52. 174 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
  53. 387 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3GpioTable.c
  54. 238 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3HdaVerbTables.c
  55. 111 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3HsioPtssTables.c
  56. 432 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3SpdTable.c
  57. 45 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPostMemLib.c
  58. 59 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
  59. 111 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.c
  60. 138 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
  61. 71 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3Detect.c
  62. 48 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h
  63. 214 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPostMemLib.c
  64. 235 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
  65. 46 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
  66. 61 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
  67. 88 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
  68. 140 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
  69. 272 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
  70. 555 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
  71. 155 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc
  72. 133 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc
  73. 205 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
  74. 166 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat
  75. 54 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/cln.bat
  76. 45 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/postbuild.bat
  77. 221 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prebuild.bat
  78. 85 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prep.bat
  79. 315 0
      Platform/Intel/KabylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
  80. 39 0
      Platform/Intel/KabylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
  81. 121 0
      Platform/Intel/KabylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.c
  82. 42 0
      Platform/Intel/KabylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
  83. 25 0
      Platform/Intel/KabylakeOpenBoardPkg/License.txt
  84. 262 0
      Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
  85. 71 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/DxeSaPolicyUpdate.c
  86. 181 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c
  87. 45 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h
  88. 62 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c
  89. 46 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h
  90. 72 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
  91. 73 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c
  92. 56 0
      Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h

+ 101 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c

@@ -0,0 +1,101 @@
+/** @file
+  Acpi Gnvs Init Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <PchAccess.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/MpService.h>
+
+/**
+@brief
+  Global NVS initialize.
+
+  @param[in] GlobalNvs         - Pointer of Global NVS area
+
+  @retval EFI_SUCCESS          - Allocate Global NVS completed.
+  @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+  IN OUT VOID                   **GlobalNvs
+  )
+{
+  UINTN                         Pages;
+  EFI_PHYSICAL_ADDRESS          Address;
+  EFI_STATUS                    Status;
+  EFI_GLOBAL_NVS_AREA_PROTOCOL  *GNVS;
+  EFI_MP_SERVICES_PROTOCOL      *MpService;
+  UINTN                         NumberOfCPUs;
+  UINTN                         NumberOfEnabledCPUs;
+
+  Pages = EFI_SIZE_TO_PAGES (sizeof (EFI_GLOBAL_NVS_AREA));
+  Address = 0xffffffff; // allocate address below 4G.
+
+  Status  = gBS->AllocatePages (
+                   AllocateMaxAddress,
+                   EfiACPIMemoryNVS,
+                   Pages,
+                   &Address
+                   );
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+  
+  //
+  // Locate the MP services protocol
+  // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
+  //
+  Status = gBS->LocateProtocol (
+                  &gEfiMpServiceProtocolGuid,
+                  NULL,
+                  (VOID **) &MpService
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Determine the number of processors
+  //
+  MpService->GetNumberOfProcessors (
+              MpService,
+              &NumberOfCPUs,
+              &NumberOfEnabledCPUs
+              );
+
+  *GlobalNvs = (VOID *) (UINTN) Address;
+  SetMem (*GlobalNvs, sizeof (EFI_GLOBAL_NVS_AREA), 0);
+
+  //
+  // GNVS default value init here...
+  //
+  GNVS = (EFI_GLOBAL_NVS_AREA_PROTOCOL *) &Address;
+
+  GNVS->Area->ThreadCount = (UINT8)NumberOfEnabledCPUs;
+
+  //
+  // Miscellaneous
+  //
+  GNVS->Area->PL1LimitCS = 0;
+  GNVS->Area->PL1LimitCSValue = 4500;
+
+  return EFI_SUCCESS;
+}
+

+ 313 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c

@@ -0,0 +1,313 @@
+/** @file
+  ACPI Platform Driver
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/AslUpdateLib.h>
+
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL              mGlobalNvsArea;
+
+/**
+@brief
+  Global NVS initialize.
+  
+  @param[in] GlobalNvs         - Pointer of Global NVS area
+
+  @retval EFI_SUCCESS          - Allocate Global NVS completed.
+  @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+  IN OUT VOID                   **GlobalNvs
+  );
+
+VOID
+UpdateDsdt (
+  IN VOID   *Table
+  );
+
+//
+// Function implementations
+//
+
+/**
+  Locate the first instance of a protocol.  If the protocol requested is an
+  FV protocol, then it will return the first FV that contains the ACPI table
+  storage file.
+
+  @param[in] Protocol           The protocol to find.
+  @param[in] Instance           Return pointer to the first instance of the protocol.
+  @param[in] Type               TRUE if the desired protocol is a FV protocol.
+
+  @retval EFI_SUCCESS           The function completed successfully.
+  @retval EFI_NOT_FOUND         The protocol could not be located.
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+  IN     EFI_GUID                      *Protocol,
+  IN     EFI_GUID                      *gEfiAcpiMultiTableStorageGuid,
+     OUT VOID                          **Instance,
+  IN     BOOLEAN                       Type
+  )
+{
+  EFI_STATUS              Status;
+  EFI_HANDLE              *HandleBuffer;
+  UINTN                   NumberOfHandles;
+  EFI_FV_FILETYPE         FileType;
+  UINT32                  FvStatus;
+  EFI_FV_FILE_ATTRIBUTES  Attributes;
+  UINTN                   Size;
+  UINTN                   Index;
+
+  //
+  // Locate protocol.
+  //
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  Protocol,
+                  NULL,
+                  &NumberOfHandles,
+                  &HandleBuffer
+                  );
+  if (EFI_ERROR (Status)) {
+    //
+    // Defined errors at this time are not found and out of resources.
+    //
+    return Status;
+  }
+
+  //
+  // Looking for FV with ACPI storage file
+  //
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+
+    //
+    // Get the protocol on this handle
+    // This should not fail because of LocateHandleBuffer
+    //
+    Status = gBS->HandleProtocol (
+                    HandleBuffer[Index],
+                    Protocol,
+                    Instance
+                    );
+    ASSERT_EFI_ERROR (Status);
+
+    if (!Type) {
+
+      //
+      // Not looking for the FV protocol, so find the first instance of the
+      // protocol.  There should not be any errors because our handle buffer
+      // should always contain at least one or LocateHandleBuffer would have
+      // returned not found.
+      //
+      break;
+    }
+
+    //
+    // See if it has the ACPI storage file
+    //
+    Size      = 0;
+    FvStatus  = 0;
+    Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+                                                              *Instance,
+                                                              gEfiAcpiMultiTableStorageGuid,
+                                                              NULL,
+                                                              &Size,
+                                                              &FileType,
+                                                              &Attributes,
+                                                              &FvStatus
+                                                              );
+
+    //
+    // If we found it, then we are done
+    //
+    if (Status == EFI_SUCCESS) {
+      break;
+    }
+  }
+
+  //
+  // Our exit status is determined by the success of the previous operations
+  // If the protocol was found, Instance already points to it.
+  //
+  //
+  // Free any allocated buffers
+  //
+  FreePool (HandleBuffer);
+
+  return Status;
+}
+
+EFI_STATUS
+PublishAcpiTablesFromFv (
+  IN EFI_GUID *gEfiAcpiMultiTableStorageGuid
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+  EFI_ACPI_COMMON_HEADER        *CurrentTable;
+  UINT32                        FvStatus;
+  UINTN                         Size;
+  EFI_ACPI_TABLE_VERSION        Version;
+  UINTN                         TableHandle;
+  INTN                          Instance;
+  EFI_ACPI_TABLE_PROTOCOL       *AcpiTable;
+
+  Instance      = 0;
+  TableHandle   = 0;
+  CurrentTable  = NULL;
+  FwVol         = NULL;
+
+  //
+  // Find the AcpiSupport protocol
+  //
+  Status = LocateSupportProtocol (
+            &gEfiAcpiTableProtocolGuid,
+            gEfiAcpiMultiTableStorageGuid,
+            (VOID **) &AcpiTable,
+            FALSE
+            );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Locate the firmware volume protocol
+  //
+  Status = LocateSupportProtocol (
+            &gEfiFirmwareVolume2ProtocolGuid,
+            gEfiAcpiMultiTableStorageGuid,
+            (VOID **) &FwVol,
+            TRUE
+            );
+
+  //
+  // Read tables from the storage file.
+  //
+
+  while (Status == EFI_SUCCESS) {
+    Status = FwVol->ReadSection (
+                      FwVol,
+                      gEfiAcpiMultiTableStorageGuid,
+                      EFI_SECTION_RAW,
+                      Instance,
+                      (VOID **) &CurrentTable,
+                      &Size,
+                      &FvStatus
+                      );
+
+    if (!EFI_ERROR (Status)) {
+
+      //
+      // Perform any table specific updates.
+      //
+      if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+        UpdateDsdt (CurrentTable);
+      }
+      BoardUpdateAcpiTable (CurrentTable, &Version);
+
+      //
+      // Add the table
+      //
+      TableHandle = 0;
+
+      if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
+        Status = AcpiTable->InstallAcpiTable (
+                              AcpiTable,
+                              CurrentTable,
+                              CurrentTable->Length,
+                              &TableHandle
+                              );
+      }
+
+      ASSERT_EFI_ERROR (Status);
+
+      //
+      // Increment the instance
+      //
+      Instance++;
+      CurrentTable = NULL;
+    }
+  }
+
+  //
+  // Finished
+  //
+  return EFI_SUCCESS;
+}
+
+/**
+  ACPI Platform driver installation function.
+
+  @param[in] ImageHandle     Handle for this drivers loaded image protocol.
+  @param[in] SystemTable     EFI system table.
+
+  @retval EFI_SUCCESS        The driver installed without error.
+  @retval EFI_ABORTED        The driver encountered an error and could not complete installation of
+                             the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiBoard (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS   Status;
+  EFI_HANDLE   Handle;
+
+  AcpiGnvsInit((VOID **) &mGlobalNvsArea.Area);
+
+  //
+  // This PCD set must be done before PublishAcpiTablesFromFv.
+  // The PCD data will be used there.
+  //
+  PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mGlobalNvsArea.Area);
+
+  //
+  // Platform ACPI Tables
+  //
+  PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
+
+  //
+  // This protocol publish must be done after PublishAcpiTablesFromFv.
+  // The NVS data is be updated there.
+  //
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEfiGlobalNvsAreaProtocolGuid,
+                  &mGlobalNvsArea,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+  
+  return EFI_SUCCESS;
+}

+ 75 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf

@@ -0,0 +1,75 @@
+### @file
+#  Component information file for AcpiPlatform module
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = BoardAcpiDxe
+  FILE_GUID                      = E269E77D-6163-4F5D-8E59-21EAF114D307
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InstallAcpiBoard
+
+[Sources.common]
+  BoardAcpiDxe.c
+  AcpiGnvsInit.c
+  UpdateDsdt.c
+  Dsdt/DSDT.ASL
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  PcAtChipsetPkg/PcAtChipsetPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  BaseLib
+  DebugLib
+  IoLib
+  PcdLib
+  UefiBootServicesTableLib
+  UefiRuntimeServicesTableLib
+  BaseMemoryLib
+  HobLib
+  AslUpdateLib
+  BoardAcpiTableLib
+
+[Protocols]
+  gEfiAcpiTableProtocolGuid                     ## CONSUMES
+  gEfiFirmwareVolume2ProtocolGuid               ## CONSUMES
+  gEfiMpServiceProtocolGuid                     ## CONSUMES
+  gEfiGlobalNvsAreaProtocolGuid
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
+
+  gBoardModuleTokenSpaceGuid.PcdAcpiSleepState
+  gBoardModuleTokenSpaceGuid.PcdAcpiHibernate
+  gPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle
+  gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints
+  gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints
+  gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints
+
+[Depex]
+  gEfiAcpiTableProtocolGuid           AND
+  gEfiFirmwareVolume2ProtocolGuid     AND
+  gEfiPciRootBridgeIoProtocolGuid     AND
+  gEfiVariableArchProtocolGuid        AND
+  gEfiVariableWriteArchProtocolGuid
+
+

+ 43 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL

@@ -0,0 +1,43 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(ALSD) 
+{
+  Name(_HID,"ACPI0008")
+
+  Method(_STA,0)
+  {
+    If(LEqual(ALSE,2))
+    {
+      Return(0x000B)    // ALS Enabled.  Don't show it in UI.
+    }
+
+    Return(0x0000)      // ALS Disabled.  Hide it.
+  }
+
+  Method(_ALI)
+  {
+    Return (Or(ShiftLeft(LHIH,8),LLOW))
+  }
+
+  Name(_ALR, Package()
+  {
+    Package() {70,  0},
+    Package() {73,  10},
+    Package() {85,  80},
+    Package() {100, 300},
+    Package() {150, 1000}
+  })
+  
+}

+ 27 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl

@@ -0,0 +1,27 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+///////////////////////////////////////////////////////////////////////////////////
+//Values are set like this to have ASL compiler reserve enough space for objects
+///////////////////////////////////////////////////////////////////////////////////
+//
+// Available Sleep states
+//
+Name(SS1,0)
+Name(SS2,0)
+Name(SS3,1)
+Name(SS4,1)
+

+ 252 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl

@@ -0,0 +1,252 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(\_PR)
+{
+  Processor(PR00,   // Unique name for Processor 0.
+    1,              // Unique ID for Processor 0.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR01,   // Unique name for Processor 1.
+    2,              // Unique ID for Processor 1.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR02,   // Unique name for Processor 2.
+    3,              // Unique ID for Processor 2.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR03,   // Unique name for Processor 3.
+    4,              // Unique ID for Processor 3.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR04,   // Unique name for Processor 4.
+    5,              // Unique ID for Processor 4.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR05,   // Unique name for Processor 5.
+    6,              // Unique ID for Processor 5.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR06,   // Unique name for Processor 6.
+    7,              // Unique ID for Processor 6.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR07,   // Unique name for Processor 7.
+    8,              // Unique ID for Processor 7.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR08,   // Unique name for Processor 8.
+    9,              // Unique ID for Processor 8.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR09,   // Unique name for Processor 9.
+    10,             // Unique ID for Processor 9.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR10,   // Unique name for Processor 10.
+    11,             // Unique ID for Processor 10.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR11,   // Unique name for Processor 11.
+    12,             // Unique ID for Processor 11.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR12,   // Unique name for Processor 12.
+    13,             // Unique ID for Processor 12.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR13,   // Unique name for Processor 13.
+    14,             // Unique ID for Processor 13.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR14,   // Unique name for Processor 14.
+    15,             // Unique ID for Processor 14.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+
+  Processor(PR15,   // Unique name for Processor 15.
+    16,             // Unique ID for Processor 15.
+    0x1810,         // P_BLK address = ACPIBASE + 10h.
+    6)              // P_BLK length = 6 bytes.
+  {}
+} // End Scope(\_PR)
+
+//
+// _CPC (Continuous Performance Control) Package declaration
+//  Package
+//  {
+//    NumEntries,                           // Integer
+//    Revision,                             // Integer
+//    HighestPerformance,                   // Generic Register Descriptor
+//    NominalPerformance,                   // Generic Register Descriptor
+//    LowestNonlinearPerformance,           // Generic Register Descriptor
+//    LowestPerformance,                    // Generic Register Descriptor
+//    GuaranteedPerformanceRegister,        // Generic Register Descriptor
+//    DesiredPerformanceRegister,           // Generic Register Descriptor
+//    MinimumPerformanceRegister,           // Generic Register Descriptor
+//    MaximumPerformanceRegister,           // Generic Register Descriptor
+//    PerformanceReductionToleranceRegister,// Generic Register Descriptor
+//    TimeWindowRegister,                   // Generic Register Descriptor
+//    CounterWraparoundTime,                // Generic Register Descriptor
+//    NominalCounterRegister,               // Generic Register Descriptor
+//    DeliveredCounterRegister,             // Generic Register Descriptor
+//    PerformanceLimitedRegister,           // Generic Register Descriptor
+//    EnableRegister                        // Generic Register Descriptor
+//  }
+//
+Scope(\_PR.PR00)
+{
+  Name(CPC2, Package()
+  {
+    21, // Number of entries
+    02, // Revision
+    //
+    // Describe processor capabilities
+    //
+    ResourceTemplate() {Register(FFixedHW, 8, 0, 0x771, 4)}, // HighestPerformance
+    ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)},  // Nominal Performance - Maximum Non Turbo Ratio
+    ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
+    ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
+    ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
+    ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
+    ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
+    ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
+    ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
+    ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window  register(Null)
+    ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
+    ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
+    ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
+    ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
+    ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
+    1, // Autonomous selection enable register (Exclusively autonomous)
+    ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
+    ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
+    0 // Reference performance (not supported)
+  })
+
+  Name(CPOC, Package()
+  {
+    21, // Number of entries
+    02, // Revision
+    //
+    // Describe processor capabilities
+    //
+    255, // HighestPerformance
+    ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)},  // Nominal Performance - Maximum Non Turbo Ratio
+    ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
+    ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
+    ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
+    ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
+    ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
+    ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
+    ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
+    ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window  register(Null)
+    ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
+    ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
+    ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
+    ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
+    ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
+    1, // Autonomous selection enable register (Exclusively autonomous)
+    ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
+    ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
+    0 // Reference performance (not supported)
+  })
+
+}// end Scope(\_PR.PR00)
+
+#ifndef SPS_SUPPORT // SPS is using Processor Aggregator Device different way
+Scope(\_SB)
+{
+  // The Processor Aggregator Device provides a control point that enables the platform to perform
+  // specific processor configuration and control that applies to all processors in the platform.
+  Device (PAGD)
+  {
+    Name (_HID, "ACPI000C") // Processor Aggregator Device
+
+    // _STA (Status)
+    //
+    // This object returns the current status of a device.
+    //
+    // Arguments: (0)
+    //   None
+    // Return Value:
+    //   An Integer containing a device status bitmap:
+    //    Bit 0 - Set if the device is present.
+    //    Bit 1 - Set if the device is enabled and decoding its resources.
+    //    Bit 2 - Set if the device should be shown in the UI.
+    //    Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics).
+    //    Bit 4 - Set if the battery is present.
+    //    Bits 5-31 - Reserved (must be cleared).
+    //
+    Method(_STA)
+    {
+      If(\_OSI("Processor Aggregator Device")){
+        Return (0x0F) // Processor Aggregator Device is supported by this OS.
+      } Else {
+        Return (0)    // No support in this OS.
+      }
+    }
+
+
+    // _PUR (Processor Utilization Request)
+    //
+    // The _PUR object is an optional object that may be declared under the Processor Aggregator Device
+    // and provides a means for the platform to indicate to OSPM the number of logical processors
+    // to be idled. OSPM evaluates the _PUR object as a result of the processing of a Notify event
+    // on the Processor Aggregator device object of type 0x80.
+    //
+    // Arguments: (0)
+    //   None
+    // Return Value:
+    //   Package
+    //
+    Name (_PUR, Package() // Requests a number of logical processors to be placed in an idle state.
+    {
+      1,                           // RevisionID, Integer: Current value is 1
+      0                            // NumProcessors, Integer
+    })
+
+  } // end Device(PAGD)
+}// end Scope(\_SB)
+#endif // ndef SPS_SUPPORT
+

+ 130 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL

@@ -0,0 +1,130 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+  "DSDT.aml",
+  "DSDT",
+  0x02, // DSDT revision.
+        // A Revision field value greater than or equal to 2 signifies that integers 
+        // declared within the Definition Block are to be evaluated as 64-bit values
+  "INTEL",   // OEM ID (6 byte string)
+  "SKL     ",// OEM table ID  (8 byte string)
+  0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+  External(LHIH)
+  External(LLOW)
+  External(IGDS)
+  External(LIDS)
+  External(BRTL)
+  External(ALSE)
+  External(GSMI)
+  External(\_SB.PCI0.GFX0, DeviceObj)
+  External(\_SB.PCI0.GFX0.ALSI)
+  External(\_SB.PCI0.GFX0.CDCK)
+  External(\_SB.PCI0.GFX0.CBLV)
+  External(\_SB.PCI0.GFX0.GSSE)
+  External(\_SB.PCI0.ISP0, DeviceObj)
+  External(\_SB.PCI0.PEG0, DeviceObj)
+  External(\_SB.PCI0.PEG0.PEGP, DeviceObj)
+  External(\_SB.PCI0.PEG1, DeviceObj)
+  External(\_SB.PCI0.PEG2, DeviceObj)
+  External(\_SB.PCI0.GFX0.DD1F, DeviceObj)
+  External(\_SB.PCI0.GFX0.GDCK, MethodObj)
+  External(\_SB.PCI0.GFX0.GHDS, MethodObj)
+  External(\_SB.PCI0.GFX0.AINT, MethodObj)
+  External(\_SB.PCI0.GFX0.GLID, MethodObj)
+  External(\_SB.PCI0.GFX0.GSCI, MethodObj)
+  External(\_PR.PR00, DeviceObj)
+  External(\_PR.PR00._PSS, MethodObj)
+  External(\_PR.PR00.LPSS, PkgObj)
+  External(\_PR.PR00.TPSS, PkgObj)
+  External(\_PR.PR00._PPC, MethodObj)
+  External(\_PR.CPPC, IntObj)
+  External(\_TZ.TZ00, DeviceObj)
+  External(\_TZ.TZ01, DeviceObj)
+  External(\_TZ.ETMD, IntObj)
+  External(\_TZ.FN00._OFF, MethodObj)
+  // Miscellaneous services enabled in Project
+  Include ("AMLUPD.asl")
+  Include ("Acpi/GlobalNvs.asl")
+  Include ("PciTree.asl")
+
+  if(LEqual(ECR1,1)){
+    Scope(\_SB.PCI0) {
+      //
+      // PCI-specific method's GUID
+      //
+      Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
+      //
+      // PCI's _DSM - an attempt at modular _DSM implementation
+      // When writing your own _DSM function that needs to include PCI-specific methods, do this:
+      //
+      // Method(_YOUR_DSM,4){ 
+      //   if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
+      //   ...continue your _DSM by checking different GUIDs...
+      //   else { return(0) }
+      // } 
+      //
+      Method(PCID, 4, Serialized) {
+        If(LEqual(Arg0, PCIG)) {         // PCIE capabilities UUID
+          If(LGreaterEqual(Arg1,3)) {                                              // revision at least 3
+            If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) }                   // function 0: list of supported functions
+            If(LEqual(Arg2,8)) { Return (1) }                                      // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
+            If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations
+          }
+        }
+        return (Buffer(1){0})
+      }
+    }//scope
+  }//if
+
+  Scope(\_SB.PCI0) {
+    //PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct
+    Method(PCIC,1,Serialized) {
+      If(LEqual(ECR1,1)) {
+        If(LEqual(Arg0, PCIG)) {
+          return (1)
+        }
+      }
+      return (0)
+    }
+  }
+
+  Include ("Pch.asl")  // Not in this package. Refer to the PCH Reference Code accordingly
+  Include ("LpcB.asl")
+  Include ("Platform.asl")
+  Include ("CPU.asl")
+  Include ("PCI_DRC.ASL")
+  Include ("Video.asl")
+  Include ("PlatformGnvs.asl")
+  Include ("Gpe.asl")
+
+  Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state
+  if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})}
+  if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})}
+  if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})}
+  Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state
+
+  Method(PTS, 1) {        // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE
+    If(Arg0)              // entering any sleep state
+      {
+      }
+    }
+    Method(WAK, 1) {      // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP
+  }
+}// End of ASL File
+

+ 845 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl

@@ -0,0 +1,845 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+  // General Purpose Events.  This Scope handles the Run-time and
+  // Wake-time SCIs.  The specific method called will be determined by
+  // the _Lxx value, where xx equals the bit location in the General
+  // Purpose Event register(s).
+
+
+  External(D1F0)
+  External(D1F1)
+  External(D1F2)
+  External(\_SB.PCI0.PEG0.HPME, MethodObj)
+  External(\_SB.PCI0.PEG1.HPME, MethodObj)
+  External(\_SB.PCI0.PEG2.HPME, MethodObj)
+  External(\_GPE.AL6F, MethodObj)
+  External(\_GPE.P0L6, MethodObj)
+  External(\_GPE.P1L6, MethodObj)
+  External(\_GPE.P2L6, MethodObj)
+  External(SGGP)
+  External(P1GP)
+  External(P2GP)
+  External(P0WK)
+  External(P1WK)
+  External(P2WK)
+  External(\_PR.HWPI, IntObj)
+  External(\_PR.DTSI, IntObj)
+
+  Scope(\_GPE)
+  {
+  // Note:
+  // Originally, the two GPE methods below are automatically generated, but, for ASL code restructuring,
+  // disabled the automatic generation and declare the ASL code here.
+  //
+
+  //
+  // This PME event (PCH's GPE 69h) is received on one or more of the PCI Express* ports or
+  // an assert PMEGPE message received via DMI
+  //
+  Method(_L69, 0, serialized) {
+    \_SB.PCI0.RP01.HPME()
+    \_SB.PCI0.RP02.HPME()
+    \_SB.PCI0.RP03.HPME()
+    \_SB.PCI0.RP04.HPME()
+    \_SB.PCI0.RP05.HPME()
+    \_SB.PCI0.RP06.HPME()
+    \_SB.PCI0.RP07.HPME()
+    \_SB.PCI0.RP08.HPME()
+    \_SB.PCI0.RP09.HPME()
+    \_SB.PCI0.RP10.HPME()
+    \_SB.PCI0.RP11.HPME()
+    \_SB.PCI0.RP12.HPME()
+    \_SB.PCI0.RP13.HPME()
+    \_SB.PCI0.RP14.HPME()
+    \_SB.PCI0.RP15.HPME()
+    \_SB.PCI0.RP16.HPME()
+    \_SB.PCI0.RP17.HPME()
+    \_SB.PCI0.RP18.HPME()
+    \_SB.PCI0.RP19.HPME()
+    \_SB.PCI0.RP20.HPME()
+    \_SB.PCI0.RP21.HPME()
+    \_SB.PCI0.RP22.HPME()
+    \_SB.PCI0.RP23.HPME()
+    \_SB.PCI0.RP24.HPME()
+
+    If(LEqual(D1F0,1))
+    {
+      \_SB.PCI0.PEG0.HPME()
+      Notify(\_SB.PCI0.PEG0, 0x02)
+      Notify(\_SB.PCI0.PEG0.PEGP, 0x02)
+    }
+
+    If(LEqual(D1F1,1))
+    {
+      \_SB.PCI0.PEG1.HPME()
+      Notify(\_SB.PCI0.PEG1, 0x02)
+    }
+
+    If(LEqual(D1F2,1))
+    {
+      \_SB.PCI0.PEG2.HPME()
+      Notify(\_SB.PCI0.PEG2, 0x02)
+    }
+  }
+
+  // PCI Express Hot-Plug caused the wake event.
+
+  Method(_L61)
+  {
+    Add(L01C,1,L01C)  // Increment L01 Entry Count.
+
+    P8XH(0,0x01)      // Output information to Port 80h.
+    P8XH(1,L01C)
+
+
+    // Check Root Port 1 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF),\_SB.PCI0.RP01.HPSX))
+    {
+      // Delay for 100ms to meet the timing requirements
+      // of the PCI Express Base Specification, Revision
+      // 1.0A, Section 6.6 ("...software must wait at
+      // least 100ms from the end of reset of one or more
+      // device before it is permitted to issue
+      // Configuration Requests to those devices").
+
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS1,0x1)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP01.PDCX)
+      {
+        // Clear all status bits first.
+
+        Store(1,\_SB.PCI0.RP01.PDCX)
+        Store(1,\_SB.PCI0.RP01.HPSX)
+
+        //
+        // PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
+        // In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
+        // hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
+        // disabled on empty slots prior booting to OS.
+        //
+        If(LNot(\_SB.PCI0.RP01.PDSX)) {
+          // The PCI Express slot is empty, so disable L0s on hot unplug
+          //
+          Store(0,\_SB.PCI0.RP01.L0SE)
+
+        }
+
+        // Perform proper notification
+        // to the OS.
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS1,0x1)))) {
+          Notify(\_SB.PCI0.RP01,0)
+        }
+      }
+      Else
+      {
+        // False event.  Clear Hot-Plug Status
+        // then exit.
+
+        Store(1,\_SB.PCI0.RP01.HPSX)
+      }
+    }
+
+    // Check Root Port 2 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF),\_SB.PCI0.RP02.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS1,0x2)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP02.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP02.PDCX)
+        Store(1,\_SB.PCI0.RP02.HPSX)
+
+        If(LNot(\_SB.PCI0.RP02.PDSX)) {
+          Store(0,\_SB.PCI0.RP02.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS1,0x2)))) {
+          Notify(\_SB.PCI0.RP02,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP02.HPSX)
+      }
+    }
+
+    // Check Root Port 3 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF),\_SB.PCI0.RP03.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS1,0x3)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP03.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP03.PDCX)
+        Store(1,\_SB.PCI0.RP03.HPSX)
+
+        If(LNot(\_SB.PCI0.RP03.PDSX)) {
+          Store(0,\_SB.PCI0.RP03.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS1,0x3)))) {
+          Notify(\_SB.PCI0.RP03,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP03.HPSX)
+      }
+    }
+
+    // Check Root Port 4 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF),\_SB.PCI0.RP04.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS1,0x4)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP04.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP04.PDCX)
+        Store(1,\_SB.PCI0.RP04.HPSX)
+
+        If(LNot(\_SB.PCI0.RP04.PDSX)) {
+          Store(0,\_SB.PCI0.RP04.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS1,0x4)))) {
+          Notify(\_SB.PCI0.RP04,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP04.HPSX)
+      }
+    }
+
+    // Check Root Port 5 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF),\_SB.PCI0.RP05.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,0x5)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP05.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP05.PDCX)
+        Store(1,\_SB.PCI0.RP05.HPSX)
+
+        If(LNot(\_SB.PCI0.RP05.PDSX)) {
+          Store(0,\_SB.PCI0.RP05.L0SE)
+        }
+
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,0x5)))) {
+          Notify(\_SB.PCI0.RP05,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP05.HPSX)
+      }
+    }
+
+    // Check Root Port 6 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF),\_SB.PCI0.RP06.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS1,0x6)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP06.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP06.PDCX)
+        Store(1,\_SB.PCI0.RP06.HPSX)
+
+        If(LNot(\_SB.PCI0.RP06.PDSX)) {
+          Store(0,\_SB.PCI0.RP06.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS1,0x6)))) {
+          Notify(\_SB.PCI0.RP06,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP06.HPSX)
+      }
+    }
+
+    // Check Root Port 7 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF),\_SB.PCI0.RP07.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x7),LNotEqual(TBS1,0x7)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP07.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP07.PDCX)
+        Store(1,\_SB.PCI0.RP07.HPSX)
+
+        If(LNot(\_SB.PCI0.RP07.PDSX)) {
+          Store(0,\_SB.PCI0.RP07.L0SE)
+        }
+
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP07.HPSX)
+      }
+    }
+
+    // Check Root Port 8 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF),\_SB.PCI0.RP08.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x8),LNotEqual(TBS1,0x8)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP08.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP08.PDCX)
+        Store(1,\_SB.PCI0.RP08.HPSX)
+
+        If(LNot(\_SB.PCI0.RP08.PDSX)) {
+          Store(0,\_SB.PCI0.RP08.L0SE)
+        }
+
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP08.HPSX)
+      }
+    }
+
+    // Check Root Port 9 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF),\_SB.PCI0.RP09.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS1,0x9)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP09.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP09.PDCX)
+        Store(1,\_SB.PCI0.RP09.HPSX)
+
+        If(LNot(\_SB.PCI0.RP09.PDSX)) {
+          Store(0,\_SB.PCI0.RP09.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS1,0x9)))) {
+          Notify(\_SB.PCI0.RP09,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP09.HPSX)
+      }
+    }
+
+    // Check Root Port 10 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF),\_SB.PCI0.RP10.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS1,0xA)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP10.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP10.PDCX)
+        Store(1,\_SB.PCI0.RP10.HPSX)
+
+        If(LNot(\_SB.PCI0.RP10.PDSX)) {
+          Store(0,\_SB.PCI0.RP10.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS1,0xA)))) {
+          Notify(\_SB.PCI0.RP10,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP10.HPSX)
+      }
+    }
+
+    // Check Root Port 11 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF),\_SB.PCI0.RP11.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS1,0xB)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP11.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP11.PDCX)
+        Store(1,\_SB.PCI0.RP11.HPSX)
+
+        If(LNot(\_SB.PCI0.RP11.PDSX)) {
+          Store(0,\_SB.PCI0.RP11.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS1,0xB)))) {
+          Notify(\_SB.PCI0.RP11,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP11.HPSX)
+      }
+    }
+
+    // Check Root Port 12 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF),\_SB.PCI0.RP12.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS1,0xC)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP12.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP12.PDCX)
+        Store(1,\_SB.PCI0.RP12.HPSX)
+
+        If(LNot(\_SB.PCI0.RP12.PDSX)) {
+          Store(0,\_SB.PCI0.RP12.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS1,0xC)))) {
+          Notify(\_SB.PCI0.RP12,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP12.HPSX)
+      }
+    }
+
+    // Check Root Port 13 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF),\_SB.PCI0.RP13.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS1,0xD)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP13.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP13.PDCX)
+        Store(1,\_SB.PCI0.RP13.HPSX)
+
+        If(LNot(\_SB.PCI0.RP13.PDSX)) {
+          Store(0,\_SB.PCI0.RP13.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS1,0xD)))) {
+          Notify(\_SB.PCI0.RP13,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP13.HPSX)
+      }
+    }
+
+    // Check Root Port 14 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF),\_SB.PCI0.RP14.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS1,0xE)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP14.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP14.PDCX)
+        Store(1,\_SB.PCI0.RP14.HPSX)
+
+        If(LNot(\_SB.PCI0.RP14.PDSX)) {
+          Store(0,\_SB.PCI0.RP14.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS1,0xE)))) {
+          Notify(\_SB.PCI0.RP14,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP14.HPSX)
+      }
+    }
+
+    // Check Root Port 15 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF),\_SB.PCI0.RP15.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS1,0xF)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP15.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP15.PDCX)
+        Store(1,\_SB.PCI0.RP15.HPSX)
+
+        If(LNot(\_SB.PCI0.RP15.PDSX)) {
+          Store(0,\_SB.PCI0.RP15.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS1,0xF)))) {
+          Notify(\_SB.PCI0.RP15,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP15.HPSX)
+      }
+    }
+
+    // Check Root Port 16 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF),\_SB.PCI0.RP16.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TBS1,0x10)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP16.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP16.PDCX)
+        Store(1,\_SB.PCI0.RP16.HPSX)
+
+        If(LNot(\_SB.PCI0.RP16.PDSX)) {
+          Store(0,\_SB.PCI0.RP16.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TBS1,0x10)))) {
+          Notify(\_SB.PCI0.RP16,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP16.HPSX)
+      }
+    }
+
+    // Check Root Port 17 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF),\_SB.PCI0.RP17.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TBS1,0x11)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP17.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP17.PDCX)
+        Store(1,\_SB.PCI0.RP17.HPSX)
+
+        If(LNot(\_SB.PCI0.RP17.PDSX)) {
+          Store(0,\_SB.PCI0.RP17.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TBS1,0x11)))) {
+          Notify(\_SB.PCI0.RP17,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP17.HPSX)
+      }
+    }
+
+    // Check Root Port 18 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF),\_SB.PCI0.RP18.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TBS1,0x12)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP18.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP18.PDCX)
+        Store(1,\_SB.PCI0.RP18.HPSX)
+
+        If(LNot(\_SB.PCI0.RP18.PDSX)) {
+          Store(0,\_SB.PCI0.RP18.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TBS1,0x12)))) {
+          Notify(\_SB.PCI0.RP18,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP18.HPSX)
+      }
+    }
+
+    // Check Root Port 19 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF),\_SB.PCI0.RP19.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TBS1,0x13)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP19.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP19.PDCX)
+        Store(1,\_SB.PCI0.RP19.HPSX)
+
+        If(LNot(\_SB.PCI0.RP19.PDSX)) {
+          Store(0,\_SB.PCI0.RP19.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TBS1,0x13)))) {
+          Notify(\_SB.PCI0.RP19,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP19.HPSX)
+      }
+    }
+
+    // Check Root Port 20 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF),\_SB.PCI0.RP20.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TBS1,0x14)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP20.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP20.PDCX)
+        Store(1,\_SB.PCI0.RP20.HPSX)
+
+        If(LNot(\_SB.PCI0.RP20.PDSX)) {
+          Store(0,\_SB.PCI0.RP20.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TBS1,0x14)))) {
+          Notify(\_SB.PCI0.RP20,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP20.HPSX)
+      }
+    }
+
+    // Check Root Port 21 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP21.VDID,0xFFFFFFFF),\_SB.PCI0.RP21.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TBS1,0x21)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP21.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP21.PDCX)
+        Store(1,\_SB.PCI0.RP21.HPSX)
+
+        If(LNot(\_SB.PCI0.RP21.PDSX)) {
+          Store(0,\_SB.PCI0.RP21.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TBS1,0x21)))) {
+          Notify(\_SB.PCI0.RP21,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP21.HPSX)
+      }
+    }
+
+    // Check Root Port 22 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP22.VDID,0xFFFFFFFF),\_SB.PCI0.RP22.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TBS1,0x22)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP22.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP22.PDCX)
+        Store(1,\_SB.PCI0.RP22.HPSX)
+
+        If(LNot(\_SB.PCI0.RP22.PDSX)) {
+          Store(0,\_SB.PCI0.RP22.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TBS1,0x22)))) {
+          Notify(\_SB.PCI0.RP22,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP22.HPSX)
+      }
+    }
+
+    // Check Root Port 23 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP23.VDID,0xFFFFFFFF),\_SB.PCI0.RP23.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TBS1,0x23)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP23.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP23.PDCX)
+        Store(1,\_SB.PCI0.RP23.HPSX)
+
+        If(LNot(\_SB.PCI0.RP23.PDSX)) {
+          Store(0,\_SB.PCI0.RP23.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TBS1,0x23)))) {
+          Notify(\_SB.PCI0.RP23,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP23.HPSX)
+      }
+    }
+
+    // Check Root Port 24 for a Hot Plug Event if the Port is
+    // enabled.
+
+    If(LAnd(LNotEqual(\_SB.PCI0.RP24.VDID,0xFFFFFFFF),\_SB.PCI0.RP24.HPSX))
+    {
+      If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TBS1,0x24)))) {
+        Sleep(100)
+      }
+
+      If(\_SB.PCI0.RP24.PDCX)
+      {
+        Store(1,\_SB.PCI0.RP24.PDCX)
+        Store(1,\_SB.PCI0.RP24.HPSX)
+
+        If(LNot(\_SB.PCI0.RP24.PDSX)) {
+          Store(0,\_SB.PCI0.RP24.L0SE)
+        }
+
+        If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TBS1,0x24)))) {
+          Notify(\_SB.PCI0.RP24,0)
+        }
+      }
+      Else
+      {
+        Store(1,\_SB.PCI0.RP24.HPSX)
+      }
+    }
+  }
+
+  //
+  // Software GPE caused the event.
+  //
+  Method(_L62)
+  {
+    // Clear GPE status bit.
+    Store(0,GPEC)
+
+    //
+    // Handle DTS Thermal SCI Event.
+    //
+    If(CondRefOf(\_PR.DTSE)){
+      If(LGreaterEqual(\_PR.DTSE, 0x01)){
+        If(LEqual(\_PR.DTSI, 1)){
+          Notify(\_TZ.TZ00,0x80)
+          Notify(\_TZ.TZ01,0x80)
+          ///
+          /// Clear HWP interrupt status
+          ///
+          Store(0,\_PR.DTSI)
+        }
+      }
+    }
+    ///
+    /// Handle HWP SCI event
+    ///
+    External(\_GPE.HLVT, MethodObj)
+    If(LEqual(\_PR.HWPI, 1)){
+      If(CondRefOf(\_GPE.HLVT)){
+        \_GPE.HLVT()
+      }
+      ///
+      /// Clear HWP interrupt status
+      ///
+      Store(0,\_PR.HWPI)
+    }
+  }
+
+  // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
+
+  Method(_L66)
+  {
+    If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?
+    {
+      \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI
+    }
+  }
+
+}

+ 39 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl

@@ -0,0 +1,39 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+// ITSS
+// Define the needed ITSS registers used by ASL on Interrupt
+// mapping.
+
+scope(\_SB){
+      OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208)
+      Field(ITSS, ByteAcc, NoLock, Preserve)
+      {
+        PARC, 8,
+        PBRC, 8,
+        PCRC, 8,
+        PDRC, 8,
+        PERC, 8,
+        PFRC, 8,
+        PGRC, 8,
+        PHRC, 8,
+       Offset(0x200),   // Offset 3300h ITSSPRC - ITSS Power Reduction Control
+            , 1,
+            , 1,
+        SCGE, 1,        // ITSSPRC[2]: 8254 Static Clock Gating Enable (8254CGE)
+
+      }
+}
+
+

+ 205 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL

@@ -0,0 +1,205 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(FWHD)  // Firmware Hub Device
+{
+  Name(_HID,EISAID("INT0800"))        
+
+  Name(_CRS,ResourceTemplate()
+  {
+    Memory32Fixed(ReadOnly,0xFF000000,0x1000000)
+  })
+}
+
+
+Device(HPET)  // High Performance Event Timer
+{
+  Name(_HID,EISAID("PNP0103"))
+  Name(_UID, 0)
+
+  Name(BUF0,ResourceTemplate()
+  {
+    Memory32Fixed(ReadWrite,0xFED00000,0x400,FED0)
+  })
+
+  Method(_STA,0)
+  {
+    // Show this Device only if the OS is WINXP or beyond.
+    If(HPTE)
+    {
+      Return(0x000F)  // Enabled, do Display.
+    }
+
+    Return(0x0000)      // Return Nothing.
+  }
+
+  Method(_CRS,0,Serialized)
+  {
+    If(HPTE)
+    {
+      // Check if HPETimer Base should be modified.
+      CreateDwordField(BUF0,^FED0._BAS,HPT0)
+      Store(HPTB,HPT0)
+    }
+
+    Return(BUF0)
+  }
+}
+
+Device(IPIC)  // 8259 PIC
+{
+  Name(_HID,EISAID("PNP0000"))
+
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16,0x20,0x20,0x01,0x02)
+    IO(Decode16,0x24,0x24,0x01,0x02)
+    IO(Decode16,0x28,0x28,0x01,0x02)
+    IO(Decode16,0x2C,0x2C,0x01,0x02)
+    IO(Decode16,0x30,0x30,0x01,0x02)
+    IO(Decode16,0x34,0x34,0x01,0x02)
+    IO(Decode16,0x38,0x38,0x01,0x02)
+    IO(Decode16,0x3C,0x3C,0x01,0x02)
+    IO(Decode16,0xA0,0xA0,0x01,0x02)
+    IO(Decode16,0xA4,0xA4,0x01,0x02)
+    IO(Decode16,0xA8,0xA8,0x01,0x02)
+    IO(Decode16,0xAC,0xAC,0x01,0x02)
+    IO(Decode16,0xB0,0xB0,0x01,0x02)
+    IO(Decode16,0xB4,0xB4,0x01,0x02)
+    IO(Decode16,0xB8,0xB8,0x01,0x02)
+    IO(Decode16,0xBC,0xBC,0x01,0x02)
+    IO(Decode16,0x4D0,0x4D0,0x01,0x02)
+    IRQNoFlags() {2}
+  })
+}
+
+
+Device(MATH)  // Math Co-Processor
+{
+  Name(_HID,EISAID("PNP0C04"))
+
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16,0xF0,0xF0,0x01,0x01)
+    IRQNoFlags() {13}
+  })
+
+  //
+  // Report device present for LPT-H.
+  //
+  Method (_STA, 0x0, NotSerialized) 
+  {
+    If(LEqual(PCHV(), SPTH)) {
+      Return(0x1F)
+    } else {
+      Return(0x0)
+    }
+  }
+}
+
+
+Device(LDRC)  // LPC Device Resource Consumption
+{
+  Name(_HID,EISAID("PNP0C02"))        
+
+  Name(_UID,2)
+
+  Name(_CRS,ResourceTemplate()                      // This is for Cougar Point
+  {
+    IO(Decode16,0x2E,0x2E,0x1,0x02)             // SIO Access.
+    IO(Decode16,0x4E,0x4E,0x1,0x02)             // LPC Slot Access.
+    IO(Decode16,0x61,0x61,0x1,0x1)               // NMI Status.           
+    IO(Decode16,0x63,0x63,0x1,0x1)               // Processor I/F.
+    IO(Decode16,0x65,0x65,0x1,0x1)               // Processor I/F.
+    IO(Decode16,0x67,0x67,0x1,0x1)               // Processor I/F.
+    IO(Decode16,0x70,0x70,0x1,0x1)               // NMI Enable.          
+    IO(Decode16,0x80,0x80,0x1,0x1)               // Port 80h.
+    IO(Decode16,0x92,0x92,0x1,0x1)               // Processor I/F.
+    IO(Decode16,0xB2,0xB2,0x01,0x02)           // Software SMI.
+    IO(Decode16,0x680,0x680,0x1,0x20)        // 32 Byte I/O.
+    IO(Decode16,0xFFFF,0xFFFF,0x1,0x1)        // ACPI IO Trap.
+    IO(Decode16,0xFFFF,0xFFFF,0x1,0x1)        // DTS IO Trap. 
+    IO(Decode16,0xFFFF,0xFFFF,0x1,0x1)        // HotKey IO Trap.                      
+
+    IO(Decode16, 0x1800,0x1800,0x1,0xFF)     // PCH ACPI Base
+
+    IO(Decode16,0x164e,0x164e,0x1,0x02)    // 16 Byte I/O.
+  })
+}
+
+Device(LDR2)  // LPC Device Resource Consumption for PCH GPIO
+{
+  Name(_HID,EISAID("PNP0C02"))        
+
+  Name(_UID, "LPC_DEV")
+  
+  // LPT-H GPIO resource map
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16, 0x800,0x800,0x1,0x80)       // PCH GPIO Base.
+  })
+
+  Method(_STA, 0, NotSerialized)
+  {
+    If(LEqual(PCHV(), SPTH)) {
+      Return(0xF)
+    } else {
+      Return(0)
+    }
+  }
+}
+
+Device(RTC) // RTC
+{
+  Name(_HID,EISAID("PNP0B00"))
+
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16,0x70,0x70,0x01,0x08)
+    IRQNoFlags() {8}
+  })
+}
+
+Device(TIMR)  // 8254 Timer
+{
+  Name(_HID,EISAID("PNP0100"))
+
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16,0x40,0x40,0x01,0x04)
+    IO(Decode16,0x50,0x50,0x10,0x04)
+    IRQNoFlags() {0}
+  })
+}
+    
+Device(CWDT)
+{
+  Name(_HID,EISAID("INT3F0D"))
+  Name(_CID,EISAID("PNP0C02"))
+  Name(BUF0,ResourceTemplate()
+    {
+      IO(Decode16, 0x1854, 0x1854, 0x4, 0x4)  // PMBS 0x1800 + Offset 0x54
+    }
+  )
+  
+  Method(_STA,0,Serialized)
+  {
+    Return(0x0F)
+  }
+  
+  Method(_CRS,0,Serialized)
+  {
+    Return(BUF0)
+  }
+}

+ 94 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl

@@ -0,0 +1,94 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+// LPC Bridge - Device 31, Function 0
+scope (\_SB.PCI0.LPCB) {
+      Include ("LPC_DEV.ASL")
+
+      // Define the KBC_COMMAND_REG-64, KBC_DATA_REG-60 Registers as an ACPI Operating
+      // Region.  These registers will be used to skip kbd mouse
+      // resource settings if not present.
+      OperationRegion(PKBS, SystemIO, 0x60, 0x05)
+      Field(PKBS, ByteAcc, Lock, Preserve)
+      {
+        PKBD, 8,
+        , 8,
+        , 8,
+        , 8,
+        PKBC, 8
+      }
+      Device(PS2K)    // PS2 Keyboard
+      {
+        Name(_HID,"MSFT0001")
+        Name(_CID,EISAID("PNP0303"))
+
+        Method(_STA)
+        {
+          If (P2MK) //Ps2 Keyboard and Mouse Enable
+          {
+            Return(0x000F)
+          }
+          Return(0x0000)
+        }
+
+        Name(_CRS,ResourceTemplate()
+        {
+          IO(Decode16,0x60,0x60,0x01,0x01)
+          IO(Decode16,0x64,0x64,0x01,0x01)
+          IRQ(Edge,ActiveHigh,Exclusive){0x01}
+        })
+
+        Name(_PRS, ResourceTemplate(){
+          StartDependentFn(0, 0) {
+          FixedIO(0x60,0x01)
+          FixedIO(0x64,0x01)
+          IRQNoFlags(){1}
+          }
+          EndDependentFn()
+        })
+
+      }
+
+      Device(PS2M)    // PS/2 Mouse
+      {
+        Name(_HID,"MSFT0003")
+        Name(_CID,EISAID("PNP0F03"))
+
+        Method(_STA)
+        {
+          If (P2ME) //Ps2 Mouse Enable
+          {
+            If (P2MK) //Ps2 Keyboard and Mouse Enable
+            {
+              Return(0x000F)
+            }
+          }
+          Return(0x0000)
+        }
+
+        Name(_CRS,ResourceTemplate()
+        {
+          IRQ(Edge,ActiveHigh,Exclusive){0x0C}
+        })
+
+        Name(_PRS, ResourceTemplate(){
+          StartDependentFn(0, 0) {
+          IRQNoFlags(){12}
+          }
+          EndDependentFn()
+        })
+      }
+
+}

+ 122 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL

@@ -0,0 +1,122 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+Scope (\_SB.PCI0){
+
+  Device(PDRC)
+  {
+    //
+    // PCI Device Resource Consumption
+    //
+
+    Name(_HID,EISAID("PNP0C02"))        
+
+    Name(_UID,1)
+
+    Name(BUF0,ResourceTemplate()
+    {
+      //
+      // MCH BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.48h
+      //
+      Memory32Fixed(ReadWrite,0,0x08000,MCHB) 
+      //
+      // DMI BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.68h
+      //
+      Memory32Fixed(ReadWrite,0,0x01000,DMIB) 
+      //
+      // EP BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.40h
+      //
+      Memory32Fixed(ReadWrite,0,0x01000,EGPB)
+      //
+      // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
+      //
+      Memory32Fixed(ReadWrite,0,0,PCIX)  
+
+      //
+      // MISC ICH TTT base address reserved for the TxT module use. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0xFED20000,0x20000)   
+      
+      //
+      // VTD engine memory range. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000)
+      
+      //
+      // MISC ICH. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM)
+      
+      //
+      // FLASH range
+      //
+      Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) //16MB as per IOH spec
+      
+      //
+      // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
+      //
+      Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
+      
+      //
+      // Sx handler reserved MMIO
+      //
+      Memory32Fixed (ReadWrite, 0, 0, SXRE)
+      
+      //
+      // Reserve HPET address decode range
+      //
+      Memory32Fixed (ReadWrite, 0, 0, HPET)
+
+    })
+ 
+
+    Method(_CRS,0,Serialized)
+    {
+
+      CreateDwordField(BUF0,^MCHB._BAS,MBR0)
+      Store(\_SB.PCI0.GMHB(), MBR0)
+
+      CreateDwordField(BUF0,^DMIB._BAS,DBR0)
+      Store(\_SB.PCI0.GDMB(), DBR0)
+
+      CreateDwordField(BUF0,^EGPB._BAS,EBR0)
+      Store(\_SB.PCI0.GEPB(), EBR0)
+
+      CreateDwordField(BUF0,^PCIX._BAS,XBR0)
+      Store(\_SB.PCI0.GPCB(), XBR0)
+
+      CreateDwordField(BUF0,^PCIX._LEN,XSZ0)
+      Store(\_SB.PCI0.GPCL(), XSZ0)
+
+      CreateDwordField(BUF0,^SXRE._BAS,SXRA)
+      Store(SXRB, SXRA)
+      CreateDwordField(BUF0,^SXRE._LEN,SXRL)
+      Store(SXRS, SXRL)
+
+      // HPET device claims the resource in LPC_DEV.ASL.
+      If(LNOT(HPTE)){
+        CreateDwordField(BUF0,^HPET._BAS,HBAS)
+        CreateDwordField(BUF0,^HPET._LEN,HLEN)
+        Store(HPTB, HBAS)
+        Store(0x400, HLEN)
+      }
+
+      Return(BUF0)
+    }
+  } //end of PDRC
+} // end of SB

+ 312 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl

@@ -0,0 +1,312 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(\_SB) {
+  Name(PR00, Package(){
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+    Package(){0x001FFFFF, 0, LNKA, 0 },
+    Package(){0x001FFFFF, 1, LNKB, 0 },
+    Package(){0x001FFFFF, 2, LNKC, 0 },
+    Package(){0x001FFFFF, 3, LNKD, 0 },
+// D30: SerialIo and SCS - can't use PIC
+// D29: PCI Express Port 9-16
+    Package(){0x001DFFFF, 0, LNKA, 0 },
+    Package(){0x001DFFFF, 1, LNKB, 0 },
+    Package(){0x001DFFFF, 2, LNKC, 0 },
+    Package(){0x001DFFFF, 3, LNKD, 0 },
+// D28: PCI Express Port 1-8
+    Package(){0x001CFFFF, 0, LNKA, 0 },
+    Package(){0x001CFFFF, 1, LNKB, 0 },
+    Package(){0x001CFFFF, 2, LNKC, 0 },
+    Package(){0x001CFFFF, 3, LNKD, 0 },
+// D27: PCI Express Port 17-20
+    Package(){0x001BFFFF, 0, LNKA, 0 },
+    Package(){0x001BFFFF, 1, LNKB, 0 },
+    Package(){0x001BFFFF, 2, LNKC, 0 },
+    Package(){0x001BFFFF, 3, LNKD, 0 },
+// D25: SerialIo - can't use PIC
+// D23: SATA controller
+    Package(){0x0017FFFF, 0, LNKA, 0 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+    Package(){0x0016FFFF, 0, LNKA, 0 },
+    Package(){0x0016FFFF, 1, LNKB, 0 },
+    Package(){0x0016FFFF, 2, LNKC, 0 },
+    Package(){0x0016FFFF, 3, LNKD, 0 },
+// D21: SerialIo - can't use PIC
+// D20: xHCI, Thermal Subsystem, Camera IO Host Controller
+    Package(){0x0014FFFF, 0, LNKA, 0 },
+    Package(){0x0014FFFF, 1, LNKB, 0 },
+    Package(){0x0014FFFF, 2, LNKC, 0 },
+    Package(){0x0014FFFF, 3, LNKD, 0 },
+// D19: Integrated Sensor Hub - can't use PIC
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+    Package(){0x0001FFFF, 0, LNKA, 0 },
+    Package(){0x0001FFFF, 1, LNKB, 0 },
+    Package(){0x0001FFFF, 2, LNKC, 0 },
+    Package(){0x0001FFFF, 3, LNKD, 0 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+    Package(){0x0002FFFF, 0, LNKA, 0 },
+// SA Thermal Device
+    Package(){0x0004FFFF, 0, LNKA, 0 },
+// SA SkyCam Device
+    Package(){0x0005FFFF, 0, LNKA, 0 },
+// SA GMM Device
+    Package(){0x0008FFFF, 0, LNKA, 0 },
+  })
+  Name(AR00, Package(){
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+    Package(){0x001FFFFF, 0, 0, 16 },
+    Package(){0x001FFFFF, 1, 0, 17 },
+    Package(){0x001FFFFF, 2, 0, 18 },
+    Package(){0x001FFFFF, 3, 0, 19 },
+// D30: SerialIo and SCS
+    Package(){0x001EFFFF, 0, 0, 20 },
+    Package(){0x001EFFFF, 1, 0, 21 },
+    Package(){0x001EFFFF, 2, 0, 22 },
+    Package(){0x001EFFFF, 3, 0, 23 },
+// D29: PCI Express Port 9-16
+    Package(){0x001DFFFF, 0, 0, 16 },
+    Package(){0x001DFFFF, 1, 0, 17 },
+    Package(){0x001DFFFF, 2, 0, 18 },
+    Package(){0x001DFFFF, 3, 0, 19 },
+// D28: PCI Express Port 1-8
+    Package(){0x001CFFFF, 0, 0, 16 },
+    Package(){0x001CFFFF, 1, 0, 17 },
+    Package(){0x001CFFFF, 2, 0, 18 },
+    Package(){0x001CFFFF, 3, 0, 19 },
+// D27: PCI Express Port 17-20
+    Package(){0x001BFFFF, 0, 0, 16 },
+    Package(){0x001BFFFF, 1, 0, 17 },
+    Package(){0x001BFFFF, 2, 0, 18 },
+    Package(){0x001BFFFF, 3, 0, 19 },
+// D25: SerialIo
+    Package(){0x0019FFFF, 0, 0, 32 },
+    Package(){0x0019FFFF, 1, 0, 33 },
+    Package(){0x0019FFFF, 2, 0, 34 },
+// D23: SATA controller
+    Package(){0x0017FFFF, 0, 0, 16 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+    Package(){0x0016FFFF, 0, 0, 16 },
+    Package(){0x0016FFFF, 1, 0, 17 },
+    Package(){0x0016FFFF, 2, 0, 18 },
+    Package(){0x0016FFFF, 3, 0, 19 },
+// D21: SerialIo
+    Package(){0x0015FFFF, 0, 0, 16 },
+    Package(){0x0015FFFF, 1, 0, 17 },
+    Package(){0x0015FFFF, 2, 0, 18 },
+    Package(){0x0015FFFF, 3, 0, 19 },
+// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
+    Package(){0x0014FFFF, 0, 0, 16 },
+    Package(){0x0014FFFF, 1, 0, 17 },
+    Package(){0x0014FFFF, 2, 0, 18 },
+    Package(){0x0014FFFF, 3, 0, 19 },
+// D19: Integrated Sensor Hub
+    Package(){0x0013FFFF, 0, 0, 20 },
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+    Package(){0x0001FFFF, 0, 0, 16 },
+    Package(){0x0001FFFF, 1, 0, 17 },
+    Package(){0x0001FFFF, 2, 0, 18 },
+    Package(){0x0001FFFF, 3, 0, 19 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+    Package(){0x0002FFFF, 0, 0, 16 },
+// SA Thermal Device
+    Package(){0x0004FFFF, 0, 0, 16 },
+// SA SkyCam Device
+    Package(){0x0005FFFF, 0, 0, 16 },
+// SA GMM Device
+    Package(){0x0008FFFF, 0, 0, 16 },
+  })
+  Name(PR04, Package(){
+    Package(){0x0000FFFF, 0, LNKA, 0 },
+    Package(){0x0000FFFF, 1, LNKB, 0 },
+    Package(){0x0000FFFF, 2, LNKC, 0 },
+    Package(){0x0000FFFF, 3, LNKD, 0 },
+  })
+  Name(AR04, Package(){
+    Package(){0x0000FFFF, 0, 0, 16 },
+    Package(){0x0000FFFF, 1, 0, 17 },
+    Package(){0x0000FFFF, 2, 0, 18 },
+    Package(){0x0000FFFF, 3, 0, 19 },
+  })
+  Name(PR05, Package(){
+    Package(){0x0000FFFF, 0, LNKB, 0 },
+    Package(){0x0000FFFF, 1, LNKC, 0 },
+    Package(){0x0000FFFF, 2, LNKD, 0 },
+    Package(){0x0000FFFF, 3, LNKA, 0 },
+  })
+  Name(AR05, Package(){
+    Package(){0x0000FFFF, 0, 0, 17 },
+    Package(){0x0000FFFF, 1, 0, 18 },
+    Package(){0x0000FFFF, 2, 0, 19 },
+    Package(){0x0000FFFF, 3, 0, 16 },
+  })
+  Name(PR06, Package(){
+    Package(){0x0000FFFF, 0, LNKC, 0 },
+    Package(){0x0000FFFF, 1, LNKD, 0 },
+    Package(){0x0000FFFF, 2, LNKA, 0 },
+    Package(){0x0000FFFF, 3, LNKB, 0 },
+  })
+  Name(AR06, Package(){
+    Package(){0x0000FFFF, 0, 0, 18 },
+    Package(){0x0000FFFF, 1, 0, 19 },
+    Package(){0x0000FFFF, 2, 0, 16 },
+    Package(){0x0000FFFF, 3, 0, 17 },
+  })
+  Name(PR07, Package(){
+    Package(){0x0000FFFF, 0, LNKD, 0 },
+    Package(){0x0000FFFF, 1, LNKA, 0 },
+    Package(){0x0000FFFF, 2, LNKB, 0 },
+    Package(){0x0000FFFF, 3, LNKC, 0 },
+  })
+  Name(AR07, Package(){
+    Package(){0x0000FFFF, 0, 0, 19 },
+    Package(){0x0000FFFF, 1, 0, 16 },
+    Package(){0x0000FFFF, 2, 0, 17 },
+    Package(){0x0000FFFF, 3, 0, 18 },
+  })
+  Name(PR08, Package(){
+    Package(){0x0000FFFF, 0, LNKA, 0 },
+    Package(){0x0000FFFF, 1, LNKB, 0 },
+    Package(){0x0000FFFF, 2, LNKC, 0 },
+    Package(){0x0000FFFF, 3, LNKD, 0 },
+  })
+  Name(AR08, Package(){
+    Package(){0x0000FFFF, 0, 0, 16 },
+    Package(){0x0000FFFF, 1, 0, 17 },
+    Package(){0x0000FFFF, 2, 0, 18 },
+    Package(){0x0000FFFF, 3, 0, 19 },
+  })
+  Name(PR09, Package(){
+    Package(){0x0000FFFF, 0, LNKB, 0 },
+    Package(){0x0000FFFF, 1, LNKC, 0 },
+    Package(){0x0000FFFF, 2, LNKD, 0 },
+    Package(){0x0000FFFF, 3, LNKA, 0 },
+  })
+  Name(AR09, Package(){
+    Package(){0x0000FFFF, 0, 0, 17 },
+    Package(){0x0000FFFF, 1, 0, 18 },
+    Package(){0x0000FFFF, 2, 0, 19 },
+    Package(){0x0000FFFF, 3, 0, 16 },
+  })
+  Name(PR0E, Package(){
+    Package(){0x0000FFFF, 0, LNKC, 0 },
+    Package(){0x0000FFFF, 1, LNKD, 0 },
+    Package(){0x0000FFFF, 2, LNKA, 0 },
+    Package(){0x0000FFFF, 3, LNKB, 0 },
+  })
+  Name(AR0E, Package(){
+    Package(){0x0000FFFF, 0, 0, 18 },
+    Package(){0x0000FFFF, 1, 0, 19 },
+    Package(){0x0000FFFF, 2, 0, 16 },
+    Package(){0x0000FFFF, 3, 0, 17 },
+  })
+  Name(PR0F, Package(){
+    Package(){0x0000FFFF, 0, LNKD, 0 },
+    Package(){0x0000FFFF, 1, LNKA, 0 },
+    Package(){0x0000FFFF, 2, LNKB, 0 },
+    Package(){0x0000FFFF, 3, LNKC, 0 },
+  })
+  Name(AR0F, Package(){
+    Package(){0x0000FFFF, 0, 0, 19 },
+    Package(){0x0000FFFF, 1, 0, 16 },
+    Package(){0x0000FFFF, 2, 0, 17 },
+    Package(){0x0000FFFF, 3, 0, 18 },
+  })
+  Name(PR02, Package(){
+    Package(){0x0000FFFF, 0, LNKA, 0 },
+    Package(){0x0000FFFF, 1, LNKB, 0 },
+    Package(){0x0000FFFF, 2, LNKC, 0 },
+    Package(){0x0000FFFF, 3, LNKD, 0 },
+  })
+  Name(AR02, Package(){
+// P.E.G. Port Slot x16
+    Package(){0x0000FFFF, 0, 0, 16 },
+    Package(){0x0000FFFF, 1, 0, 17 },
+    Package(){0x0000FFFF, 2, 0, 18 },
+    Package(){0x0000FFFF, 3, 0, 19 },
+  })
+  Name(PR0A, Package(){
+// P.E.G. Port Slot x8
+    Package(){0x0000FFFF, 0, LNKB, 0 },
+    Package(){0x0000FFFF, 1, LNKC, 0 },
+    Package(){0x0000FFFF, 2, LNKD, 0 },
+    Package(){0x0000FFFF, 3, LNKA, 0 },
+  })
+  Name(AR0A, Package(){
+// P.E.G. Port Slot x8
+    Package(){0x0000FFFF, 0, 0, 17 },
+    Package(){0x0000FFFF, 1, 0, 18 },
+    Package(){0x0000FFFF, 2, 0, 19 },
+    Package(){0x0000FFFF, 3, 0, 16 },
+  })
+  Name(PR0B, Package(){
+// P.E.G. Port Slot x4
+    Package(){0x0000FFFF, 0, LNKC, 0 },
+    Package(){0x0000FFFF, 1, LNKD, 0 },
+    Package(){0x0000FFFF, 2, LNKA, 0 },
+    Package(){0x0000FFFF, 3, LNKB, 0 },
+  })
+  Name(AR0B, Package(){
+// P.E.G. Port Slot x4
+    Package(){0x0000FFFF, 0, 0, 18 },
+    Package(){0x0000FFFF, 1, 0, 19 },
+    Package(){0x0000FFFF, 2, 0, 16 },
+    Package(){0x0000FFFF, 3, 0, 17 },
+  })
+//---------------------------------------------------------------------------
+// List of IRQ resource buffers compatible with _PRS return format.
+//---------------------------------------------------------------------------
+// Naming legend:
+// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
+// Note. PRSy name is generated if IRQ Link name starts from "LNK".
+// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
+//---------------------------------------------------------------------------
+  Name(PRSA, ResourceTemplate(){  // Link name: LNKA
+    IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
+  })
+  Alias(PRSA,PRSB)  // Link name: LNKB
+  Alias(PRSA,PRSC)  // Link name: LNKC
+  Alias(PRSA,PRSD)  // Link name: LNKD
+  Alias(PRSA,PRSE)  // Link name: LNKE
+  Alias(PRSA,PRSF)  // Link name: LNKF
+  Alias(PRSA,PRSG)  // Link name: LNKG
+  Alias(PRSA,PRSH)  // Link name: LNKH
+//---------------------------------------------------------------------------
+// Begin PCI tree object scope
+//---------------------------------------------------------------------------
+  Device(PCI0) { // PCI Bridge "Host Bridge"
+    Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+    Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
+    Name(_ADR, 0x00000000)
+    Method(^BN00, 0){ return(0x0000) }  // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
+    Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
+    Name(_UID, 0x0000)  // Unique Bus ID, optional
+    Method(_PRT,0) {
+      If(PICM) {Return(AR00)} // APIC mode
+      Return (PR00) // PIC Mode
+    } // end _PRT
+
+  Include("HostBus.asl")
+  } // end PCI0 Bridge "Host Bridge"
+} // end _SB scope

+ 1135 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl

@@ -0,0 +1,1135 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#define TRAP_TYPE_DTS     0x02
+#define TRAP_TYPE_IGD     0x03
+#define TRAP_TYPE_BGD     0x04  // BIOS Guard
+
+// Define the following External variables to prevent a WARNING when
+// using ASL.EXE and an ERROR when using IASL.EXE.
+
+External(\PC00, IntObj) // PR00 _PDC Flags
+External(\PC01)
+External(\PC02)
+External(\PC03)
+External(\PC04)
+External(\PC05)
+External(\PC06)
+External(\PC07)
+External(\PC08)
+External(\PC09)
+External(\PC10)
+External(\PC11)
+External(\PC12)
+External(\PC13)
+External(\PC14)
+External(\PC15)
+External(\_PR.CFGD)
+External(\SGMD)
+
+//
+// DTS externals
+//
+External(\_PR.DTSF)
+External(\_PR.DTSE)
+External(\_PR.TRPD)
+External(\_PR.TRPF)
+External(\_PR.DSAE)
+//
+//  SGX
+//
+External(\_PR.EPCS)
+External(\_PR.EMNA)
+External(\_PR.ELNG)
+
+External(\_SB.PCI0.GFX0.TCHE)   // Technology enabled indicator
+External(\_SB.PCI0.GFX0.STAT)   // State Indicator
+
+External(\_SB.TPM.PTS, MethodObj)
+External(\_SB.PCI0.PAUD.PUAM, MethodObj) //PUAM - PowerResource User Absent Mode
+External(\_SB.PCI0.XHC.DUAM, MethodObj)  //DUAM - Device User Absent Mode for XHCI controller
+External(\_SB.PCI0.I2C4.GEXP.INVC, MethodObj)
+
+External(\_SB.PCI0.GFX0.IUEH, MethodObj)
+
+#define CONVERTIBLE_BUTTON   6
+#define DOCK_INDICATOR       7
+
+Name(ECUP, 1)  // EC State indicator: 1- Normal Mode 0- Low Power Mode
+Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power State 1- Someone else is accessing the EC Power State
+
+
+
+External(TBTD, MethodObj)
+External(TBTF, MethodObj)
+External(MMRP, MethodObj)
+External(MMTB, MethodObj)
+External(TBFF, MethodObj)
+External(FFTB, MethodObj)
+External(SXTB, MethodObj)
+
+
+// Interrupt specific registers
+include("Itss.asl")
+
+// Create a Global MUTEX.
+
+Mutex(MUTX,0)
+
+// OS Up mutex
+Mutex(OSUM, 0)
+// _WAK Finished Event
+Event(WFEV)
+
+// Define Port 80 as an ACPI Operating Region to use for debugging.  Please
+// note that the Intel CRBs have the ability to ouput an entire DWord to
+// Port 80h for debugging purposes, so the model implemented here may not be
+// able to be used on OEM Designs.
+
+OperationRegion(PRT0,SystemIO,0x80,4)
+Field(PRT0,DwordAcc,Lock,Preserve)
+{
+  P80H, 32
+}
+
+// Port 80h Update:
+//    Update 8 bits of the 32-bit Port 80h.
+//
+//  Arguments:
+//    Arg0: 0 = Write Port 80h, Bits 7:0 Only.
+//            1 = Write Port 80h, Bits 15:8 Only.
+//            2 = Write Port 80h, Bits 23:16 Only.
+//            3 = Write Port 80h, Bits 31:24 Only.
+//    Arg1: 8-bit Value to write
+//
+//  Return Value:
+//    None
+
+Method(D8XH,2,Serialized)
+{
+  If(LEqual(Arg0,0))    // Write Port 80h, Bits 7:0.
+  {
+    Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
+  }
+
+  If(LEqual(Arg0,1))    // Write Port 80h, Bits 15:8.
+  {
+    Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
+  }
+
+  If(LEqual(Arg0,2))    // Write Port 80h, Bits 23:16.
+  {
+    Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
+  }
+
+  If(LEqual(Arg0,3))    // Write Port 80h, Bits 31:24.
+  {
+    Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
+  }
+
+  Store(P80D,P80H)
+}
+
+// Debug Port 80h Update:
+//    If Acpidebug is enabled only then call D8XH to update 8 bits of the 32-bit Port 80h.
+//
+//  Arguments:
+//    Arg0: 0 = Write Port 80h, Bits 7:0 Only.
+//            1 = Write Port 80h, Bits 15:8 Only.
+//            2 = Write Port 80h, Bits 23:16 Only.
+//            3 = Write Port 80h, Bits 31:24 Only.
+//    Arg1: 8-bit Value to write
+//
+//  Return Value:
+//    None
+Method(P8XH,2,Serialized)
+{
+  // If ACPI debug is enabled, then display post codes on Port 80h
+  If(CondRefOf(MDBG)) {// Check if ACPI Debug SSDT is loaded
+     D8XH(Arg0,Arg1)
+   }
+}
+
+Method(ADBG,1,Serialized)
+{
+  Return(0)
+}
+
+//
+// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
+//
+OperationRegion(SPRT,SystemIO, 0xB2,2)
+Field (SPRT, ByteAcc, Lock, Preserve) {
+  SSMP, 8
+}
+
+// The _PIC Control Method is optional for ACPI design.  It allows the
+// OS to inform the ASL code which interrupt controller is being used,
+// the 8259 or APIC.  The reference code in this document will address
+// PCI IRQ Routing and resource allocation for both cases.
+//
+// The values passed into _PIC are:
+//   0 = 8259
+//   1 = IOAPIC
+
+Method(\_PIC,1)
+{
+  Store(Arg0,GPIC)
+  Store(Arg0,PICM)
+}
+
+// Prepare to Sleep.  The hook is called when the OS is about to
+// enter a sleep state.  The argument passed is the numeric value of
+// the Sx state.
+
+Method(_PTS,1)
+{
+  Store(0,P80D)   // Zero out the entire Port 80h DWord.
+  D8XH(0,Arg0)    // Output Sleep State to Port 80h, Byte 0.
+
+  ADBG(Concatenate("_PTS=",ToHexString(Arg0)))
+
+
+  // If code is executed, Wake from RI# via Serial Modem will be
+  // enabled.  If code is not executed, COM Port Debugging throughout
+  // all Sx states will be enabled.
+
+  If(LEqual(Arg0,3))
+  {
+    //
+    // Disable update DTS temperature and threshold value in every SMI
+    //
+    If(CondRefOf(\_PR.DTSE)){
+      If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
+      {
+        TRAP(TRAP_TYPE_DTS,30)
+      }
+    }
+  }
+
+
+  // Generate a SW SMI trap to save some NVRAM data back to CMOS.
+
+  //  Don't enable IGD OpRegion support yet.
+  //  TRAP(1, 81)
+  //
+  // Call TPM.PTS
+  //
+  If(CondRefOf(\_SB.TPM.PTS))
+  {
+    //
+    // Call TPM PTS method
+    //
+    \_SB.TPM.PTS (Arg0)
+  }
+
+}
+
+// Wake.  This hook is called when the OS is about to wake from a
+// sleep state.  The argument passed is the numeric value of the
+// sleep state the system is waking from.
+
+Method(_WAK,1,Serialized)
+{
+  D8XH(1,0xAB)    // Beginning of _WAK.
+
+  ADBG("_WAK")
+
+  //
+  // Only set 8254 CG if Low Power S0 Idle Capability is enabled
+  //
+  If (LEqual(S0ID, One)) {
+    //
+    //  Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
+    //
+    Store(0x01, \_SB.SCGE)
+  }
+
+  If(NEXP)
+  {
+      // Reinitialize the Native PCI Express after resume
+
+    If(And(OSCC,0x02))
+    {
+      \_SB.PCI0.NHPG()
+    }
+    If(And(OSCC,0x04))  // PME control granted?
+    {
+      \_SB.PCI0.NPME()
+    }
+  }
+
+
+  If(LOr(LEqual(Arg0,3), LEqual(Arg0,4)))  // If S3 or S4 Resume
+  {
+
+    // Check to send Convertible/Dock state changes upon resume from Sx.
+    If(And(GBSX,0x40))
+    {
+      \_SB.PCI0.GFX0.IUEH(6)
+
+      //
+      //  Do the same thing for Virtul Button device.
+      //  Toggle Bit3 of PB1E(Slate/Notebook status)
+      //
+      Xor(PB1E, 0x08, PB1E)
+
+    }
+
+    If(And(GBSX,0x80))
+    {
+      \_SB.PCI0.GFX0.IUEH(7)
+
+      //
+      //  Do the same thing for Virtul Button device.
+      //  Toggle Bit4 of PB1E (Dock/Undock status)
+      //
+      Xor(PB1E, 0x10, PB1E)
+
+    }
+
+
+    If(CondRefOf(\_PR.DTSE)){
+      If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
+      {
+        TRAP(TRAP_TYPE_DTS, 20)
+      }
+    }
+
+
+    // For PCI Express Express Cards, it is possible a device was
+    // either inserted or removed during an Sx State.  The problem
+    // is that no wake event will occur for a given warm insertion
+    // or removal, so the OS will not become aware of any change.
+    // To get around this, re-enumerate all Express Card slots.
+    //
+    // If the Root Port is enabled, it may be assumed to be hot-pluggable.
+
+    If(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP01,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP02,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP03,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP04,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP05,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP06,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP07,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP08,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP09,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP10,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP11,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF))
+    {
+        Notify (\_SB.PCI0.RP12,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP13,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP14,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP15,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP16,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP17,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP18,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP19,0)
+    }
+
+    If(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF))
+    {
+      Notify (\_SB.PCI0.RP20,0)
+    }
+  }
+
+
+  Return(Package(){0,0})
+}
+
+// Get Buffer:
+//    This method will take a buffer passed into the method and
+//    create then return a smaller buffer based on the pointer
+//    and size parameters passed in.
+//
+//  Arguments:
+//    Arg0: Pointer to start of new Buffer in passed in Buffer.
+//    Arg1: Size of Buffer to create.
+//    Arg2: Original Buffer
+//
+//  Return Value:
+//    Newly created buffer.
+
+Method(GETB,3,Serialized)
+{
+  Multiply(Arg0,8,Local0)     // Convert Index.
+  Multiply(Arg1,8,Local1)     // Convert Size.
+  CreateField(Arg2,Local0,Local1,TBF3)  // Create Buffer.
+
+  Return(TBF3)        // Return Buffer.
+}
+
+// Power Notification:
+//    Perform all needed OS notifications during a
+//    Power Switch.
+//
+//  Arguments:
+//    None
+//
+//  Return Value:
+//    None
+
+Method(PNOT,0,Serialized)
+{
+  //
+  // If MP enabled and driver support is present, notify all
+  // processors.
+  //
+  If(LGreater(TCNT, 1))
+  {
+    If(And(\PC00,0x0008)){
+      Notify(\_PR.PR00,0x80)    // Eval PR00 _PPC.
+    }
+    If(And(\PC01,0x0008)){
+      Notify(\_PR.PR01,0x80)    // Eval PR01 _PPC.
+    }
+    If(And(\PC02,0x0008)){
+      Notify(\_PR.PR02,0x80)    // Eval PR02 _PPC.
+    }
+    If(And(\PC03,0x0008)){
+      Notify(\_PR.PR03,0x80)    // Eval PR03 _PPC.
+    }
+    If(And(\PC04,0x0008)){
+      Notify(\_PR.PR04,0x80)    // Eval PR04 _PPC.
+    }
+    If(And(\PC05,0x0008)){
+      Notify(\_PR.PR05,0x80)    // Eval PR05 _PPC.
+    }
+    If(And(\PC06,0x0008)){
+      Notify(\_PR.PR06,0x80)    // Eval PR06 _PPC.
+    }
+    If(And(\PC07,0x0008)){
+      Notify(\_PR.PR07,0x80)    // Eval PR07 _PPC.
+    }
+    If(And(\PC08,0x0008)){
+      Notify(\_PR.PR08,0x80)    // Eval PR08 _PPC.
+    }
+    If(And(\PC09,0x0008)){
+      Notify(\_PR.PR09,0x80)    // Eval PR09 _PPC.
+    }
+    If(And(\PC10,0x0008)){
+      Notify(\_PR.PR10,0x80)    // Eval PR10 _PPC.
+    }
+    If(And(\PC11,0x0008)){
+      Notify(\_PR.PR11,0x80)    // Eval PR11 _PPC.
+    }
+    If(And(\PC12,0x0008)){
+      Notify(\_PR.PR12,0x80)    // Eval PR12 _PPC.
+    }
+    If(And(\PC13,0x0008)){
+      Notify(\_PR.PR13,0x80)    // Eval PR13 _PPC.
+    }
+    If(And(\PC14,0x0008)){
+      Notify(\_PR.PR14,0x80)    // Eval PR14 _PPC.
+    }
+    If(And(\PC15,0x0008)){
+      Notify(\_PR.PR15,0x80)    // Eval PR15 _PPC.
+    }
+  }Else{
+    Notify(\_PR.PR00,0x80)      // Eval _PPC.
+  }
+
+  If(LGreater(TCNT, 1)){
+    If(LAnd(And(\PC00,0x0008),And(\PC00,0x0010))){
+      Notify(\_PR.PR00,0x81)  // Eval PR00 _CST.
+    }
+    If(LAnd(And(\PC01,0x0008),And(\PC01,0x0010))){
+      Notify(\_PR.PR01,0x81)  // Eval PR01 _CST.
+    }
+    If(LAnd(And(\PC02,0x0008),And(\PC02,0x0010))){
+      Notify(\_PR.PR02,0x81)  // Eval PR02 _CST.
+    }
+    If(LAnd(And(\PC03,0x0008),And(\PC03,0x0010))){
+      Notify(\_PR.PR03,0x81)  // Eval PR03 _CST.
+    }
+    If(LAnd(And(\PC04,0x0008),And(\PC04,0x0010))){
+      Notify(\_PR.PR04,0x81)  // Eval PR04 _CST.
+    }
+    If(LAnd(And(\PC05,0x0008),And(\PC05,0x0010))){
+      Notify(\_PR.PR05,0x81)  // Eval PR05 _CST.
+    }
+    If(LAnd(And(\PC06,0x0008),And(\PC06,0x0010))){
+      Notify(\_PR.PR06,0x81)  // Eval PR06 _CST.
+    }
+    If(LAnd(And(\PC07,0x0008),And(\PC07,0x0010))){
+      Notify(\_PR.PR07,0x81)  // Eval PR07 _CST.
+    }
+    If(LAnd(And(\PC08,0x0008),And(\PC08,0x0010))){
+      Notify(\_PR.PR08,0x81)  // Eval PR08 _CST.
+    }
+    If(LAnd(And(\PC09,0x0008),And(\PC09,0x0010))){
+      Notify(\_PR.PR09,0x81)  // Eval PR09 _CST.
+    }
+    If(LAnd(And(\PC10,0x0008),And(\PC10,0x0010))){
+      Notify(\_PR.PR10,0x81)  // Eval PR10 _CST.
+    }
+    If(LAnd(And(\PC11,0x0008),And(\PC11,0x0010))){
+      Notify(\_PR.PR11,0x81)  // Eval PR11 _CST.
+    }
+    If(LAnd(And(\PC12,0x0008),And(\PC12,0x0010))){
+      Notify(\_PR.PR12,0x81)  // Eval PR12 _CST.
+    }
+    If(LAnd(And(\PC13,0x0008),And(\PC13,0x0010))){
+      Notify(\_PR.PR13,0x81)  // Eval PR13 _CST.
+    }
+    If(LAnd(And(\PC14,0x0008),And(\PC14,0x0010))){
+      Notify(\_PR.PR14,0x81)  // Eval PR14 _CST.
+    }
+    If(LAnd(And(\PC15,0x0008),And(\PC15,0x0010))){
+      Notify(\_PR.PR15,0x81)  // Eval PR15 _CST.
+    }
+  } Else {
+    Notify(\_PR.PR00,0x81)      // Eval _CST.
+  }
+
+
+} // end of Method(PNOT)
+
+//
+// Memory window to the CTDP registers starting at MCHBAR+5000h.
+//
+  OperationRegion (MBAR, SystemMemory, Add(\_SB.PCI0.GMHB(),0x5000), 0x1000)
+  Field (MBAR, ByteAcc, NoLock, Preserve)
+  {
+    Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938)
+    PWRU,  4,       // Power Units [3:0] unit value is calculated by 1 W / Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W.
+    Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0)
+    PPL1, 15,       // PKG_PWR_LIM_1 [14:0]
+    PL1E,1,         // PKG_PWR_LIM1_EN [15]
+    CLP1,1,         // Package Clamping Limitation 1
+  }
+Name(CLMP, 0) // save the clamp bit
+Name(PLEN,0) // save the power limit enable bit
+Name(PLSV,0x8000) // save value of PL1 upon entering CS
+Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1.  SPL1/RPL1 must always be called in pairs, like push/pop off a stack
+//
+// SPL1 (Set PL1 to 4.5 watts with clamp bit set)
+//   Per Legacy Thermal management CS requirements, we would like to set the PL1 limit when entering CS to 4.5W with clamp bit set via MMIO.
+//   This can be done in the ACPI object which gets called by graphics driver during CS Entry.
+//   Likewise, during CS exit, the BIOS must reset the PL1 value to the previous value prior to CS entry and reset the clamp bit.
+//
+//  Arguments:
+//    None
+//
+//  Return Value:
+//    None
+Method(SPL1,0,Serialized)
+{
+    Name(PPUU,0) // units
+    If (LEqual(CSEM, 1))
+    {
+      Return() // we have already been called, must have CS exit before calling again
+    }
+    Store(1, CSEM) // record first call
+
+    Store (PPL1, PLSV) // save PL1 value upon entering CS
+    Store (PL1E, PLEN) // save PL1 Enable bit upon entering CS
+    Store (CLP1, CLMP) // save PL1 Clamp bit upon entering CS
+
+    If (LEqual(PWRU,0)) {  // use PACKAGE_POWER_SKU_UNIT - Power Units[3:0]
+      Store(1,PPUU)
+    } Else {
+      ShiftLeft(Decrement(PWRU),2,PPUU) // get units
+    }
+
+    Multiply(PLVL,PPUU,Local0)  // convert SETUP value to power units in milli-watts
+    Divide(Local0,1000,,Local1) // convert SETUP value to power units in watts
+    Store(Local1, PPL1)   // copy value to PL1
+    Store(1, PL1E)     // set Enable bit
+    Store(1, CLP1)     // set Clamp bit
+}
+//
+// RPL1 (Restore the PL1 register to the values prior to CS entry)
+//
+//  Arguments:
+//    None
+//
+//  Return Value:
+//    None
+Method(RPL1,0,Serialized)
+{
+    Store (PLSV, PPL1)  // restore value of PL1 upon exiting CS
+    Store(PLEN, PL1E)   // restore the PL1 enable bit
+    Store(CLMP, CLP1)   // restore the PL1 Clamp bit
+    Store(0, CSEM)      // restore semaphore
+}
+
+Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero - User not present
+Name(GLCK, 0) // a spin lock to avoid multi execution of GUAM
+// GUAM - Global User Absent Mode
+//    Run when a change to User Absent mode is made,  e.g. screen/display on/off events.
+//    Any device that needs notifications of these events includes its own UAMN Control Method.
+//
+//    Arguments:
+//      Power State:
+//        00h = On
+//        01h = Standby
+//        other value = do nothing & return
+//
+//    Return Value:
+//      None
+//
+Method(GUAM,1,Serialized)
+{
+  Switch(ToInteger(Arg0))
+  {
+    Case(0) // exit CS
+    {
+      If(LEqual(GLCK, 1)){
+        store(0, GLCK)
+
+        P8XH(0, 0xE1)
+        P8XH(1, 0xAB)
+        ADBG("Exit Resiliency")
+
+        // @Todo: Exit EC Low Power Mode here
+
+
+        If(PSCP){
+          // if P-state Capping s enabled
+          If (CondRefOf(\_PR.PR00._PPC))
+          {
+            Store(Zero, \_PR.CPPC)
+            PNOT()
+          }
+        }
+        If(PLCS){
+          RPL1() // restore PL1 to pre-CS value upon exiting CS
+        }
+      } // end GLCK=1
+    } // end case(0)
+
+    Case(1) // enter CS
+    {
+      If(LEqual(GLCK, 0)){
+        store(1, GLCK)
+
+        P8XH(0, 0xE0)
+        P8XH(1, 00)
+        ADBG("Enter Resiliency")
+
+        //@Todo: Enter EC Low Power Mode here
+
+
+        If(PSCP){
+          // if P-state Capping is enabled
+          If (LAnd(CondRefOf(\_PR.PR00._PSS), CondRefOf(\_PR.PR00._PPC)))
+          {
+            If(And(\PC00,0x0400))
+            {
+              Subtract(SizeOf(\_PR.PR00.TPSS), One, \_PR.CPPC)
+            } Else {
+              Subtract(SizeOf(\_PR.PR00.LPSS), One, \_PR.CPPC)
+            }
+            PNOT()
+          }
+        }
+        If(PLCS){
+          SPL1() // set PL1 to low value upon CS entry
+        }
+      } // end GLCK=0
+    } // end case(1)
+    Default{
+      Return()  // do nothing
+    }
+  } // end switch(arg0)
+
+  Store(LAnd(Arg0, LNot(PWRS)), UAMS)  // UAMS: User Absent Mode state, Zero - User Present; non-Zero - User not present
+  P_CS()                               // Powergating during CS
+
+} // end method GUAM()
+
+// Power CS Powergated Devices:
+//    Method to enable/disable power during CS
+Method(P_CS,0,Serialized)
+{
+    // NOTE: Do not turn ON Touch devices from here. Touch does not have PUAM
+    If(CondRefOf(\_SB.PCI0.PAUD.PUAM)){           // Notify Codec(HD-A/ADSP)
+        \_SB.PCI0.PAUD.PUAM()
+    }
+    // Adding back USB powergating (ONLY for Win8) until RTD3 walkup port setup implementation is complete */
+    If(LEqual(OSYS,2012)){    // ONLY for Win8 OS
+      If(CondRefOf(\_SB.PCI0.XHC.DUAM)){ // Notify USB port- RVP
+        \_SB.PCI0.XHC.DUAM()
+      }
+    }
+    // TODO: Add calls to UAMN methods for
+    //    * USB controller(s)
+    //    * Embedded Controller
+    //    * Sensor devices
+    //    * Audio DSP?
+    //    * Any other devices dependent on User Absent mode for power controls
+}
+
+// SMI I/O Trap:
+//    Generate a Mutex protected SMI I/O Trap.
+//
+//  Arguments:
+//    Arg0: I/O Trap type.
+//               2 - For DTS
+//               3 - For IGD
+//               4 - For BIOS Guard Tools
+//    Arg1: SMI I/O Trap Function to call.
+//
+//  Return Value:
+//    SMI I/O Trap Return value.
+//      0 = Success.  Non-zero = Failure.
+
+Scope(\)
+{
+  //
+  // The IO address in this ACPI Operating Region will be updated during POST.
+  // This address range is used as a HotKey I/O Trap SMI so that ASL and SMI can
+  // communicate when needed.
+  //
+  OperationRegion(IO_H,SystemIO,0x1000,0x4)
+  Field(IO_H,ByteAcc,NoLock,Preserve) {
+    TRPH,  8
+  }
+}
+
+Method(TRAP,2,Serialized)
+{
+  Store(Arg1,SMIF)        // Store SMI Function.
+
+  If(LEqual(Arg0,TRAP_TYPE_DTS))  // Is DTS IO Trap?
+  {
+    Store(Arg1,\_PR.DTSF)      // Store the function number global NVS
+    Store(0,\_PR.TRPD)         // Generate IO Trap.
+    Return(\_PR.DTSF)          // Return status from SMI handler
+  }
+
+  If(LEqual(Arg0,TRAP_TYPE_IGD))  // Is IGD IO Trap?
+  {
+    Store(0,TRPH)         // Generate IO Trap.
+  }
+
+  If(LEqual(Arg0,TRAP_TYPE_BGD))  // Is BIOS Guard TOOLS IO Trap?
+  {
+    Store(0,\_PR.TRPF)         // Generate IO Trap
+  }
+
+  Return(SMIF)            // Return SMIF.  0 = Success.
+}
+
+// Note:  Only add the indicator device needed by the platform.
+
+//
+// System Bus
+//
+Scope(\_SB.PCI0)
+{
+
+  Method(_INI,0, Serialized)
+  {
+
+    // Determine the OS and store the value, where:
+    //
+    //   OSYS = 1000 = Linux.
+    //   OSYS = 2000 = WIN2000.
+    //   OSYS = 2001 = WINXP, RTM or SP1.
+    //   OSYS = 2002 = WINXP SP2.
+    //   OSYS = 2006 = Vista.
+    //   OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
+    //   OSYS = 2012 = Windows 8 and Windows Server 2012.
+    //   OSYS = 2013 = Windows Blue.
+    //
+    // Assume Windows 2000 at a minimum.
+
+    Store(2000,OSYS)
+
+    // Check for a specific OS which supports _OSI.
+
+    If(CondRefOf(\_OSI))
+    {
+      If(\_OSI("Linux"))
+      {
+        Store(1000,OSYS)
+      }
+
+      If(\_OSI("Windows 2001")) // Windows XP
+      {
+        Store(2001,OSYS)
+      }
+
+      If(\_OSI("Windows 2001 SP1")) //Windows XP SP1
+      {
+        Store(2001,OSYS)
+      }
+
+      If(\_OSI("Windows 2001 SP2")) //Windows XP SP2
+      {
+        Store(2002,OSYS)
+      }
+
+      If (\_OSI( "Windows 2001.1"))  //Windows Server 2003
+      {
+        Store(2003,OSYS)
+      }
+
+      If(\_OSI("Windows 2006")) //Windows Vista
+      {
+        Store(2006,OSYS)
+      }
+
+      If(\_OSI("Windows 2009")) //Windows 7 and Windows Server 2008 R2
+      {
+        Store(2009,OSYS)
+      }
+
+      If(\_OSI("Windows 2012")) //Windows 8 and Windows Server 2012
+      {
+        Store(2012,OSYS)
+      }
+
+      If(\_OSI("Windows 2013")) //Windows 8.1 and Windows Server 2012 R2
+      {
+        Store(2013,OSYS)
+      }
+
+      If(\_OSI("Windows 2015")) //Windows 10
+      {
+        Store(2015,OSYS)
+      }
+    }
+
+    //
+    // Set DTS NVS data means in OS ACPI mode enabled insteads of GlobalNvs OperatingSystem (OSYS)
+    //
+    If(CondRefOf(\_PR.DTSE)){
+      If(LGreaterEqual(\_PR.DTSE, 0x01)){
+        Store(0x01, \_PR.DSAE)
+      }
+    }
+
+  }
+
+  Method(NHPG,0,Serialized)
+  {
+    Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP07.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP08.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP09.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP10.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP11.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP12.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP13.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP14.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP15.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP16.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP17.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP18.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP19.HPEX) // clear the hot plug SCI enable bit
+    Store(0,^RP20.HPEX) // clear the hot plug SCI enable bit
+
+    Store(1,^RP01.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP02.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP03.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP04.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP05.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP06.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP07.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP08.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP09.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP10.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP11.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP12.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP13.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP14.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP15.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP16.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP17.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP18.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP19.HPSX) // clear the hot plug SCI status bit
+    Store(1,^RP20.HPSX) // clear the hot plug SCI status bit
+  }
+
+  Method(NPME,0,Serialized)
+  {
+    Store(0,^RP01.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP02.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP03.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP04.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP05.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP06.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP07.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP08.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP09.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP10.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP11.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP12.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP13.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP14.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP15.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP16.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP17.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP18.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP19.PMEX) // clear the PME SCI enable bit
+    Store(0,^RP20.PMEX) // clear the PME SCI enable bit
+
+    Store(1,^RP01.PMSX) // clear the PME SCI status bit
+    Store(1,^RP02.PMSX) // clear the PME SCI status bit
+    Store(1,^RP03.PMSX) // clear the PME SCI status bit
+    Store(1,^RP04.PMSX) // clear the PME SCI status bit
+    Store(1,^RP05.PMSX) // clear the PME SCI status bit
+    Store(1,^RP06.PMSX) // clear the PME SCI enable bit
+    Store(1,^RP07.PMSX) // clear the PME SCI status bit
+    Store(1,^RP08.PMSX) // clear the PME SCI status bit
+    Store(1,^RP09.PMSX) // clear the PME SCI status bit
+    Store(1,^RP10.PMSX) // clear the PME SCI status bit
+    Store(1,^RP11.PMSX) // clear the PME SCI status bit
+    Store(1,^RP12.PMSX) // clear the PME SCI status bit
+    Store(1,^RP13.PMSX) // clear the PME SCI status bit
+    Store(1,^RP14.PMSX) // clear the PME SCI status bit
+    Store(1,^RP15.PMSX) // clear the PME SCI status bit
+    Store(1,^RP16.PMSX) // clear the PME SCI status bit
+    Store(1,^RP17.PMSX) // clear the PME SCI status bit
+    Store(1,^RP18.PMSX) // clear the PME SCI status bit
+    Store(1,^RP19.PMSX) // clear the PME SCI status bit
+    Store(1,^RP20.PMSX) // clear the PME SCI status bit
+  }
+}
+
+Scope (\)
+{
+  //
+  // Global Name, returns current Interrupt controller mode;
+  // updated from _PIC control method
+  //
+  Name(PICM, 0)
+
+  //
+  // Procedure: GPRW
+  //
+  // Description: Generic Wake up Control Method ("Big brother")
+  //              to detect the Max Sleep State available in ASL Name scope
+  //              and Return the Package compatible with _PRW format.
+  // Input: Arg0 =  bit offset within GPE register space device event will be triggered to.
+  //        Arg1 =  Max Sleep state, device can resume the System from.
+  //                If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
+  // Output:  _PRW package
+  //
+  Name(PRWP, Package(){Zero, Zero})   // _PRW Package
+
+  Method(GPRW, 2)
+  {
+    Store(Arg0, Index(PRWP, 0))             // copy GPE#
+    //
+    // SS1-SS4 - enabled in BIOS Setup Sleep states
+    //
+    Store(ShiftLeft(SS1,1),Local0)          // S1 ?
+    Or(Local0,ShiftLeft(SS2,2),Local0)      // S2 ?
+    Or(Local0,ShiftLeft(SS3,3),Local0)      // S3 ?
+    Or(Local0,ShiftLeft(SS4,4),Local0)      // S4 ?
+    //
+    // Local0 has a bit mask of enabled Sx(1 based)
+    // bit mask of enabled in BIOS Setup Sleep states(1 based)
+    //
+    If(And(ShiftLeft(1, Arg1), Local0))
+    {
+      //
+      // Requested wake up value (Arg1) is present in Sx list of available Sleep states
+      //
+      Store(Arg1, Index(PRWP, 1))           // copy Sx#
+    }
+    Else
+    {
+      //
+      // Not available -> match Wake up value to the higher Sx state
+      //
+      ShiftRight(Local0, 1, Local0)
+      // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) {  // ??? Win9x
+      // FindSetLeftBit(Local0, Index(PRWP,1))  // Arg1 == Max Sx
+      // } Else {           // ??? Win2k / XP
+     FindSetLeftBit(Local0, Index(PRWP,1))  // Arg1 == Min Sx
+      // }
+    }
+
+    Return(PRWP)
+  }
+}
+
+
+Scope (\_SB)
+{
+  Name(OSCI, 0)  // \_SB._OSC DWORD2 input
+  Name(OSCO, 0)  // \_SB._OSC DWORD2 output
+  Name(OSCP, 0)  // \_SB._OSC CAPABILITIES
+  // _OSC (Operating System Capabilities)
+  //    _OSC under \_SB scope is used to convey platform wide OSPM capabilities.
+  //    For a complete description of _OSC ACPI Control Method, refer to ACPI 5.0
+  //    specification, section 6.2.10.
+  // Arguments: (4)
+  //    Arg0 - A Buffer containing the UUID "0811B06E-4A27-44F9-8D60-3CBBC22E7B48"
+  //    Arg1 - An Integer containing the Revision ID of the buffer format
+  //    Arg2 - An Integer containing a count of entries in Arg3
+  //    Arg3 - A Buffer containing a list of DWORD capabilities
+  // Return Value:
+  //    A Buffer containing the list of capabilities
+  //
+  Method(_OSC,4,Serialized)
+  {
+    //
+    // Point to Status DWORD in the Arg3 buffer (STATUS)
+    //
+    CreateDWordField(Arg3, 0, STS0)
+    //
+    // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
+    //
+    CreateDwordField(Arg3, 4, CAP0)
+
+
+    //
+    // Only set 8254 CG if Low Power S0 Idle Capability is enabled
+    //
+    If (LEqual(S0ID, One)) {
+      //
+      //  Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
+      //
+      Store(0x01, \_SB.SCGE)
+    }
+
+    //
+    // Check UUID
+    //
+    If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+    {
+      //
+      // Check Revision
+      //
+      If(LEqual(Arg1,One))
+      {
+        Store(CAP0, OSCP)
+        If(And(CAP0,0x04)) // Check _PR3 Support(BIT2)
+        {
+          Store(0x04, OSCO)
+          If(LNotEqual(And(SGMD,0x0F),2)) // Check Switchable/Hybrid graphics is not enabled in bios setup [SgModeMuxless]?
+          {
+            If(LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup?
+            {
+              // RTD3 is disabled via BIOS Setup.
+              And(CAP0, 0x3B, CAP0) // Clear _PR3 capability
+              Or(STS0, 0x10, STS0) // Indicate capability bit is cleared
+            }
+          }
+        }
+      } Else{
+        And(STS0,0xFFFFFF00,STS0)
+        Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC failure
+      }
+    } Else {
+      And(STS0,0xFFFFFF00,STS0)
+      Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure
+    }
+
+    Return(Arg3)
+  } // End _OSC
+
+} // End of Scope(\_SB)
+
+//
+// CS Wake up event support
+//
+Scope (\_SB)
+{
+  // Define Sleep button to put the system in sleep
+  Device (SLPB)
+  {
+    Name (_HID, EISAID ("PNP0C0E"))
+    Name (_STA, 0x0B)
+    // Bit0 - the device is present: Yes.
+    // Bit1 - the device is enabled and decoding its resources: Yes.
+    // Bit2 - the device should be shown in the UI: No.
+    // Bit3 - the device is functioning properly: Yes.
+    // Bit4 - the battery is present: N/A
+  }
+} // End of Scope(\_SB)

+ 14 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl

@@ -0,0 +1,14 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+

+ 35 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl

@@ -0,0 +1,35 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+External(DIDX)
+
+// Brightness Notification:
+//    Generate a brightness related notification
+//      to the LFP if its populated.
+//
+//  Arguments:
+//    Arg0: Notification value.
+//
+//  Return Value:
+//    None
+
+Method(BRTN,1,Serialized)
+{
+    If(LEqual(And(DIDX,0x0F00),0x400))
+    {
+        Notify(\_SB.PCI0.GFX0.DD1F,Arg0)
+    }
+}

+ 782 - 0
Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c

@@ -0,0 +1,782 @@
+/** @file
+  Acpi Gnvs Init Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/GlobalNvsArea.h>
+extern GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL              mGlobalNvsArea;
+
+VOID
+UpdateDsdt (
+  IN VOID   *Table
+  )
+{
+  UINT8   *CurrPtr;
+  UINT8   *TmpDsdtPointer;
+  UINT8   *DsdtPointer;
+  UINT32  *Signature;
+  UINT8   *Operation;
+  UINT32  *Address;
+  UINT8   *Value;
+  UINT16  *Size;
+  BOOLEAN EnterDock = FALSE;
+
+  UINT8   MaximumDsdtPointLength;
+
+  MaximumDsdtPointLength = 20;
+
+    //
+    // Fix up the AML code in the DSDT affected by end user options.
+    // Fix up the following ASL Code:
+    // (1)  ACPI Global NVS Memory Base and Size.
+    // (2)  ACPI Graphics NVS Memory Base and Size.
+    // (3)  SMBus I/O Base.
+    // (4)  Thermal Management Methods.
+    //
+      //
+      // Loop through the ASL looking for values that we must fix up.
+      //
+      CurrPtr = (UINT8 *) Table;
+      for (DsdtPointer = CurrPtr;
+           DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
+           DsdtPointer++
+          ) {
+        Signature = (UINT32 *) DsdtPointer;
+        switch (*Signature) {
+        //
+        // GNVS operation region
+        //
+        case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
+          //
+          // Conditional match.  For Region Objects, the Operator will always be the
+          // byte immediately before the specific name.  Therefore, subtract 1 to check
+          // the Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_EXT_REGION_OP) {
+            Address   = (UINT32 *) (DsdtPointer + 6);
+            *Address  = (UINT32) (UINTN) mGlobalNvsArea.Area;
+            Size      = (UINT16 *) (DsdtPointer + 11);
+            *Size     = sizeof (EFI_GLOBAL_NVS_AREA);
+          }
+          break;
+
+        //
+        // _AC0 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '0')):
+          //
+          // Conditional match.  _AC0 is >63 and <4095 bytes, so the package length is 2 bytes.
+          // Therefore, subtract 3 to check the Operator.
+          //
+          Operation = DsdtPointer - 3;
+          if (*Operation == AML_METHOD_OP) {
+            //
+            // Check if we want _AC0 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '0');
+            }
+          }
+          break;
+
+        //
+        // _AL0 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '0')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL0 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '0');
+            }
+          }
+          break;
+
+        //
+        // _AC1 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '1')):
+          //
+          // Conditional match.  _AC1 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC1 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '1');
+            }
+          }
+          break;
+
+        //
+        // _AL1 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '1')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL1 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '1');
+            }
+          }
+          break;
+
+        //
+        // _AC2 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '2')):
+          //
+          // Conditional match.  _AC2 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC2 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '2');
+            }
+          }
+          break;
+
+        //
+        // _AL2 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '2')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL2 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '2');
+            }
+          }
+          break;
+
+        //
+        // _AC3 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '3')):
+          //
+          // Conditional match.  _AC3 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC3 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '3');
+            }
+          }
+          break;
+
+        //
+        // _AL3 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '3')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL3 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '3');
+            }
+          }
+          break;
+
+        //
+        // _AC4 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '4')):
+          //
+          // Conditional match.  _AC4 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC4 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '4');
+            }
+          }
+          break;
+
+        //
+        // _AL4 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '4')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL4 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '4');
+            }
+          }
+          break;
+
+        //
+        // _AC5 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '5')):
+          //
+          // Conditional match.  _AC5 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC5 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '5');
+            }
+          }
+          break;
+
+        //
+        // _AL5 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '5')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL5 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '5');
+            }
+          }
+          break;
+
+        //
+        // _AC6 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '6')):
+          //
+          // Conditional match.  _AC6 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC6 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '6');
+            }
+          }
+          break;
+
+        //
+        // _AL6 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '6')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL6 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '6');
+            }
+          }
+          break;
+
+        //
+        // _AC7 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '7')):
+          //
+          // Conditional match.  _AC7 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC7 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '7');
+            }
+          }
+          break;
+
+        //
+        // _AL7 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '7')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL7 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '7');
+            }
+          }
+          break;
+
+        //
+        // _AC8 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '8')):
+          //
+          // Conditional match.  _AC8 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC8 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '8');
+            }
+          }
+          break;
+
+        //
+        // _AL8 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '8')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL8 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '8');
+            }
+          }
+          break;
+
+        //
+        // _AC9 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'C', '9')):
+          //
+          // Conditional match.  _AC9 is < 63 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _AC9 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'C', '9');
+            }
+          }
+          break;
+
+        //
+        // _AL9 method
+        //
+        case (SIGNATURE_32 ('_', 'A', 'L', '9')):
+          //
+          // Conditional match.  For Name Objects, the Operator will always be the byte
+          // immediately before the specific name. Therefore, subtract 1 to check the
+          // Operator.
+          //
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+
+            //
+            // Check if we want _AL9 enabled
+            //
+            if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'A', 'L', '9');
+            }
+          }
+          break;
+
+        //
+        // _PSL method
+        //
+        case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
+          //
+          // Conditional match.  _PSL is < 256 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 3;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _PSL enabled
+            //
+            if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'P', 'S', 'L');
+            }
+          }
+          break;
+
+        //
+        // _PSV method
+        //
+        case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
+          //
+          // Conditional match.  _PSV is < 256 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 3;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _PSV enabled
+            //
+            if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'P', 'S', 'V');
+            }
+          }
+          break;
+
+        //
+        // _CRT method
+        //
+        case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
+          //
+          // Conditional match.  _CRT is < 256 bytes, so the package length is 1 byte.
+          // Subtract 3 to check the Operator for CRB, subract 2 for Harris Beach.
+          //
+          Operation = DsdtPointer - 3;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _CRT enabled
+            //
+            if (PcdGet8 (PcdDisableCriticalTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'C', 'R', 'T');
+            }
+          }
+          break;
+
+        //
+        // _TC1 method
+        //
+        case (SIGNATURE_32 ('_', 'T', 'C', '1')):
+          //
+          // Conditional match.  _TC1 is < 256 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _TC1 enabled
+            //
+            if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'T', 'C', '1');
+            }
+          }
+          break;
+
+        //
+        // _TC2 method
+        //
+        case (SIGNATURE_32 ('_', 'T', 'C', '2')):
+          //
+          // Conditional match.  _TC2 is < 256 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _TC2 enabled
+            //
+            if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'T', 'C', '2');
+            }
+          }
+          break;
+
+        //
+        // _TSP method
+        //
+        case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
+          //
+          // Conditional match.  _TSP is < 256 bytes, so the package length is 1 byte.
+          // Therefore, subtract 2 to check the Operator.
+          //
+          Operation = DsdtPointer - 2;
+          if (*Operation == AML_METHOD_OP) {
+
+            //
+            // Check if we want _TSP enabled
+            //
+            if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'T', 'S', 'P');
+            }
+          }
+          break;
+
+        //
+        // Update SS3 Name with Setup value
+        //
+        case (SIGNATURE_32 ('S', 'S', '3', '_')):
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+            Value   = (UINT8 *) DsdtPointer + 4;
+            *Value  = PcdGet8 (PcdAcpiSleepState);
+          }
+          break;
+        //
+        // Update SS4 Name with Setup value
+        //
+        case (SIGNATURE_32 ('S', 'S', '4', '_')):
+          Operation = DsdtPointer - 1;
+          if (*Operation == AML_NAME_OP) {
+            Value   = (UINT8 *) DsdtPointer + 4;
+            *Value  = PcdGet8 (PcdAcpiHibernate);
+          }
+          break;
+        //
+        // _EJ0 method
+        //
+        case (SIGNATURE_32 ('_', 'E', 'J', '0')):
+          if (PcdGet8 (PcdLowPowerS0Idle)) {
+            //
+            // Remove _EJ0 for SOC
+            //
+            if (*(DsdtPointer-3) == AML_METHOD_OP) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'E', 'J', '0');
+              EnterDock = TRUE;
+            }
+          }
+          break;
+        //
+        // _STA method for Device (\_SB.PCI0.DOCK)
+        //
+        case (SIGNATURE_32 ('_', 'S', 'T', 'A')):
+          if (PcdGet8 (PcdLowPowerS0Idle)) {
+            //
+            // Remove _STA in (\_SB.PCI0.DOCK) for SOC
+            //
+            if ((*(DsdtPointer-3) == AML_METHOD_OP) && (EnterDock)) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'S', 'T', 'A');
+              EnterDock = FALSE;
+            }
+          }
+          break;
+        //
+        // _UPC method for Device (\_SB.PCI0.XHC.RHUB)
+        //
+        case (SIGNATURE_32('H', 'S', '1', '3')):
+          for (TmpDsdtPointer = DsdtPointer;
+               TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength;
+               TmpDsdtPointer++){
+            Signature = (UINT32 *) TmpDsdtPointer;
+            switch (*Signature) {
+              case(SIGNATURE_32('U', 'P', 'C', 'P')):
+                Value   = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
+                break;
+              default:
+                //
+                // Do nothing.
+                //
+                break;
+            }
+          }
+        break;
+
+
+        //
+        // _DCK method
+        //
+        case (SIGNATURE_32 ('_', 'D', 'C', 'K')):
+          if (PcdGet8 (PcdLowPowerS0Idle)) {
+            //
+            // Remove _DCK for SOC
+            //
+            if (*(DsdtPointer-3) == AML_METHOD_OP) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'D', 'C', 'K');
+            }
+          }
+          break;
+
+        //
+        // mask _DEP from CPU's scope if CS disabled.
+        //
+        case (SIGNATURE_32 ('P', 'R', '0', '0')):
+        case (SIGNATURE_32 ('P', 'R', '0', '1')):
+        case (SIGNATURE_32 ('P', 'R', '0', '2')):
+        case (SIGNATURE_32 ('P', 'R', '0', '3')):
+        case (SIGNATURE_32 ('P', 'R', '0', '4')):
+        case (SIGNATURE_32 ('P', 'R', '0', '5')):
+        case (SIGNATURE_32 ('P', 'R', '0', '6')):
+        case (SIGNATURE_32 ('P', 'R', '0', '7')):
+        case (SIGNATURE_32 ('P', 'R', '0', '8')):
+        case (SIGNATURE_32 ('P', 'R', '0', '9')):
+        case (SIGNATURE_32 ('P', 'R', '1', '0')):
+        case (SIGNATURE_32 ('P', 'R', '1', '1')):
+        case (SIGNATURE_32 ('P', 'R', '1', '2')):
+        case (SIGNATURE_32 ('P', 'R', '1', '3')):
+        case (SIGNATURE_32 ('P', 'R', '1', '4')):
+        case (SIGNATURE_32 ('P', 'R', '1', '5')):
+
+          if (PcdGet8 (PcdLowPowerS0Idle) == 0) {
+            for (TmpDsdtPointer = DsdtPointer; TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength; TmpDsdtPointer++){
+              Signature = (UINT32 *) TmpDsdtPointer;
+              switch (*Signature) {
+                case(SIGNATURE_32('_', 'D', 'E', 'P')):
+                  *(UINT8 *) TmpDsdtPointer = 'X';
+                  break;
+                default:
+                  //
+                  // Do nothing.
+                  //
+                  break;
+              }
+            }
+          }
+          break;
+
+        //
+        // _EDL name
+        //
+        case (SIGNATURE_32 ('_', 'E', 'D', 'L')):
+          if (PcdGet8 (PcdLowPowerS0Idle)) {
+            //
+            // Remove _EDL for SOC
+            //
+            if (*(DsdtPointer-1) == AML_NAME_OP) {
+              Signature   = (UINT32 *) DsdtPointer;
+              *Signature  = SIGNATURE_32 ('X', 'E', 'D', 'L');
+            }
+          }
+          break;
+
+        default:
+          //
+          // Do nothing.
+          //
+          break;
+        }
+      }
+}
+

+ 218 - 0
Platform/Intel/KabylakeOpenBoardPkg/Contributions.txt

@@ -0,0 +1,218 @@
+
+======================
+= Code Contributions =
+======================
+
+To make a contribution to a TianoCore project, follow these steps.
+1. Create a change description in the format specified below to
+   use in the source control commit log.
+2. Your commit message must include your "Signed-off-by" signature,
+   and "Contributed-under" message.
+3. Your "Contributed-under" message explicitly states that the
+   contribution is made under the terms of the specified
+   contribution agreement.  Your "Contributed-under" message
+   must include the name of contribution agreement and version.
+   For example: Contributed-under: TianoCore Contribution Agreement 1.0
+   The "TianoCore Contribution Agreement" is included below in
+   this document.
+4. Submit your code to the TianoCore project using the process
+   that the project documents on its web page.  If the process is
+   not documented, then submit the code on development email list
+   for the project.
+5. It is preferred that contributions are submitted using the same
+   copyright license as the base project. When that is not possible,
+   then contributions using the following licenses can be accepted:
+   * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
+   * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
+   * MIT: http://opensource.org/licenses/MIT
+   * Python-2.0: http://opensource.org/licenses/Python-2.0
+   * Zlib: http://opensource.org/licenses/Zlib
+
+   Contributions of code put into the public domain can also be
+   accepted.
+
+   Contributions using other licenses might be accepted, but further
+   review will be required.
+
+=====================================================
+= Change Description / Commit Message / Patch Email =
+=====================================================
+
+Your change description should use the standard format for a
+commit message, and must include your "Signed-off-by" signature
+and the "Contributed-under" message.
+
+== Sample Change Description / Commit Message =
+
+=== Start of sample patch email message ===
+
+From: Contributor Name <contributor@example.com>
+Subject: [PATCH] CodeModule: Brief-single-line-summary
+
+Full-commit-message
+
+Contributed-under: TianoCore Contribution Agreement 1.0
+Signed-off-by: Contributor Name <contributor@example.com>
+---
+
+An extra message for the patch email which will not be considered part
+of the commit message can be added here.
+
+Patch content inline or attached
+
+=== End of sample patch email message ===
+
+=== Notes for sample patch email ===
+
+* The first line of commit message is taken from the email's subject
+  line following [PATCH]. The remaining portion of the commit message
+  is the email's content until the '---' line.
+* git format-patch is one way to create this format
+
+=== Definitions for sample patch email ===
+
+* "CodeModule" is a short idenfier for the affected code.  For
+  example MdePkg, or MdeModulePkg UsbBusDxe.
+* "Brief-single-line-summary" is a short summary of the change.
+* The entire first line should be less than ~70 characters.
+* "Full-commit-message" a verbose multiple line comment describing
+  the change.  Each line should be less than ~70 characters.
+* "Contributed-under" explicitely states that the contribution is
+  made under the terms of the contribtion agreement.  This
+  agreement is included below in this document.
+* "Signed-off-by" is the contributor's signature identifying them
+  by their real/legal name and their email address.
+
+========================================
+= TianoCore Contribution Agreement 1.0 =
+========================================
+
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
+TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
+REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
+BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
+AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
+AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
+USE THE CONTENT.
+
+Unless otherwise indicated, all Content made available on the TianoCore
+site is provided to you under the terms and conditions of the BSD
+License ("BSD"). A copy of the BSD License is available at
+http://opensource.org/licenses/bsd-license.php
+or when applicable, in the associated License.txt file.
+
+Certain other content may be made available under other licenses as
+indicated in or with such Content. (For example, in a License.txt file.)
+
+You accept and agree to the following terms and conditions for Your
+present and future Contributions submitted to TianoCore site. Except
+for the license granted to Intel hereunder, You reserve all right,
+title, and interest in and to Your Contributions.
+
+== SECTION 1: Definitions ==
+* "You" or "Contributor" shall mean the copyright owner or legal
+  entity authorized by the copyright owner that is making a
+  Contribution hereunder. All other entities that control, are
+  controlled by, or are under common control with that entity are
+  considered to be a single Contributor. For the purposes of this
+  definition, "control" means (i) the power, direct or indirect, to
+  cause the direction or management of such entity, whether by
+  contract or otherwise, or (ii) ownership of fifty percent (50%)
+  or more of the outstanding shares, or (iii) beneficial ownership
+  of such entity.
+* "Contribution" shall mean any original work of authorship,
+  including any modifications or additions to an existing work,
+  that is intentionally submitted by You to the TinaoCore site for
+  inclusion in, or documentation of, any of the Content. For the
+  purposes of this definition, "submitted" means any form of
+  electronic, verbal, or written communication sent to the
+  TianoCore site or its representatives, including but not limited
+  to communication on electronic mailing lists, source code
+  control systems, and issue tracking systems that are managed by,
+  or on behalf of, the TianoCore site for the purpose of
+  discussing and improving the Content, but excluding
+  communication that is conspicuously marked or otherwise
+  designated in writing by You as "Not a Contribution."
+
+== SECTION 2: License for Contributions ==
+* Contributor hereby agrees that redistribution and use of the
+  Contribution in source and binary forms, with or without
+  modification, are permitted provided that the following
+  conditions are met:
+** Redistributions of source code must retain the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer.
+** Redistributions in binary form must reproduce the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer in the documentation and/or other materials provided
+   with the distribution.
+* Disclaimer. None of the names of Contributor, Intel, or the names
+  of their respective contributors may be used to endorse or
+  promote products derived from this software without specific
+  prior written permission.
+* Contributor grants a license (with the right to sublicense) under
+  claims of Contributor's patents that Contributor can license that
+  are infringed by the Contribution (as delivered by Contributor) to
+  make, use, distribute, sell, offer for sale, and import the
+  Contribution and derivative works thereof solely to the minimum
+  extent necessary for licensee to exercise the granted copyright
+  license; this patent license applies solely to those portions of
+  the Contribution that are unmodified. No hardware per se is
+  licensed.
+* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
+  CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
+  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+  CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
+  CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+  DAMAGE.
+
+== SECTION 3: Representations ==
+* You represent that You are legally entitled to grant the above
+  license. If your employer(s) has rights to intellectual property
+  that You create that includes Your Contributions, You represent
+  that You have received permission to make Contributions on behalf
+  of that employer, that Your employer has waived such rights for
+  Your Contributions.
+* You represent that each of Your Contributions is Your original
+  creation (see Section 4 for submissions on behalf of others).
+  You represent that Your Contribution submissions include complete
+  details of any third-party license or other restriction
+  (including, but not limited to, related patents and trademarks)
+  of which You are personally aware and which are associated with
+  any part of Your Contributions.
+
+== SECTION 4: Third Party Contributions ==
+* Should You wish to submit work that is not Your original creation,
+  You may submit it to TianoCore site separately from any
+  Contribution, identifying the complete details of its source
+  and of any license or other restriction (including, but not
+  limited to, related patents, trademarks, and license agreements)
+  of which You are personally aware, and conspicuously marking the
+  work as "Submitted on behalf of a third-party: [named here]".
+
+== SECTION 5: Miscellaneous ==
+* Applicable Laws. Any claims arising under or relating to this
+  Agreement shall be governed by the internal substantive laws of
+  the State of Delaware or federal courts located in Delaware,
+  without regard to principles of conflict of laws.
+* Language. This Agreement is in the English language only, which
+  language shall be controlling in all respects, and all versions
+  of this Agreement in any other language shall be for accommodation
+  only and shall not be binding. All communications and notices made
+  or given pursuant to this Agreement, and all documentation and
+  support to be provided, unless otherwise noted, shall be in the
+  English language.
+

+ 121 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PcieDeviceTable.c

@@ -0,0 +1,121 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+
+#define PCI_CLASS_NETWORK             0x02
+#define PCI_CLASS_NETWORK_ETHERNET    0x00
+#define PCI_CLASS_NETWORK_OTHER       0x80
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
+  //
+  // Intel PRO/Wireless
+  //
+  { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel WiMAX/WiFi Link
+  //
+  { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Crane Peak WLAN NIC
+  //
+  { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Crane Peak w/BT WLAN NIC
+  //
+  { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Kelsey Peak WiFi, WiMax
+  //
+  { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 105
+  //
+  { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 135
+  //
+  { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 2200
+  //
+  { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 2230
+  //
+  { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 6235
+  //
+  { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel CampPeak 2 Wifi
+  //
+  { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel WilkinsPeak 1 Wifi
+  //
+  { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  //
+  // Intel Wilkins Peak 2 Wifi
+  //
+  { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  //
+  // Intel Wilkins Peak PF Wifi
+  //
+  { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+
+  //
+  // End of Table
+  //
+  { 0 }
+};
+

+ 83 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspMiscUpdUpdateLib.c

@@ -0,0 +1,83 @@
+/** @file
+  Implementation of Fsp Misc UPD Initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeiLib.h>
+#include <Library/ConfigBlockLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Guid/MemoryOverwriteControl.h>
+
+/**
+  Performs FSP Misc UPD initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSPM_UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                        Status;
+  UINTN                             VariableSize;
+  VOID                              *MemorySavedData;
+  UINT8                             MorControl;
+  VOID                              *MorControlPtr;
+
+  //
+  // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
+  //
+  VariableSize = 0;
+  MemorySavedData = NULL;
+  Status = PeiGetVariable (
+             L"MemoryConfig",
+             &gFspNonVolatileStorageHobGuid,
+             &MemorySavedData,
+             &VariableSize
+             );
+  DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status));
+  DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));
+  FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
+
+  //
+  // MOR
+  //
+  MorControl = 0;
+  MorControlPtr = &MorControl;
+  VariableSize = sizeof (MorControl);
+  Status = PeiGetVariable (
+             MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+             &gEfiMemoryOverwriteControlDataGuid,
+             &MorControlPtr,
+             &VariableSize
+             );
+  DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
+  if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+    FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
+  }
+
+  return EFI_SUCCESS;
+}
+

+ 148 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.c

@@ -0,0 +1,148 @@
+/** @file
+  Provide FSP wrapper platform related function.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/FspPolicyUpdateLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+/**
+  Performs FSP Misc UPD initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSPM_UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+  Performs FSP PCH PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+  Performs FSP PCH PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+  IN OUT FSPS_UPD    *FspsUpd
+  );
+
+/**
+  Performs FSP SA PEI Policy initialization in pre-memory.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+  Performs FSP SA PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdate (
+  IN OUT FSPS_UPD    *FspsUpd
+  );
+
+VOID
+InternalPrintVariableData (
+  IN UINT8   *Data8,
+  IN UINTN   DataSize
+  )
+{
+  UINTN      Index;
+
+  for (Index = 0; Index < DataSize; Index++) {
+    if (Index % 0x10 == 0) {
+      DEBUG ((DEBUG_INFO, "\n%08X:", Index));
+    }
+    DEBUG ((DEBUG_INFO, " %02X", *Data8++));
+  }
+  DEBUG ((DEBUG_INFO, "\n"));
+}
+
+VOID
+EFIAPI
+FspmPolicyUpdate (
+  IN OUT VOID    *FspmUpd
+  )
+{
+  FSPM_UPD              *FspmUpdDataPtr;
+
+  FspmUpdDataPtr = FspmUpd;
+  PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);
+  PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr);
+  PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
+
+  InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD));
+}
+
+VOID
+EFIAPI
+FspsPolicyUpdate (
+  IN OUT VOID    *FspsUpd
+  )
+{
+  FSPS_UPD              *FspsUpdDataPtr;
+
+  FspsUpdDataPtr = FspsUpd;
+  PeiFspSaPolicyUpdate (FspsUpdDataPtr);
+  PeiFspPchPolicyUpdate (FspsUpdDataPtr);
+  
+  InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD));
+}
+
+

+ 144 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf

@@ -0,0 +1,144 @@
+## @file
+#  Provide FSP wrapper platform related function.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiFspPolicyUpdateLib
+  FILE_GUID                      = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = FspPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+  PeiFspPolicyUpdateLib.c
+  PeiPchPolicyUpdatePreMem.c
+  PeiPchPolicyUpdate.c
+  PeiSaPolicyUpdatePreMem.c
+  PeiSaPolicyUpdate.c
+  PeiFspMiscUpdUpdateLib.c
+  PcieDeviceTable.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+#                              this module.
+#
+################################################################################
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelFsp2Pkg/IntelFsp2Pkg.dec
+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+  KabylakeFspBinPkg/KabylakeFspBinPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses.IA32]
+  FspWrapperApiLib
+  OcWdtLib
+  PchResetLib
+  FspWrapperPlatformResetLib
+  BaseMemoryLib
+  CpuPlatformLib
+  DebugLib
+  HobLib
+  IoLib
+  PcdLib
+  PostCodeLib
+  SmbusLib
+  MmPciLib
+  ConfigBlockLib
+  PeiSaPolicyLib
+  PchGbeLib
+  PchInfoLib
+  PchHsioLib
+  PchPcieRpLib
+  MemoryAllocationLib
+  CpuMailboxLib
+  DebugPrintErrorLevelLib
+  SiPolicyLib
+  PchGbeLib
+  TimerLib
+  GpioLib
+  PeiLib
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor       ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget         ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram      ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress      ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable        ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber             ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi                   ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit           ## CONSUMES
+  
+  gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
+  gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
+  gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
+  gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+  gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+  gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+  gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+  gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+  gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1
+  gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2
+  gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
+  gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
+
+  gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
+  gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2
+  gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable
+  gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1
+  gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2
+  gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3
+  gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable
+
+  gBoardModuleTokenSpaceGuid.PcdAudioConnector
+
+[Guids]
+  gFspNonVolatileStorageHobGuid                 ## CONSUMES
+  gIntelPeiGraphicsVbtGuid                      ## CONSUMES
+  gTianoLogoGuid                                ## CONSUMES
+  gEfiMemoryOverwriteControlDataGuid
+

+ 159 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.c

@@ -0,0 +1,159 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+
+extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[];
+
+/**
+  Add verb table helper function.
+  This function calculates verbtable number and shows verb table information.
+
+  @param[in,out] VerbTableEntryNum      Input current VerbTable number and output the number after adding new table
+  @param[in,out] VerbTableArray         Pointer to array of VerbTable
+  @param[in]     VerbTable              VerbTable which is going to add into array
+**/
+STATIC
+VOID
+InternalAddVerbTable (
+  IN OUT  UINT8                   *VerbTableEntryNum,
+  IN OUT  UINT32                  *VerbTableArray,
+  IN      HDAUDIO_VERB_TABLE      *VerbTable
+  )
+{
+  if (VerbTable == NULL) {
+    DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable == NULL\n"));
+    return;
+  }
+
+  VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable;
+  *VerbTableEntryNum += 1;
+
+  DEBUG ((DEBUG_INFO,
+    "Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n",
+    VerbTable->Header.VendorId,
+    VerbTable->Header.DeviceId,
+    VerbTable->Header.DataDwords)
+    );
+}
+
+enum HDAUDIO_CODEC_SELECT {
+  PchHdaCodecPlatformOnboard = 0,
+  PchHdaCodecExternalKit     = 1
+};
+
+/**
+  Add verb table function.
+  This function update the verb table number and verb table ptr of policy.
+
+  @param[in] HdAudioConfig            HDAudie config block
+  @param[in] CodecType                Platform codec type indicator
+  @param[in] AudioConnectorType       Platform audio connector type
+**/
+STATIC
+VOID
+InternalAddPlatformVerbTables (
+  IN OUT FSPS_UPD                     *FspsUpd,
+  IN  UINT8                           CodecType,
+  IN  UINT8                           AudioConnectorType
+  )
+{
+  UINT8                           VerbTableEntryNum;
+  UINT32                          VerbTableArray[32];
+  UINT32                          *VerbTablePtr;
+
+  VerbTableEntryNum = 0;
+
+  InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable));
+
+  if (CodecType == PchHdaCodecPlatformOnboard) {
+    DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n"));
+    if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) {
+      if (AudioConnectorType == 0) { //Type-C Audio connector selected in Bios Setup menu
+        InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable));
+        InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+        InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+        DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n"));
+      } else { //Stacked Jack Audio connector selected in Bios Setup menu
+        InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
+        InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
+        InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+        DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n"));
+      }
+    } else {
+      InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
+      InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
+      InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);
+    }
+  } else {
+    DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));
+    InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1));
+    InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2));
+    InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3));
+  }
+
+  FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum;
+
+  VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntryNum);
+  CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryNum);
+  FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr;
+}
+
+/**
+  Performs FSP PCH PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+
+  FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
+  FspsUpd->FspsConfig.PchSubSystemId       = V_PCH_DEFAULT_SID;
+
+  FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
+
+  InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector));
+
+DEBUG_CODE_BEGIN();
+if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
+      FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) {
+    FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart;
+  }
+DEBUG_CODE_END();
+
+  return EFI_SUCCESS;
+}
+

+ 34 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.h

@@ -0,0 +1,34 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/MmPciLib.h>
+#include <Library/ConfigBlockLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#endif

+ 254 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c

@@ -0,0 +1,254 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <PchHsioPtssTables.h>
+#include <Library/DebugLib.h>
+
+VOID
+InstallPlatformHsioPtssTable (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  HSIO_PTSS_TABLES            *UnknowPtssTables;
+  HSIO_PTSS_TABLES            *SpecificPtssTables;
+  HSIO_PTSS_TABLES            *PtssTables;
+  UINT8                       PtssTableIndex;
+  UINT32                      UnknowTableSize;
+  UINT32                      SpecificTableSize;
+  UINT32                      TableSize;
+  UINT32                      Entry;
+  UINT8                       LaneNum;
+  UINT8                       Index;
+  UINT8                       MaxSataPorts;
+  UINT8                       MaxPciePorts;
+  UINT8                       PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
+  UINT8                       PciePort;
+  UINTN                       RpBase;
+  UINTN                       RpDevice;
+  UINTN                       RpFunction;
+  UINT32                      StrapFuseCfg;
+  UINT8                       PcieControllerCfg;
+  EFI_STATUS                  Status;
+
+  UnknowPtssTables = NULL;
+  UnknowTableSize = 0;
+  SpecificPtssTables = NULL;
+  SpecificTableSize = 0;
+
+  if (GetPchGeneration () == SklPch) {
+    switch (PchStepping ()) {
+      case PchLpB0:
+      case PchLpB1:
+        UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
+        UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
+        SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
+        SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
+        break;
+      case PchLpC0:
+      case PchLpC1:
+        UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
+        UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
+        SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
+        SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
+        break;
+      case PchHB0:
+      case PchHC0:
+        UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
+        UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
+        SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
+        SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
+        break;
+      case PchHD0:
+      case PchHD1:
+        UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
+        UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
+        SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
+        SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
+        break;
+      default:
+        UnknowPtssTables = NULL;
+        UnknowTableSize = 0;
+        SpecificPtssTables = NULL;
+        SpecificTableSize = 0;
+        DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
+    }
+  } else {
+    switch (PchStepping ()) {
+      case KblPchHA0:
+        UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
+        UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
+        SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
+        SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
+        break;
+      default:
+        UnknowPtssTables = NULL;
+        UnknowTableSize = 0;
+        SpecificPtssTables = NULL;
+        SpecificTableSize = 0;
+        DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
+    }
+  }
+
+  PtssTableIndex = 0;
+  MaxSataPorts = GetPchMaxSataPortNum ();
+  MaxPciePorts = GetPchMaxPciePortNum ();
+  ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
+
+  //Populate PCIe topology based on lane configuration
+  for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
+    Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
+    ASSERT_EFI_ERROR (Status);
+
+    RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
+    StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
+    PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
+    DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
+  }
+  for (Index = 0; Index < MaxPciePorts; Index++) {
+    DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
+  }
+
+  //Case 1: BoardId is known, Topology is known/unknown
+  //Case 1a: SATA
+  PtssTables = SpecificPtssTables;
+  TableSize = SpecificTableSize;
+  for (Index = 0; Index < MaxSataPorts; Index++) {
+    if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+      for (Entry = 0; Entry < TableSize; Entry++) {
+        if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+            (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
+          )
+        {
+          PtssTableIndex++;
+          if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
+            (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
+            FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
+            FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
+          } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
+            if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
+              FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
+              FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
+            }
+            if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
+              FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
+              FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
+            }
+          } else {
+            ASSERT (FALSE);
+          }
+        }
+      }
+    }
+  }
+  //Case 1b: PCIe
+  for (Index = 0; Index < MaxPciePorts; Index++) {
+    if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+      for (Entry = 0; Entry < TableSize; Entry++) {
+        if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+            (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
+            (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
+          PtssTableIndex++;
+          if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
+            (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
+            FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
+            FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
+          } else {
+            ASSERT (FALSE);
+          }
+        }
+      }
+    }
+  }
+  //Case 2: BoardId is unknown, Topology is known/unknown
+  if (PtssTableIndex == 0) {
+    DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
+
+    PtssTables = UnknowPtssTables;
+    TableSize = UnknowTableSize;
+
+    for (Index = 0; Index < MaxSataPorts; Index++) {
+      if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+        for (Entry = 0; Entry < TableSize; Entry++) {
+          if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+              (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
+             )
+          {
+            if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
+              (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
+              FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
+              FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
+            } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
+              if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
+                FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
+                FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
+              }
+              if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
+                FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
+                FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
+              }
+            } else {
+              ASSERT (FALSE);
+            }
+          }
+        }
+      }
+    }
+    for (Index = 0; Index < MaxPciePorts; Index++) {
+      if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
+        for (Entry = 0; Entry < TableSize; Entry++) {
+          if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
+              (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
+              (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
+            if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
+              (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
+              FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
+              FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
+            } else {
+              ASSERT (FALSE);
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/**
+  Performs FSP PCH PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  InstallPlatformHsioPtssTable (FspmUpd);
+  return EFI_SUCCESS;
+}
+

+ 90 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.c

@@ -0,0 +1,90 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/PeiLib.h>
+
+/**
+  Performs FSP SA PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdate (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  VOID                            *Buffer;
+  VOID                            *MemBuffer;
+  UINT32                          Size;
+
+  DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+
+    FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
+
+    Size   = 0;
+    Buffer = NULL;
+    PeiGetSectionFromAnyFv (&gIntelPeiGraphicsVbtGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
+    if (Buffer == NULL) {
+      DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
+    } else {
+      MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+      if ((MemBuffer != NULL) && (Buffer != NULL)) {
+        CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+        FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer;
+      } else {
+        DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
+        FspsUpd->FspsConfig.GraphicsConfigPtr = 0;
+      }
+    }
+    DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
+    DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+
+    Size   = 0;
+    Buffer = NULL;
+    PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
+    if (Buffer == NULL) {
+      DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
+    } else {
+      MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+      if ((MemBuffer != NULL) && (Buffer != NULL)) {
+        CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+        FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer;
+        FspsUpd->FspsConfig.LogoSize = Size;
+      } else {
+        DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
+        FspsUpd->FspsConfig.LogoPtr = 0;
+        FspsUpd->FspsConfig.LogoSize = 0;
+      }
+    }
+    DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
+    DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
+
+  return EFI_SUCCESS;
+}
+

+ 37 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.h

@@ -0,0 +1,37 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <SaPolicyCommon.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <CpuAccess.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+extern EFI_GUID gIntelPeiGraphicsVbtGuid;
+extern EFI_GUID gTianoLogoGuid;
+
+#endif
+

+ 74 - 0
Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c

@@ -0,0 +1,74 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Library/CpuMailboxLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+
+
+/**
+  Performs FSP SA PEI Policy initialization in pre-memory.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  VOID                        *Buffer;
+
+  CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
+  CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
+
+  DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12);
+  }
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8);
+  }
+
+  DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
+  }
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
+  }
+  return EFI_SUCCESS;
+}
+

+ 120 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl

@@ -0,0 +1,120 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+  // Define a Global region of ACPI NVS Region that may be used for any
+  // type of implementation.  The starting offset and size will be fixed
+  // up by the System BIOS during POST.  Note that the Size must be a word
+  // in size to be fixed up correctly.
+
+  
+
+
+  OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
+  Field(GNVS,AnyAcc,Lock,Preserve)
+  {
+  //
+  // Miscellaneous Dynamic Registers:
+  //
+  Offset(0),      OSYS, 16, // Offset(0),     Operating System
+  Offset(2),      SMIF, 8,  // Offset(2),     SMI Function Call (ASL to SMI via I/O Trap)
+  Offset(3),      P80D, 32, // Offset(3),     Port 80 Debug Port Value
+  Offset(7),      PWRS, 8,  // Offset(7),     Power State (AC Mode = 1)
+  //
+  // Thermal Policy Registers:
+  //
+  Offset(8),      DTSE, 8,  // Offset(8),    Digital Thermal Sensor Enable
+  Offset(9),      DTSF, 8,  // Offset(9),    DTS SMI Function Call
+  //                 
+  // CPU Identification Registers:
+  //
+  Offset(10),     APIC, 8,  // Offset(10),    APIC Enabled by SBIOS (APIC Enabled = 1)
+  Offset(11),     TCNT, 8,  // Offset(11),    Number of Enabled Threads
+  //
+  // PCIe Hot Plug
+  //
+  Offset(12),     OSCC, 8,  // Offset(12),    PCIE OSC Control
+  Offset(13),     NEXP, 8,  // Offset(13),    Native PCIE Setup Value
+  //
+  // Global Variables
+  //
+  Offset(14),     DSEN, 8,  // Offset(14),    _DOS Display Support Flag.
+  Offset(15),     GPIC, 8,  // Offset(15),    Global IOAPIC/8259 Interrupt Mode Flag.
+  Offset(16),     L01C, 8,  // Offset(16),    Global L01 Counter.
+  Offset(17),     LTR1, 8,  // Offset(17),    Latency Tolerance Reporting Enable
+  Offset(18),     LTR2, 8,  // Offset(18),    Latency Tolerance Reporting Enable
+  Offset(19),     LTR3, 8,  // Offset(19),    Latency Tolerance Reporting Enable
+  Offset(20),     LTR4, 8,  // Offset(20),    Latency Tolerance Reporting Enable
+  Offset(21),     LTR5, 8,  // Offset(21),    Latency Tolerance Reporting Enable
+  Offset(22),     LTR6, 8,  // Offset(22),    Latency Tolerance Reporting Enable
+  Offset(23),     LTR7, 8,  // Offset(23),    Latency Tolerance Reporting Enable
+  Offset(24),     LTR8, 8,  // Offset(24),    Latency Tolerance Reporting Enable
+  Offset(25),     LTR9, 8,  // Offset(25),    Latency Tolerance Reporting Enable
+  Offset(26),     LTRA, 8,  // Offset(26),    Latency Tolerance Reporting Enable
+  Offset(27),     LTRB, 8,  // Offset(27),    Latency Tolerance Reporting Enable
+  Offset(28),     LTRC, 8,  // Offset(28),    Latency Tolerance Reporting Enable
+  Offset(29),     LTRD, 8,  // Offset(29),    Latency Tolerance Reporting Enable
+  Offset(30),     LTRE, 8,  // Offset(30),    Latency Tolerance Reporting Enable
+  Offset(31),     LTRF, 8,  // Offset(31),    Latency Tolerance Reporting Enable
+  Offset(32),     LTRG, 8,  // Offset(32),    Latency Tolerance Reporting Enable
+  Offset(33),     LTRH, 8,  // Offset(33),    Latency Tolerance Reporting Enable
+  Offset(34),     LTRI, 8,  // Offset(34),    Latency Tolerance Reporting Enable
+  Offset(35),     LTRJ, 8,  // Offset(35),    Latency Tolerance Reporting Enable
+  Offset(36),     LTRK, 8,  // Offset(36),    Latency Tolerance Reporting Enable
+  Offset(37),     LTRL, 8,  // Offset(37),    Latency Tolerance Reporting Enable
+  Offset(38),     LTRM, 8,  // Offset(38),    Latency Tolerance Reporting Enable
+  Offset(39),     LTRN, 8,  // Offset(39),    Latency Tolerance Reporting Enable
+  Offset(40),     LTRO, 8,  // Offset(40),    Latency Tolerance Reporting Enable
+  Offset(41),     OBF1, 8,  // Offset(41),    Optimized Buffer Flush and Fill
+  Offset(42),     OBF2, 8,  // Offset(42),    Optimized Buffer Flush and Fill
+  Offset(43),     OBF3, 8,  // Offset(43),    Optimized Buffer Flush and Fill
+  Offset(44),     OBF4, 8,  // Offset(44),    Optimized Buffer Flush and Fill
+  Offset(45),     OBF5, 8,  // Offset(45),    Optimized Buffer Flush and Fill
+  Offset(46),     OBF6, 8,  // Offset(46),    Optimized Buffer Flush and Fill
+  Offset(47),     OBF7, 8,  // Offset(47),    Optimized Buffer Flush and Fill
+  Offset(48),     OBF8, 8,  // Offset(48),    Optimized Buffer Flush and Fill
+  Offset(49),     OBF9, 8,  // Offset(49),    Optimized Buffer Flush and Fill
+  Offset(50),     OBFA, 8,  // Offset(50),    Optimized Buffer Flush and Fill
+  Offset(51),     OBFB, 8,  // Offset(51),    Optimized Buffer Flush and Fill
+  Offset(52),     OBFC, 8,  // Offset(52),    Optimized Buffer Flush and Fill
+  Offset(53),     OBFD, 8,  // Offset(53),    Optimized Buffer Flush and Fill
+  Offset(54),     OBFE, 8,  // Offset(54),    Optimized Buffer Flush and Fill
+  Offset(55),     OBFF, 8,  // Offset(55),    Optimized Buffer Flush and Fill
+  Offset(56),     OBFG, 8,  // Offset(56),    Optimized Buffer Flush and Fill
+  Offset(57),     OBFH, 8,  // Offset(57),    Optimized Buffer Flush and Fill
+  Offset(58),     OBFI, 8,  // Offset(58),    Optimized Buffer Flush and Fill
+  Offset(59),     OBFJ, 8,  // Offset(59),    Optimized Buffer Flush and Fill
+  Offset(60),     OBFK, 8,  // Offset(60),    Optimized Buffer Flush and Fill
+  Offset(61),     OBFL, 8,  // Offset(61),    Optimized Buffer Flush and Fill
+  Offset(62),     OBFM, 8,  // Offset(62),    Optimized Buffer Flush and Fill
+  Offset(63),     OBFN, 8,  // Offset(63),    Optimized Buffer Flush and Fill
+  Offset(64),     OBFO, 8,  // Offset(64),    Optimized Buffer Flush and Fill
+  Offset(65),     RTD3, 8,  // Offset(65),    Runtime D3 support.
+  Offset(66),     S0ID, 8,  // Offset(66),    Low Power S0 Idle Enable
+  Offset(67),     GBSX, 8,  // Offset(67),    Virtual GPIO button Notify Sleep State Change
+  Offset(68),     PSCP, 8,  // Offset(68),    P-state Capping
+  Offset(69),     P2ME, 8,  // Offset(69),    Ps2 Mouse Enable
+  Offset(70),     P2MK, 8,  // Offset(70),    Ps2 Keyboard and Mouse Enable
+  //
+  // Driver Mode
+  //
+  Offset(71),     GIRQ, 32, // Offset(71),    GPIO IRQ
+  Offset(75),     PLCS, 8,  // Offset(75),    set PL1 limit when entering CS
+  Offset(76),     PLVL, 16, // Offset(76),    PL1 limit value
+  Offset(78),     PB1E, 8,  // Offset(78),    10sec Power button support
+  Offset(79),     ECR1, 8,  // Offset(79),    Pci Delay Optimization Ecr
+  Offset(80),     TBTS, 8,  // Offset(80),    Thunderbolt(TM) support
+  Offset(81),     TNAT, 8,  // Offset(81),    TbtNativeOsHotPlug
+  Offset(82),     TBSE, 8,  // Offset(82),    Thunderbolt(TM) Root port selector
+  Offset(83),     TBS1, 8,  // Offset(83),    Thunderbolt(TM) Root port selector
+  }

+ 123 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h

@@ -0,0 +1,123 @@
+/** @file
+  ACPI DSDT table
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+  // Define a Global region of ACPI NVS Region that may be used for any
+  // type of implementation.  The starting offset and size will be fixed
+  // up by the System BIOS during POST.  Note that the Size must be a word
+  // in size to be fixed up correctly.
+
+  
+#ifndef _GLOBAL_NVS_AREA_DEF_H_
+#define _GLOBAL_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+  //
+  // Miscellaneous Dynamic Registers:
+  //
+  UINT16   OperatingSystem;                         ///< Offset 0       Operating System
+  UINT8    SmiFunction;                             ///< Offset 2       SMI Function Call (ASL to SMI via I/O Trap)
+  UINT32   Port80DebugValue;                        ///< Offset 3       Port 80 Debug Port Value
+  UINT8    PowerState;                              ///< Offset 7       Power State (AC Mode = 1)
+  //
+  // Thermal Policy Registers:
+  //
+  UINT8    EnableDigitalThermalSensor;              ///< Offset 8       Digital Thermal Sensor Enable
+  UINT8    DigitalThermalSensorSmiFunction;         ///< Offset 9       DTS SMI Function Call
+  //                 
+  // CPU Identification Registers:
+  //
+  UINT8    ApicEnable;                              ///< Offset 10      APIC Enabled by SBIOS (APIC Enabled = 1)
+  UINT8    ThreadCount;                             ///< Offset 11      Number of Enabled Threads
+  //
+  // PCIe Hot Plug
+  //
+  UINT8    PcieOSCControl;                          ///< Offset 12      PCIE OSC Control
+  UINT8    NativePCIESupport;                       ///< Offset 13      Native PCIE Setup Value
+  //
+  // Global Variables
+  //
+  UINT8    DisplaySupportFlag;                      ///< Offset 14      _DOS Display Support Flag.
+  UINT8    InterruptModeFlag;                       ///< Offset 15      Global IOAPIC/8259 Interrupt Mode Flag.
+  UINT8    L01Counter;                              ///< Offset 16      Global L01 Counter.
+  UINT8    LtrEnable[24];                           ///< Offset 17      Latency Tolerance Reporting Enable
+                                                    ///< Offset 18      Latency Tolerance Reporting Enable
+                                                    ///< Offset 19      Latency Tolerance Reporting Enable
+                                                    ///< Offset 20      Latency Tolerance Reporting Enable
+                                                    ///< Offset 21      Latency Tolerance Reporting Enable
+                                                    ///< Offset 22      Latency Tolerance Reporting Enable
+                                                    ///< Offset 23      Latency Tolerance Reporting Enable
+                                                    ///< Offset 24      Latency Tolerance Reporting Enable
+                                                    ///< Offset 25      Latency Tolerance Reporting Enable
+                                                    ///< Offset 26      Latency Tolerance Reporting Enable
+                                                    ///< Offset 27      Latency Tolerance Reporting Enable
+                                                    ///< Offset 28      Latency Tolerance Reporting Enable
+                                                    ///< Offset 29      Latency Tolerance Reporting Enable
+                                                    ///< Offset 30      Latency Tolerance Reporting Enable
+                                                    ///< Offset 31      Latency Tolerance Reporting Enable
+                                                    ///< Offset 32      Latency Tolerance Reporting Enable
+                                                    ///< Offset 33      Latency Tolerance Reporting Enable
+                                                    ///< Offset 34      Latency Tolerance Reporting Enable
+                                                    ///< Offset 35      Latency Tolerance Reporting Enable
+                                                    ///< Offset 36      Latency Tolerance Reporting Enable
+                                                    ///< Offset 37      Latency Tolerance Reporting Enable
+                                                    ///< Offset 38      Latency Tolerance Reporting Enable
+                                                    ///< Offset 39      Latency Tolerance Reporting Enable
+                                                    ///< Offset 40      Latency Tolerance Reporting Enable
+  UINT8    ObffEnable[24];                          ///< Offset 41      Optimized Buffer Flush and Fill
+                                                    ///< Offset 42      Optimized Buffer Flush and Fill
+                                                    ///< Offset 43      Optimized Buffer Flush and Fill
+                                                    ///< Offset 44      Optimized Buffer Flush and Fill
+                                                    ///< Offset 45      Optimized Buffer Flush and Fill
+                                                    ///< Offset 46      Optimized Buffer Flush and Fill
+                                                    ///< Offset 47      Optimized Buffer Flush and Fill
+                                                    ///< Offset 48      Optimized Buffer Flush and Fill
+                                                    ///< Offset 49      Optimized Buffer Flush and Fill
+                                                    ///< Offset 50      Optimized Buffer Flush and Fill
+                                                    ///< Offset 51      Optimized Buffer Flush and Fill
+                                                    ///< Offset 52      Optimized Buffer Flush and Fill
+                                                    ///< Offset 53      Optimized Buffer Flush and Fill
+                                                    ///< Offset 54      Optimized Buffer Flush and Fill
+                                                    ///< Offset 55      Optimized Buffer Flush and Fill
+                                                    ///< Offset 56      Optimized Buffer Flush and Fill
+                                                    ///< Offset 57      Optimized Buffer Flush and Fill
+                                                    ///< Offset 58      Optimized Buffer Flush and Fill
+                                                    ///< Offset 59      Optimized Buffer Flush and Fill
+                                                    ///< Offset 60      Optimized Buffer Flush and Fill
+                                                    ///< Offset 61      Optimized Buffer Flush and Fill
+                                                    ///< Offset 62      Optimized Buffer Flush and Fill
+                                                    ///< Offset 63      Optimized Buffer Flush and Fill
+                                                    ///< Offset 64      Optimized Buffer Flush and Fill
+  UINT8    Rtd3Support;                             ///< Offset 65      Runtime D3 support.
+  UINT8    LowPowerS0Idle;                          ///< Offset 66      Low Power S0 Idle Enable
+  UINT8    VirtualGpioButtonSxBitmask;              ///< Offset 67      Virtual GPIO button Notify Sleep State Change
+  UINT8    PstateCapping;                           ///< Offset 68      P-state Capping
+  UINT8    Ps2MouseEnable;                          ///< Offset 69      Ps2 Mouse Enable
+  UINT8    Ps2KbMsEnable;                           ///< Offset 70      Ps2 Keyboard and Mouse Enable
+  //
+  // Driver Mode
+  //
+  UINT32   GpioIrqRoute;                            ///< Offset 71      GPIO IRQ
+  UINT8    PL1LimitCS;                              ///< Offset 75      set PL1 limit when entering CS
+  UINT16   PL1LimitCSValue;                         ///< Offset 76      PL1 limit value
+  UINT8    TenSecondPowerButtonEnable;              ///< Offset 78      10sec Power button support
+  UINT8    PciDelayOptimizationEcr;                 ///< Offset 79      Pci Delay Optimization Ecr
+  UINT8    TbtSupport;                              ///< Offset 80      Thunderbolt(TM) support
+  UINT8    TbtNativeOsHotPlug;                      ///< Offset 81      TbtNativeOsHotPlug
+  UINT8    TbtSelector;                             ///< Offset 82      Thunderbolt(TM) Root port selector
+  UINT8    TbtSelector1;                            ///< Offset 83      Thunderbolt(TM) Root port selector
+} EFI_GLOBAL_NVS_AREA;
+
+#pragma pack(pop)
+#endif

+ 48 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf

@@ -0,0 +1,48 @@
+## @file
+#  FDF file of Platform.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+#=================================================================================#
+# 8 M BIOS - for FSP wrapper
+#=================================================================================#
+DEFINE FLASH_BASE                                                   = 0xFF800000  #
+DEFINE FLASH_SIZE                                                   = 0x00800000  #
+DEFINE FLASH_BLOCK_SIZE                                             = 0x00010000  #
+DEFINE FLASH_NUM_BLOCKS                                             = 0x00000080  #
+#=================================================================================#
+
+SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageOffset           = 0x00000000  # Flash addr (0xFF800000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageSize             = 0x00040000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset   = 0x00000000  # Flash addr (0xFF800000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize    = 0x0001E000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000  # Flash addr (0xFF81E000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize  = 0x00002000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset   = 0x00020000  # Flash addr (0xFF820000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize    = 0x00020000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Offset             = 0x00080000  # Flash addr (0xFF880000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Size               = 0x00090000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMainOffset              = 0x00110000  # Flash addr (0xFF910000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize                = 0x00270000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Offset         = 0x00380000  # Flash addr (0xFFB80000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size           = 0x00170000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsOffset              = 0x004F0000  # Flash addr (0xFFCF0000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsSize                = 0x00050000  #
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset                  = 0x00550000  # Flash addr (0xFFD50000)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    = 0x000B0000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Offset         = 0x00600000  # Flash addr (0xFFE00000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size           = 0x00120000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtOffset             = 0x00720000  # Flash addr (0xFFF20000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtSize               = 0x000C0000  #
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryOffset          = 0x007E0000  # Flash addr (0xFFFE0000)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize            = 0x00020000  #

+ 73 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/IoExpander.h

@@ -0,0 +1,73 @@
+/** @file
+  GPIO definition table for KabylakeRvp3
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IO_EXPANDER_H_
+#define _IO_EXPANDER_H_
+
+typedef struct {
+  UINT32 IoExpanderNumber   : 1;  // IO Expander Number (0/1)
+  UINT32 GpioPinNumber      : 5;  // GPIO Pin Number (0 to 23)
+  UINT32 GpioDirection      : 1;  // GPIO Pin Direction (Input/Output)
+  UINT32 GpioLevel          : 1;  // GPIO Pin Output Level (High/Low)
+  UINT32 GpioInversion     : 1;  // GPIO Pin Inversion (Enabled/Disabled)
+  UINT32 Reserved           : 23; // Reserved
+} IO_EXPANDER_GPIO_CONFIG;
+
+//SKL PCH LP GPIO Expander Number
+#define IO_EXPANDER_0            0
+#define IO_EXPANDER_1            1
+
+//SKL PCH LP GPIO Pin Mapping
+#define IO_EXPANDER_GPIO_0        0   // P00
+#define IO_EXPANDER_GPIO_1        1   // P01
+#define IO_EXPANDER_GPIO_2        2   // P02
+#define IO_EXPANDER_GPIO_3        3   // P03
+#define IO_EXPANDER_GPIO_4        4   // P04
+#define IO_EXPANDER_GPIO_5        5   // P05
+#define IO_EXPANDER_GPIO_6        6   // P06
+#define IO_EXPANDER_GPIO_7        7   // P07
+#define IO_EXPANDER_GPIO_8        8   // P10
+#define IO_EXPANDER_GPIO_9        9   // P11
+#define IO_EXPANDER_GPIO_10       10  // P12
+#define IO_EXPANDER_GPIO_11       11  // P13
+#define IO_EXPANDER_GPIO_12       12  // P14
+#define IO_EXPANDER_GPIO_13       13  // P15
+#define IO_EXPANDER_GPIO_14       14  // P16
+#define IO_EXPANDER_GPIO_15       15  // P17
+#define IO_EXPANDER_GPIO_16       16  // P20
+#define IO_EXPANDER_GPIO_17       17  // P21
+#define IO_EXPANDER_GPIO_18       18  // P22
+#define IO_EXPANDER_GPIO_19       19  // P23
+#define IO_EXPANDER_GPIO_20       20  // P24
+#define IO_EXPANDER_GPIO_21       21  // P25
+#define IO_EXPANDER_GPIO_22       22  // P26
+#define IO_EXPANDER_GPIO_23       23  // P27
+
+//SKL PCH LP GPIO Expander GPIO Direction
+#define IO_EXPANDER_GPIO_OUTPUT   0
+#define IO_EXPANDER_GPIO_INPUT    1
+
+//SKL PCH LP GPIO Expaner GPIO Output Level
+#define IO_EXPANDER_GPO_LEVEL_LOW    0
+#define IO_EXPANDER_GPO_LEVEL_HIGH   1
+
+//SKL PCH LP GPIO Expaner GPIO Inversion Status
+#define IO_EXPANDER_GPI_INV_DISABLED  0
+#define IO_EXPANDER_GPI_INV_ENABLED   1
+#define IO_EXPANDER_GPIO_RESERVED     0x00
+
+//GPIO Table Terminator
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+#endif

+ 128 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/Library/GpioExpanderLib.h

@@ -0,0 +1,128 @@
+/** @file
+  Support for IO expander TCA6424.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GPIO_EXPANDER_LIB_H_
+#define _GPIO_EXPANDER_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+/**
+  Set the Direction value for the given Expander Gpio pin.
+
+  This function is to Set the direction value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+**/
+VOID
+GpioExpSetDirection (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Direction
+  );
+/**
+  Set the input value for the given Expander Gpio pin.
+
+  This function is to get the input value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetPolarity  (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Polarity
+  );
+/**
+  Set the Output value for the given Expander Gpio pin.
+
+  This function is to Set the Output value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetOutput    (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value
+  );
+/**
+  Returns the data from register value giving in the input.
+
+  This function is to get the data from the Expander
+  Registers by following the I2C Protocol communication
+
+
+  @param[in]  Bar0       Bar address of the SerialIo Controller
+  @param[in]  Address    Expander Value with in the Contoller
+  @param[in]  Register   Address of Input/Output/Configure/Polarity
+                         registers with in the Expander
+
+  @retval     UINT8      Value returned from the register
+**/
+UINT8
+GpioExpGetInput     (
+  IN UINT8 Expander,
+  IN UINT8 Pin
+  );
+
+/**
+  Configures all registers of a single IO Expander in one go.
+
+  @param[in]  Expander    Expander number (0/1)
+  @param[in]  Direction   Bit-encoded direction values. BIT0 is for pin0, etc. 0=output, 1=input
+  @param[in]  Polarity    Bit-encoded input inversion values. BIT0 is for pin0, etc. 0=normal, 1=inversion
+  @param[in]  Output      Bit-encoded output state, ignores polarity, only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
+
+**/
+VOID
+GpioExpBulkConfig (
+  IN UINT8  Expander,
+  IN UINT32 Direction,
+  IN UINT32 Polarity,
+  IN UINT32 Output
+  );
+
+/**
+  Returns the Controller on which GPIO expander is present.
+
+  This function returns the Controller value
+
+  @param[out] Controller              Pointer to a Controller value on
+                                      which I2C expander is configured.
+
+  @retval     EFI_SUCCESS              non.
+**/
+EFI_STATUS
+GpioExpGetController (
+  OUT UINT8 *Controller
+  );
+
+#endif

+ 39 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/Library/I2cAccessLib.h

@@ -0,0 +1,39 @@
+/** @file
+  Support for IO expander TCA6424.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _I2C_ACCESS_LIB_H_
+#define _I2C_ACCESS_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+#define WAIT_1_SECOND            1600000000 //1.6 * 10^9
+
+EFI_STATUS
+I2cWriteRead (
+  IN UINTN  MmioBase,
+  IN UINT8  SlaveAddress,
+  IN UINT8  WriteLength,
+  IN UINT8  *WriteBuffer,
+  IN UINT8  ReadLength,
+  IN UINT8  *ReadBuffer,
+  IN UINT64  TimeBudget
+  );
+
+#endif

+ 57 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/PchHsioPtssTables.h

@@ -0,0 +1,57 @@
+/** @file*
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCH_HSIO_PTSSTABLES_H_
+#define PCH_HSIO_PTSSTABLES_H_
+
+#include <PchAccess.h>
+
+///
+/// SATA PTSS Topology Types
+///
+typedef enum {
+  PchSataTopoUnknown = 0x00,
+  PchSataTopoIsata,
+  PchSataTopoDirectConnect,
+  PchSataTopoFlex,
+  PchSataTopoM2
+} PCH_SATA_TOPOLOGY;
+
+///
+/// PCIe PTSS Topology Types
+///
+typedef enum {
+  PchPcieTopoUnknown = 0x00,
+  PchPcieTopox1,
+  PchPcieTopox4,
+  PchPcieTopoSataE,
+  PchPcieTopoM2
+} PCH_PCIE_TOPOLOGY;
+
+///
+/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH.
+///
+typedef struct {
+  UINT8       LaneNum;
+  UINT8       PhyMode;
+  UINT16      Offset;
+  UINT32      Value;
+  UINT32      BitMask;
+} PCH_SBI_PTSS_HSIO_TABLE;
+
+typedef struct {
+  PCH_SBI_PTSS_HSIO_TABLE   PtssTable;
+  UINT16                    Topology;
+} HSIO_PTSS_TABLES;
+
+#endif // PCH_HSIO_PTSSTABLES_H_

+ 53 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h

@@ -0,0 +1,53 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+
+#define GLOBAL_NVS_AREA_REVISION       16
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#include <Acpi/GlobalNvsAreaDef.h>
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+  EFI_GLOBAL_NVS_AREA     *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif

+ 163 - 0
Platform/Intel/KabylakeOpenBoardPkg/Include/SioRegs.h

@@ -0,0 +1,163 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SIO_REG_H_
+#define _SIO_REG_H_
+
+#define REG_LOGICAL_DEVICE        0x07
+#define ACTIVATE                  0x30
+
+#define BASE_ADDRESS_HIGH0        0x60
+#define BASE_ADDRESS_LOW0         0x61
+#define BASE_ADDRESS_HIGH1        0x62
+#define BASE_ADDRESS_LOW1         0x63
+#define BASE_ADDRESS_HIGH2        0x64
+#define BASE_ADDRESS_LOW2         0x65
+#define BASE_ADDRESS_HIGH3        0x66
+#define BASE_ADDRESS_LOW3         0x67
+#define PRIMARY_INTERRUPT_SELECT  0x70
+#define WAKEUP_ON_IRQ_EN          0x70
+#define INTERRUPT_TYPE            0x71
+#define DMA_CHANNEL_SELECT0       0x74
+#define DMA_CHANNEL_SELECT1       0x75
+
+
+
+//
+//Port address for PILOT - III
+//
+#define PILOTIII_CHIP_ID         0x03
+#define PILOTIII_SIO_INDEX_PORT  0x04E
+#define PILOTIII_SIO_DATA_PORT   (PILOTIII_SIO_INDEX_PORT+1)
+
+#define PILOTIII_UNLOCK      0x5A
+#define PILOTIII_LOCK        0xA5
+
+//
+// logical device in PILOT-III
+//
+#define PILOTIII_SIO_PSR     0x00
+#define PILOTIII_SIO_COM2    0x01
+#define PILOTIII_SIO_COM1    0x02
+#define PILOTIII_SIO_SWCP    0x03
+#define PILOTIII_SIO_GPIO    0x04
+#define PILOTIII_SIO_WDT     0x05
+#define PILOTIII_SIO_KCS3    0x08
+#define PILOTIII_SIO_KCS4    0x09
+#define PILOTIII_SIO_KCS5    0x0A
+#define PILOTIII_SIO_BT      0x0B
+#define PILOTIII_SIO_SMIC    0x0C
+#define PILOTIII_SIO_MAILBOX 0x0D
+#define PILOTIII_SIO_RTC     0x0E
+#define PILOTIII_SIO_SPI     0x0F
+#define PILOTIII_SIO_TAP     0x10
+//
+// Regisgers for Pilot-III
+//
+#define PILOTIII_CHIP_ID_REG               0x20
+#define PILOTIII_LOGICAL_DEVICE            REG_LOGICAL_DEVICE
+#define PILOTIII_ACTIVATE                  ACTIVATE
+#define PILOTIII_BASE_ADDRESS_HIGH0        BASE_ADDRESS_HIGH0
+#define PILOTIII_BASE_ADDRESS_LOW0         BASE_ADDRESS_LOW0
+#define PILOTIII_BASE_ADDRESS_HIGH1        BASE_ADDRESS_HIGH1
+#define PILOTIII_BASE_ADDRESS_LOW1         BASE_ADDRESS_LOW1
+#define PILOTIII_PRIMARY_INTERRUPT_SELECT  PRIMARY_INTERRUPT_SELECT
+
+//
+// Port address for PC8374
+//
+#define PC8374_SIO_INDEX_PORT  0x02E
+#define PC8374_SIO_DATA_PORT   (PC8374_SIO_INDEX_PORT+1)
+
+//
+// Logical device in PC8374
+//
+#define PC8374_SIO_FLOPPY  0x00
+#define PC8374_SIO_PARA    0x01
+#define PC8374_SIO_COM2    0x02
+#define PC8374_SIO_COM1    0x03
+#define PC8374_SIO_MOUSE   0x05
+#define PC8374_SIO_KYBD    0x06
+#define PC8374_SIO_GPIO    0x07
+
+//
+// Registers specific for PC8374
+//
+#define PC8374_CLOCK_SELECT  0x2D
+#define PC8374_CLOCK_CONFIG  0x29
+
+//
+// Registers for PC8374
+//
+#define PC8374_LOGICAL_DEVICE            REG_LOGICAL_DEVICE
+#define PC8374_ACTIVATE                  ACTIVATE
+#define PC8374_BASE_ADDRESS_HIGH0        BASE_ADDRESS_HIGH0
+#define PC8374_BASE_ADDRESS_LOW0         BASE_ADDRESS_LOW0
+#define PC8374_PRIMARY_INTERRUPT_SELECT  PRIMARY_INTERRUPT_SELECT
+#define PC8374_DMA_CHANNEL_SELECT        DMA_CHANNEL_SELECT0
+
+#define PC87427_SERVERIO_CNF2           0x22
+
+
+//
+// Pilot III Mailbox Data Register definitions
+//
+#define MBDAT00_OFFSET                  0x00
+#define MBDAT01_OFFSET                  0x01
+#define MBDAT02_OFFSET                  0x02
+#define MBDAT03_OFFSET                  0x03
+#define MBDAT04_OFFSET                  0x04
+#define MBDAT05_OFFSET                  0x05
+#define MBDAT06_OFFSET                  0x06
+#define MBDAT07_OFFSET                  0x07
+#define MBDAT08_OFFSET                  0x08
+#define MBDAT09_OFFSET                  0x09
+#define MBDAT10_OFFSET                  0x0A
+#define MBDAT11_OFFSET                  0x0B
+#define MBDAT12_OFFSET                  0x0C
+#define MBDAT13_OFFSET                  0x0D
+#define MBDAT14_OFFSET                  0x0E
+#define MBDAT15_OFFSET                  0x0F
+#define MBST0_OFFSET                    0x10
+#define MBST1_OFFSET                    0x11
+#define MBBINT_OFFSET                   0x12
+
+//
+// Mailbox Bit definitions...
+//
+#define   MBBINT_MBBIST_BIT               0x80
+// If both are there, use the default one
+//
+#define  W83527_EXIST     BIT2
+#define  PC8374_EXIST     BIT1
+#define  PILOTIII_EXIST   BIT0
+#define  DEFAULT_SIO      PILOTIII_EXIST
+#define  DEFAULT_KDB      PC8374_EXIST
+
+#define IPMI_DEFAULT_SMM_IO_BASE           0xca2
+//
+// For Pilot III
+//
+
+#define PILOTIII_SWC_BASE_ADDRESS          0xA00
+#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
+#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
+#define PILOTIII_GPE1_BLK_BASE_ADDRESS     0x0A86
+#define PILOTIII_KCS3_DATA_BASE_ADDRESS    0x0CA4
+#define PILOTIII_KCS3_CMD_BASE_ADDRESS     0x0CA5
+#define PILOTIII_KCS4_DATA_BASE_ADDRESS    0x0CA2
+#define PILOTIII_KCS4_CMD_BASE_ADDRESS     0x0CA3
+#define PILOTIII_MAILBOX_BASE_ADDRESS      0x0600
+#define PILOTIII_MAILBOX_MASK              0xFFE0
+#define BMC_KCS_BASE_ADDRESS               0x0CA0
+#endif

+ 66 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/GitEdk2MinKabylake.bat

@@ -0,0 +1,66 @@
+@REM @file
+@REM
+@REM Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution.  The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+@echo off
+
+pushd ..\..\..\..\..\
+
+@REM Set WORKSPACE environment.
+set WORKSPACE=%cd%
+echo.
+echo Set WORKSPACE as: %WORKSPACE%
+echo.
+
+@REM Check whether Git has been installed and been added to system path.
+git --help >nul 2>nul
+if %ERRORLEVEL% NEQ 0 (
+  echo.
+  echo The 'git' command is not recognized.
+  echo Please make sure that Git is installed and has been added to system path.
+  echo.
+  goto :EOF
+)
+
+@REM Create the Conf directory under WORKSPACE
+if not exist %WORKSPACE%\Conf (
+  mkdir Conf
+)
+
+@REM Set other environments.
+@REM Basic Rule:
+@REM   Platform override Silicon override Core
+@REM   Source override Binary
+
+set PACKAGES_PATH=%WORKSPACE%\edk2-platforms\Platform\Intel;%WORKSPACE%\edk2-platforms\Silicon\Intel;%WORKSPACE%\edk2-non-osi\Platform\Intel;%WORKSPACE%\edk2-non-osi\Silicon\Intel;%WORKSPACE%\FSP;%WORKSPACE%\edk2;%WORKSPACE%
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+
+@REM Call edksetup.bat in the edk2 repository.
+call %WORKSPACE%\edk2\edksetup.bat
+
+set openssl_path=%WORKSPACE%
+
+popd
+
+goto :EOF
+
+:Help
+echo.
+echo Usage:
+echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] (optional)
+echo.
+echo -w    A absolute/relative path to be the workspace.
+echo       Default value is the current directory.
+echo.
+echo -b    The branch name of the repository. Currently, only master, udk2015,
+echo       trunk (same as master) and bp13 (same as udk2015) are supported.
+echo       Default value is master.
+echo.

+ 21 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/KabylakeRvp3Id.h

@@ -0,0 +1,21 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _KABYLAKE_RVP3_ID_H_
+#define _KABYLAKE_RVP3_ID_H_
+
+// PUT SKL CRB BoardIds here
+#define BoardIdSkylakeRvp3                  0x4
+#define BoardIdKabyLakeYLpddr3Rvp3          0x60
+
+#endif // _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_

+ 668 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.c

@@ -0,0 +1,668 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PlatformHookLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <SystemAgent/Include/SaAccess.h>
+#include <SioRegs.h>
+#include <Library/MmPciLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Register/PchRegsLpc.h>
+#include <PchAccess.h>
+
+#define COM1_BASE                                 0x3f8
+#define COM2_BASE                                 0x2f8
+
+#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS   0x0690
+
+#define LPC_SIO_INDEX_DEFAULT_PORT_2              0x2E
+#define LPC_SIO_DATA_DEFAULT_PORT_2               0x2F
+#define LPC_SIO_GPIO_REGISTER_ADDRESS_2           0x0A20
+
+#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT       0x2E
+#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT        0x2F
+#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT     0x4E
+#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT      0x4F
+
+typedef struct {
+  UINT8 Register;
+  UINT8 Value;
+} EFI_SIO_TABLE;
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] = {
+  {0x002, 0x88},     // Power On UARTs
+  {0x024, COM1_BASE >> 2},
+  {0x025, COM2_BASE >> 2},
+  {0x028, 0x043},    // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
+  {0x029, 0x080},    // SIRQ_CLKRUN_EN
+  {0x02A, 0x000},
+  {0x02B, 0x0DE},
+  {0x00A, 0x040},
+  {0x00C, 0x00E},
+  {0x02c, 0x002},
+  {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
+  {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
+  {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
+  {0x03a, 0x00A},    // LPC Docking Enabling
+  {0x031, 0x01f},
+  {0x032, 0x000},
+  {0x033, 0x004},
+  {0x038, 0x0FB},
+  {0x035, 0x0FE},
+  {0x036, 0x000},
+  {0x037, 0x0FF},
+  {0x039, 0x000},
+  {0x034, 0x001},
+  {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF},           // Relocate configuration ports base address
+  {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF}     // to ensure SIO config address can be accessed in OS
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] = {
+  {0x002, 0x88},     // Power On UARTs
+  {0x007, 0x00},
+  {0x024, COM1_BASE >> 2},
+  {0x025, COM2_BASE >> 2},
+  {0x028, 0x043},    // IRQ of UARTs, UART2 IRQ=3,UART1 IRQ=4,
+  {0x029, 0x080},    // SIRQ_CLKRUN_EN
+  {0x02A, 0x000},
+  {0x02B, 0x0DE},
+  {0x00A, 0x040},
+  {0x00C, 0x00E},
+  {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},
+  {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},
+  {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},
+  {0x03a, 0x00A},    // LPC Docking Enabling
+  {0x031, 0x01f},
+  {0x032, 0x000},
+  {0x033, 0x004},
+  {0x038, 0x0FB},
+  {0x035, 0x0FE},
+  {0x036, 0x000},
+  {0x037, 0x0FE},
+  {0x039, 0x000},
+  {0x034, 0x001}
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] = {
+  {0x29, 0x0A0},                  // Enable super I/O clock and set to 48MHz
+  {0x22, 0x003},                  //
+  {0x07, 0x003},                  // Select UART0 device
+  {0x60, (COM1_BASE >> 8)},       // Set Base Address MSB
+  {0x61, (COM1_BASE & 0x00FF)},   // Set Base Address LSB
+  {0x70, 0x004},                  // Set to IRQ4
+  {0x30, 0x001},                  // Enable it with Activation bit
+  {0x07, 0x002},                  // Select UART1 device
+  {0x60, (COM2_BASE >> 8)},       // Set Base Address MSB
+  {0x61, (COM2_BASE & 0x00FF)},   // Set Base Address LSB
+  {0x70, 0x003},                  // Set to IRQ3
+  {0x30, 0x001},                  // Enable it with Activation bit
+  {0x07, 0x007},                  // Select GPIO device
+  {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)},      // Set Base Address MSB
+  {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)},  // Set Base Address LSB
+  {0x30, 0x001},                  // Enable it with Activation bit
+  {0x21, 0x001},                  // Global Device Enable
+  {0x26, 0x000}                   // Fast Enable UART 0 & 1 as their enable & activation bit
+};
+
+//
+// National PC8374L
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] = {
+  {0x007, 0x03}, // Select Com1
+  {0x061, 0xF8}, // 0x3F8
+  {0x060, 0x03}, // 0x3F8
+  {0x070, 0x04}, // IRQ4
+  {0x030, 0x01}  // Active
+};
+
+//
+// IT8628
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = {
+  {0x023, 0x09}, // Clock Selection register
+  {0x007, 0x01}, // Com1 Logical Device Number select
+  {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register
+  {0x060, 0x03}, // Serial Port 1 Base Address LSB Register
+  {0x070, 0x04}, // Serial Port 1 Interrupt Level Select
+  {0x030, 0x01}, // Serial Port 1 Activate
+  {0x007, 0x02}, // Com1 Logical Device Number select
+  {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register
+  {0x060, 0x02}, // Serial Port 2 Base Address MSB Register
+  {0x070, 0x03}, // Serial Port 2 Interrupt Level Select
+  {0x030, 0x01}  // Serial Port 2 Activate
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = {
+  {0x007, 0x03}, // Parallel Port Logical Device Number select
+  {0x030, 0x00}, // Parallel port Activate
+  {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register
+  {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register
+  {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register
+  {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register
+  {0x0F0, 0x03}  // Special Configuration register
+};
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] = {
+  {0x07, 0x03},                   // Select UART0 device
+  {0x60, (COM1_BASE >> 8)},       // Set Base Address MSB
+  {0x61, (COM1_BASE & 0x00FF)},   // Set Base Address LSB
+  {0x70, 0x04},                   // Set to IRQ4
+  {0x30, 0x01}                    // Enable it with Activation bit
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] = {
+  {0x07, 0x02}, // Set logical device SP Serial port Com0
+  {0x61, 0xF8}, // Write Base Address LSB register 0x3F8
+  {0x60, 0x03}, // Write Base Address MSB register 0x3F8
+  {0x70, 0x04}, // Write IRQ1 value (IRQ 1)  keyboard
+  {0x30, 0x01}  // Enable serial port with Activation bit
+};
+
+/**
+  Detect if a National 393 SIO is docked. If yes, enable the docked SIO
+  and its serial port, and disable the onboard serial port.
+
+  @retval EFI_SUCCESS     Operations performed successfully.
+**/
+STATIC
+VOID
+CheckNationalSio (
+  VOID
+  )
+{
+  UINT8           Data8;
+
+  //
+  // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).
+  // We use (0x2e, 0x2f) which is determined by BADD default strapping
+  //
+
+  //
+  // Read the Pc87393 signature
+  //
+  IoWrite8 (0x2e, 0x20);
+  Data8 = IoRead8 (0x2f);
+
+  if (Data8 == 0xea) {
+    //
+    // Signature matches - National PC87393 SIO is docked
+    //
+
+    //
+    // Enlarge the LPC decode scope to accommodate the Docking LPC Switch
+    // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at
+    // SIO_BASE_ADDRESS + 0x10)
+    //
+    PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20);
+
+    //
+    // Enable port switch
+    //
+    IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);
+
+    //
+    // Turn on docking power
+    //
+    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);
+
+    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);
+
+    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);
+
+    //
+    // Enable port switch
+    //
+    IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);
+
+    //
+    // GPIO setting
+    //
+    IoWrite8 (0x2e, 0x24);
+    IoWrite8 (0x2f, 0x29);
+
+    //
+    // Enable chip clock
+    //
+    IoWrite8 (0x2e, 0x29);
+    IoWrite8 (0x2f, 0x1e);
+
+
+    //
+    // Enable serial port
+    //
+
+    //
+    // Select com1
+    //
+    IoWrite8 (0x2e, 0x7);
+    IoWrite8 (0x2f, 0x3);
+
+    //
+    // Base address: 0x3f8
+    //
+    IoWrite8 (0x2e, 0x60);
+    IoWrite8 (0x2f, 0x03);
+    IoWrite8 (0x2e, 0x61);
+    IoWrite8 (0x2f, 0xf8);
+
+    //
+    // Interrupt: 4
+    //
+    IoWrite8 (0x2e, 0x70);
+    IoWrite8 (0x2f, 0x04);
+
+    //
+    // Enable bank selection
+    //
+    IoWrite8 (0x2e, 0xf0);
+    IoWrite8 (0x2f, 0x82);
+
+    //
+    // Activate
+    //
+    IoWrite8 (0x2e, 0x30);
+    IoWrite8 (0x2f, 0x01);
+
+    //
+    // Disable onboard serial port
+    //
+    IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);
+
+    //
+    // Power Down UARTs
+    //
+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);
+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);
+
+    //
+    // Dissable COM1 decode
+    //
+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);
+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
+
+    //
+    // Disable COM2 decode
+    //
+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);
+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
+
+    //
+    // Disable interrupt
+    //
+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);
+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);
+
+    IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
+
+    //
+    // Enable floppy
+    //
+
+    //
+    // Select floppy
+    //
+    IoWrite8 (0x2e, 0x7);
+    IoWrite8 (0x2f, 0x0);
+
+    //
+    // Base address: 0x3f0
+    //
+    IoWrite8 (0x2e, 0x60);
+    IoWrite8 (0x2f, 0x03);
+    IoWrite8 (0x2e, 0x61);
+    IoWrite8 (0x2f, 0xf0);
+
+    //
+    // Interrupt: 6
+    //
+    IoWrite8 (0x2e, 0x70);
+    IoWrite8 (0x2f, 0x06);
+
+    //
+    // DMA 2
+    //
+    IoWrite8 (0x2e, 0x74);
+    IoWrite8 (0x2f, 0x02);
+
+    //
+    // Activate
+    //
+    IoWrite8 (0x2e, 0x30);
+    IoWrite8 (0x2f, 0x01);
+
+  } else {
+
+    //
+    // No National pc87393 SIO is docked, turn off dock power and
+    // disable port switch
+    //
+    // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);
+    // IoWrite8 (0x690, 0);
+
+    //
+    // If no National pc87393, just return
+    //
+    return;
+  }
+}
+
+
+/**
+Check whether the IT8628 SIO present on LPC. If yes, enable its serial
+ports, parallel port, and port 80.
+
+@retval EFI_SUCCESS     Operations performed successfully.
+**/
+STATIC
+VOID
+It8628SioSerialPortInit (
+  VOID
+  )
+{
+  UINT8   ChipId0              = 0;
+  UINT8   ChipId1              = 0;
+  UINT16  LpcIoDecondeRangeSet = 0;
+  UINT16  LpcIoDecoodeSet      = 0;
+  UINT8   Index;
+  UINTN   LpcBaseAddr;
+
+
+  //
+  // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh.
+  //
+  LpcBaseAddr = MmPciBase (
+                  DEFAULT_PCI_BUS_NUMBER_PCH,
+                  PCI_DEVICE_NUMBER_PCH_LPC,
+                  PCI_FUNCTION_NUMBER_PCH_LPC
+                  );
+
+  LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD);
+  LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE);
+  MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8)));
+  MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE)));
+
+  //
+  // Enter MB PnP Mode
+  //
+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87);
+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01);
+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);
+
+  //
+  // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)
+  //
+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);
+  ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);
+  ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+  //
+  // Enable Serial Port 1, Port 2
+  //
+  if ((ChipId0 == 0x86) && (ChipId1 == 0x28)) {
+    for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) {
+      IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register);
+      IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value);
+    }
+  }
+
+  //
+  // Exit MB PnP Mode
+  //
+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02);
+  IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02);
+
+  return;
+}
+
+
+/**
+  Performs platform specific initialization required for the CPU to access
+  the hardware associated with a SerialPortLib instance.  This function does
+  not initialize the serial port hardware itself.  Instead, it initializes
+  hardware devices that are required for the CPU to access the serial port
+  hardware.  This function may be called more than once.
+
+  @retval RETURN_SUCCESS       The platform specific initialization succeeded.
+  @retval RETURN_DEVICE_ERROR  The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+  VOID
+  )
+{
+  UINT16  ConfigPort;
+  UINT16  IndexPort;
+  UINT16  DataPort;
+  UINT16  DeviceId;
+  UINT8   Index;
+  UINT16  AcpiBase;
+
+  //
+  // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit
+  // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use.
+  //
+  IndexPort = 0;
+  DataPort = 0;
+  Index = 0;
+  AcpiBase = 0;
+  PchAcpiBaseGet (&AcpiBase);
+  if (AcpiBase == 0) {
+    PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
+  }
+
+  //
+  // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+  //
+  PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+  PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+  // Configure Sio IT8628
+  It8628SioSerialPortInit ();
+
+  DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID);
+  if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {
+    //
+    // if no EC, it is SV Bidwell Bar board
+    //
+    if ((IoRead8 (0x66) != 0xFF) && (IoRead8 (0x62) != 0xFF)) {
+      //
+      // Super I/O initialization for SMSC SI1007
+      //
+      ConfigPort = FixedPcdGet16 (PcdLpcSioConfigDefaultPort);
+      DataPort   = PcdGet16 (PcdLpcSioDataDefaultPort);
+      IndexPort  = PcdGet16 (PcdLpcSioIndexDefaultPort);
+
+      //
+      // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
+      //
+      PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x10);
+
+      //
+      // Program and Enable Default Super IO Configuration Port Addresses and range
+      //
+      PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
+
+      //
+      // Enter Config Mode
+      //
+      IoWrite8 (ConfigPort, 0x55);
+
+      //
+      // Check for SMSC SIO1007
+      //
+      IoWrite8 (IndexPort, 0x0D);   // SMSC SIO1007 Device ID register is 0x0D
+      if (IoRead8 (DataPort) == 0x20) {   // SMSC SIO1007 Device ID is 0x20
+        //
+        // Configure SIO
+        //
+        for (Index = 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
+          IoWrite8 (IndexPort, mSioTable[Index].Register);
+          IoWrite8 (DataPort, mSioTable[Index].Value);
+        }
+
+        //
+        // Exit Config Mode
+        //
+        IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
+
+        //
+        // GPIO 15-17:IN  10-14:OUT  Enable RS232  ref: Page42 of CRB_SCH
+        //
+        IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f);
+      }
+
+      //
+      // Check if a National Pc87393 SIO is docked
+      //
+      CheckNationalSio ();
+
+      //
+      // Super I/O initialization for SMSC SIO1000
+      //
+      ConfigPort = PcdGet16 (PcdLpcSioIndexPort);
+      IndexPort  = PcdGet16 (PcdLpcSioIndexPort);
+      DataPort   = PcdGet16 (PcdLpcSioDataPort);
+
+      //
+      // Enter Config Mode
+      //
+      IoWrite8 (ConfigPort, 0x55);
+
+      //
+      // Check for SMSC SIO1000
+      //
+      if (IoRead8 (ConfigPort) != 0xFF) {
+        //
+        // Configure SIO
+        //
+        for (Index = 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI_SIO_TABLE); Index++) {
+          IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register);
+          IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value);
+        }
+
+        //
+        // Exit Config Mode
+        //
+        IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
+      }
+
+      //
+      // Super I/O initialization for Winbond WPCN381U
+      //
+      IndexPort  = LPC_SIO_INDEX_DEFAULT_PORT_2;
+      DataPort   = LPC_SIO_DATA_DEFAULT_PORT_2;
+
+      //
+      // Check for Winbond WPCN381U
+      //
+      IoWrite8 (IndexPort, 0x20);         // Winbond WPCN381U Device ID register is 0x20
+      if (IoRead8 (DataPort) == 0xF4) {   // Winbond WPCN381U Device ID is 0xF4
+        //
+        // Configure SIO
+        //
+        for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
+          IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
+          IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
+        }
+      }
+    } //EC is not exist, skip mobile board detection for SV board
+
+    //
+    //add for SV Bidwell Bar board
+    //
+    if (IoRead8 (COM1_BASE) == 0xFF) {
+      //
+      // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC)
+      // Looking for LDC2 card first
+      //
+      IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);
+      if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) == 0x55) {
+        IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
+        DataPort  = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
+      } else {
+        IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
+        DataPort  = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
+      }
+
+      IoWrite8 (IndexPort, 0x20);         // Winbond x374 Device ID register is 0x20
+      if (IoRead8 (DataPort) == 0xF1) {   // Winbond x374 Device ID is 0xF1
+        for (Index = 0; Index < sizeof (mSioTableWinbondX374) / sizeof (EFI_SIO_TABLE); Index++) {
+          IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register);
+          IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value);
+        }
+      }
+    }// end of Bidwell Bar SIO initialization
+  } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) ||  IS_SA_DEVICE_ID_SERVER (DeviceId)) {
+    //
+    // If we are in debug mode, we will allow serial status codes
+    //
+
+    //
+    // National PC8374 SIO & Winbond WPCD374 (LDC2)
+    //
+    IndexPort  = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
+
+    IoWrite8 (IndexPort, 0x55);
+    if (IoRead8 (IndexPort) == 0x55) {
+      IndexPort = LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;
+      DataPort  = LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;
+    } else {
+      IndexPort = LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;
+      DataPort  = LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;
+    }
+
+    //
+    // Configure SIO
+    //
+    IoWrite8 (IndexPort, 0x20);         // Winbond x374 Device ID register is 0x20
+    if (IoRead8 (DataPort) == 0xF1) {   // Winbond x374 Device ID is 0xF1
+      for (Index = 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SIO_TABLE); Index++) {
+        IoWrite8 (IndexPort, mDesktopSioTable[Index].Register);
+        //PrePpiStall (200);
+        IoWrite8 (DataPort, mDesktopSioTable[Index].Value);
+        //PrePpiStall (200);
+      }
+      return RETURN_SUCCESS;
+    }
+    //
+    // Configure Pilot3 SIO
+    //
+    IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mode.
+    IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG);     // Pilot3 SIO Device ID register is 0x20.
+    if (IoRead8 (PILOTIII_SIO_DATA_PORT) == PILOTIII_CHIP_ID) {    // Pilot3 SIO Device ID register is 0x03.
+      //
+      // Configure SIO
+      //
+      for (Index = 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO_TABLE); Index++) {
+        IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register);
+        IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value);
+      }
+    }
+    IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode.
+  }
+
+
+  return RETURN_SUCCESS;
+}

+ 57 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf

@@ -0,0 +1,57 @@
+### @file
+# Platform Hook Library instance for SandyBridge Mobile/Desktop CRB.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = BasePlatformHookLib
+  FILE_GUID                      = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  MmPciLib
+  PciLib
+  PchCycleDecodingLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress                         ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort                ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort                 ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort         ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort          ## CONSUMES
+
+[FixedPcd]
+  gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort        ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSioBaseAddress                 ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange               ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding            ## CONSUMES
+
+[Sources]
+  BasePlatformHookLib.c

+ 42 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c

@@ -0,0 +1,42 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardUpdateAcpiTable (
+  IN OUT EFI_ACPI_COMMON_HEADER       *Table,
+  IN OUT EFI_ACPI_TABLE_VERSION       *Version
+  );
+
+EFI_STATUS
+EFIAPI
+BoardUpdateAcpiTable (
+  IN OUT EFI_ACPI_COMMON_HEADER       *Table,
+  IN OUT EFI_ACPI_TABLE_VERSION       *Version
+  )
+{
+  KabylakeRvp3BoardUpdateAcpiTable (Table, Version);
+
+  return EFI_SUCCESS;
+}
+

+ 53 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf

@@ -0,0 +1,53 @@
+### @file
+# Platform Hook Library instance for SandyBridge Mobile/Desktop CRB.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = DxeBoardAcpiTableLib
+  FILE_GUID                      = 6562E0AE-90D8-4D41-8C97-81286B4BE7D2
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = BoardAcpiTableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  PciLib
+  AslUpdateLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable
+  gPlatformModuleTokenSpaceGuid.PcdPciExpNative
+  gPlatformModuleTokenSpaceGuid.PcdNativeAspmEnable
+  gPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle
+  gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
+  
+[Sources]
+  DxeKabylakeRvp3AcpiTableLib.c
+  DxeBoardAcpiTableLib.c
+

+ 80 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c

@@ -0,0 +1,80 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/AslUpdateLib.h>
+#include <Protocol/GlobalNvsArea.h>
+
+#include <KabylakeRvp3Id.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL              mGlobalNvsArea;
+
+VOID
+KabylakeRvp3UpdateGlobalNvs (
+  VOID
+  )
+{
+
+  //
+  // Allocate and initialize the NVS area for SMM and ASL communication.
+  //
+  mGlobalNvsArea.Area = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress);
+
+  //
+  // Update global NVS area for ASL and SMM init code to use
+  //
+
+  //
+  // Enable PowerState
+  //
+  mGlobalNvsArea.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c
+
+  mGlobalNvsArea.Area->NativePCIESupport        = PcdGet8 (PcdPciExpNative);
+  
+  //
+  // Enable APIC
+  //
+  mGlobalNvsArea.Area->ApicEnable = GLOBAL_NVS_DEVICE_ENABLE;
+
+  //
+  // Low Power S0 Idle - Enabled/Disabled
+  //
+  mGlobalNvsArea.Area->LowPowerS0Idle = PcdGet8 (PcdLowPowerS0Idle);
+
+  mGlobalNvsArea.Area->Ps2MouseEnable     = FALSE;
+  mGlobalNvsArea.Area->Ps2KbMsEnable      = PcdGet8 (PcdPs2KbMsEnable);
+}
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardUpdateAcpiTable (
+  IN OUT EFI_ACPI_COMMON_HEADER       *Table,
+  IN OUT EFI_ACPI_TABLE_VERSION       *Version
+  )
+{
+  if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+    KabylakeRvp3UpdateGlobalNvs ();
+  }
+
+  return EFI_SUCCESS;
+}
+

+ 49 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c

@@ -0,0 +1,49 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <KabylakeRvp3Id.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardUpdateAcpiTable (
+  IN OUT EFI_ACPI_COMMON_HEADER       *Table,
+  IN OUT EFI_ACPI_TABLE_VERSION       *Version
+  );
+
+BOARD_ACPI_TABLE_FUNC  mKabylakeRvp3BoardAcpiTableFunc = {
+  KabylakeRvp3BoardUpdateAcpiTable
+};
+
+EFI_STATUS
+EFIAPI
+DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor (
+  VOID
+  )
+{
+  if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
+    return RegisterBoardAcpiTableFunc (&mKabylakeRvp3BoardAcpiTableFunc);
+  }
+  return EFI_SUCCESS;
+}
+

+ 54 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf

@@ -0,0 +1,54 @@
+### @file
+# Platform Hook Library instance for SandyBridge Mobile/Desktop CRB.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = DxeKabylakeRvp3MultiBoardAcpiTableLib
+  FILE_GUID                      = 8E6A3B38-53E0-48C0-970F-058F380FCB80
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  PciLib
+  AslUpdateLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable
+  gPlatformModuleTokenSpaceGuid.PcdPciExpNative
+  gPlatformModuleTokenSpaceGuid.PcdNativeAspmEnable
+  gPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle
+  gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
+  
+[Sources]
+  DxeKabylakeRvp3AcpiTableLib.c
+  DxeMultiBoardAcpiSupportLib.c
+

+ 68 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c

@@ -0,0 +1,68 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+  IN BOOLEAN  EnableSci
+  );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+  IN BOOLEAN  DisableSci
+  );
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  )
+{
+  SiliconEnableAcpi (EnableSci);
+  return KabylakeRvp3BoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  )
+{
+  SiliconDisableAcpi (DisableSci);
+  return KabylakeRvp3BoardDisableAcpi (DisableSci);
+}
+
+

+ 53 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf

@@ -0,0 +1,53 @@
+### @file
+# Platform Hook Library instance for SandyBridge Mobile/Desktop CRB.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = SmmBoardAcpiEnableLib
+  FILE_GUID                      = 549E69AE-D3B3-485B-9C17-AF16E20A58AD
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = BoardAcpiEnableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  PciLib
+  MmPciLib
+  PchCycleDecodingLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition   ## CONSUMES
+  
+[Protocols]
+
+[Sources]
+  SmmKabylakeRvp3AcpiEnableLib.c
+  SmmSiliconAcpiEnableLib.c
+  SmmBoardAcpiEnableLib.c
+

+ 45 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c

@@ -0,0 +1,45 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <KabylakeRvp3Id.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  )
+{
+  // enable additional board register
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  )
+{
+  // enable additional board register
+  return EFI_SUCCESS;
+}
+

+ 87 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c

@@ -0,0 +1,87 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <KabylakeRvp3Id.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+  IN BOOLEAN  EnableSci
+  );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+  IN BOOLEAN  DisableSci
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3MultiBoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  )
+{
+  SiliconEnableAcpi (EnableSci);
+  return KabylakeRvp3BoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3MultiBoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  )
+{
+  SiliconDisableAcpi (DisableSci);
+  return KabylakeRvp3BoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC  mKabylakeRvp3BoardAcpiEnableFunc = {
+  KabylakeRvp3MultiBoardEnableAcpi,
+  KabylakeRvp3MultiBoardDisableAcpi,
+};
+
+EFI_STATUS
+EFIAPI
+SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor (
+  VOID
+  )
+{
+  if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
+    return RegisterBoardAcpiEnableFunc (&mKabylakeRvp3BoardAcpiEnableFunc);
+  }
+  return EFI_SUCCESS;
+}
+

+ 54 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf

@@ -0,0 +1,54 @@
+### @file
+# Platform Hook Library instance for SandyBridge Mobile/Desktop CRB.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = SmmKabylakeRvp3MultiBoardAcpiSupportLib
+  FILE_GUID                      = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  PciLib
+  MmPciLib
+  PchCycleDecodingLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition   ## CONSUMES
+  
+[Protocols]
+
+[Sources]
+  SmmKabylakeRvp3AcpiEnableLib.c
+  SmmSiliconAcpiEnableLib.c
+  SmmMultiBoardAcpiSupportLib.c
+

+ 174 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c

@@ -0,0 +1,174 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PchAccess.h>
+#include <Library/MmPciLib.h>
+#include <Library/PchCycleDecodingLib.h>
+
+/**
+  Clear Port 80h
+
+  SMI handler to enable ACPI mode
+
+  Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+  Disables the SW SMI Timer.
+  ACPI events are disabled and ACPI event status is cleared.
+  SCI mode is then enabled.
+
+  Clear SLP SMI status
+  Enable SLP SMI
+
+  Disable SW SMI Timer
+
+  Clear all ACPI event status and disable all ACPI events
+
+  Disable PM sources except power button
+  Clear status bits
+
+  Disable GPE0 sources
+  Clear status bits
+
+  Disable GPE1 sources
+  Clear status bits
+
+  Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+  Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+  IN BOOLEAN  EnableSci
+  )
+{
+  UINT32                              OutputValue;
+  UINT32                              SmiEn;
+  UINT32                              SmiSts;
+  UINT32                              ULKMC;
+  UINTN                               LpcBaseAddress;
+  UINT16                              AcpiBaseAddr;
+  UINT32                              Pm1Cnt;
+
+  LpcBaseAddress = MmPciBase (
+                     DEFAULT_PCI_BUS_NUMBER_PCH,
+                     PCI_DEVICE_NUMBER_PCH_LPC,
+                     PCI_FUNCTION_NUMBER_PCH_LPC
+                     );
+  
+  //
+  // Get the ACPI Base Address
+  //
+  PchAcpiBaseGet (&AcpiBaseAddr);
+
+  //
+  // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+  // OS in order to prevent the host from issuing global resets and resetting ME
+  //
+  // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+  // MmioWrite32 (
+  //     PmcBaseAddress + R_PCH_PMC_ETR3),
+  //     PmInit);
+
+  //
+  // Clear Port 80h
+  //
+  IoWrite8 (0x80, 0);
+
+  //
+  // Disable SW SMI Timer and clean the status
+  //
+  SmiEn = IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN);
+  SmiEn &= ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB);
+  IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn);
+
+  SmiSts = IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS);
+  SmiSts |= B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB;
+  IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts);
+
+  //
+  // Disable port 60/64 SMI trap if they are enabled
+  //
+  ULKMC = MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN | B_PCH_LPC_ULKMC_A20PASSEN);
+  MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC);
+
+  //
+  // Disable PM sources except power button
+  //
+  IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
+
+  //
+  // Clear PM status except Power Button status for RapidStart Resume
+  //
+  IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF);
+
+  //
+  // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+  //
+  IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD);
+  IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0);
+
+  //
+  // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+  //
+  OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
+  OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
+  IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
+  
+
+  //
+  // Enable SCI
+  //
+  if (EnableSci) {
+    Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
+    Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
+    IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+  IN BOOLEAN  DisableSci
+  )
+{
+  UINT16                              AcpiBaseAddr;
+  UINT32                              Pm1Cnt;
+  
+  //
+  // Get the ACPI Base Address
+  //
+  PchAcpiBaseGet (&AcpiBaseAddr);
+
+  //
+  // Disable SCI
+  //
+  if (DisableSci) {
+    Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
+    Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
+    IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
+  }
+
+  return EFI_SUCCESS;
+}

+ 387 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3GpioTable.c

@@ -0,0 +1,387 @@
+/** @file
+  GPIO definition table for KabylakeRvp3
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _KABYLAKE_RVP3_GPIO_TABLE_H_
+#define _KABYLAKE_RVP3_GPIO_TABLE_H_
+
+#include <PiPei.h>
+#include <GpioPinsSklLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+#include <IoExpander.h>
+
+
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
+{
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//H_RCIN_N
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//LPC_FRAME_ESPI_CS_N
+//skip for eSPI function  {GPIO_SKL_LP_GPP_A6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//INT_SERIRQ
+  {GPIO_SKL_LP_GPP_A7,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SLP_S0ix_R_N
+// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_CLKRUN_N
+//skip for eSPI function    {GPIO_SKL_LP_GPP_A9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
+// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//PCH_CLK_PCI_TPM
+  {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//EC_HID_INTR
+  {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,    GpioIntDis, GpioResumeReset,  GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
+//skip for SUS_PWR_ACK_R  {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SUS_PWR_ACK_R
+//skip for eSPI function    {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
+//skip for SUSACK_R_N  {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SUSACK_R_N
+  {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_1P8_SEL
+  {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_PWR_EN_N
+  {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_0_SENSOR
+  {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_1_SENSOR
+  {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_GP_2_SENSOR
+  {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GNSS_CHUB_IRQ
+  {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//FPS_SLP_N
+  {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//FPS_DRDY
+  {GPIO_SKL_LP_GPP_B0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID0
+  {GPIO_SKL_LP_GPP_B1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//V0.85A_VID1
+  {GPIO_SKL_LP_GPP_B2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//GP_VRALERTB
+  {GPIO_SKL_LP_GPP_B3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,  GpioTermNone}},//TCH_PAD_INTR_R_N
+  {GPIO_SKL_LP_GPP_B4,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//BT_RF_KILL_N
+  {GPIO_SKL_LP_GPP_B5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_BT_UART_WAKE_N
+  // {GPIO_SKL_LP_GPP_B6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT1_N
+  // {GPIO_SKL_LP_GPP_B7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
+  // {GPIO_SKL_LP_GPP_B8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
+  // {GPIO_SKL_LP_GPP_B9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
+  // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CLK_REQ_M.2_WLAN_N
+  {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//MPHY_EXT_PWR_GATEB
+  {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SLP_S0_N
+  {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PLT_RST_N
+  {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_PWREN
+  // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_DFU, NOT OWNED BY BIOS
+  {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
+  {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset,  GpioTermWpu20K}},//TBT_CIO_PLUG_EVENT_N
+  {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
+  {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,   GpioTermNone}},//FPS_GSPI1_CS_R1_N
+  {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
+  {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
+  {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
+  {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
+  {GPIO_SKL_LP_GPP_C0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SMB_CLK
+  {GPIO_SKL_LP_GPP_C1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SMB_DATA
+  {GPIO_SKL_LP_GPP_C2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
+  {GPIO_SKL_LP_GPP_C3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_CLK
+  {GPIO_SKL_LP_GPP_C4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML0_DATA
+  {GPIO_SKL_LP_GPP_C5,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
+  {GPIO_SKL_LP_GPP_C6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SML1_CLK, OWNED BY ME
+  {GPIO_SKL_LP_GPP_C7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//SML1_DATA, OWNED BY ME
+  {GPIO_SKL_LP_GPP_C8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RXD
+  {GPIO_SKL_LP_GPP_C9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_TXD
+  {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_RTS_N
+  {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART0_CTS_N
+  {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
+  {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
+  {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
+  {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
+  {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SDA
+  {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C0_SCL
+  {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SDA
+  {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_I2C1_SCL
+  {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RXD
+  {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_TXD
+  {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_RTS_N
+  {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SERIALIO_UART2_CTS_N
+  {GPIO_SKL_LP_GPP_D0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CS_N
+  {GPIO_SKL_LP_GPP_D1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_CLK
+  {GPIO_SKL_LP_GPP_D2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MISO
+  {GPIO_SKL_LP_GPP_D3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_MOSI
+  {GPIO_SKL_LP_GPP_D4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//CSI2_FLASH_STROBE
+  {GPIO_SKL_LP_GPP_D5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SDA
+  {GPIO_SKL_LP_GPP_D6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C0_SCL
+  {GPIO_SKL_LP_GPP_D7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SDA
+  {GPIO_SKL_LP_GPP_D8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_I2C1_SCL
+  {GPIO_SKL_LP_GPP_D9,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//HOME_BTN
+  {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SCREEN_LOCK_PCH
+  {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_UP_PCH
+  {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//VOL_DOWN_PCH
+  {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
+  {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
+  {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_RTS_N
+  {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
+  {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_1
+  {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DMIC_DATA_1
+  {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DMIC_CLK_0
+  {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DMIC_DATA_0
+  {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO2
+  {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SPI1_TCHPNL_IO3
+  {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP_MCLK
+  {GPIO_SKL_LP_GPP_E0,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//SPI_TPM_HDR_IRQ_N
+  {GPIO_SKL_LP_GPP_E1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA_ODD_PRSNT_N
+  {GPIO_SKL_LP_GPP_E2,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
+  {GPIO_SKL_LP_GPP_E3,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioResumeReset,  GpioTermNone}},//EINK_SSR_DFU_N
+  {GPIO_SKL_LP_GPP_E4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_RESET
+  {GPIO_SKL_LP_GPP_E5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
+  // {GPIO_SKL_LP_GPP_E6,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutLow,     GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS
+  {GPIO_SKL_LP_GPP_E8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_SATA_LED_N
+  {GPIO_SKL_LP_GPP_E9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_0_WP1_OTG_N
+  {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_1_WP4_N
+  {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
+  // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS
+  {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_HPD_Q
+  {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_HPD_Q
+  {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset,  GpioTermNone}},//SMC_EXTSMI_R_N
+  {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio,    GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset,  GpioTermNone}},//SMC_RUNTIME_SCI_R_N
+  {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EDP_HPD
+  {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI1_CTRL_CLK
+  {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI1_CTRL_DATA
+  {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//DDI2_CTRL_CLK
+  {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//DDI2_CTRL_DATA
+  {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_CODEC_IRQ
+  {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,   GpioOutHigh,    GpioIntDis, GpioHostDeepReset,  GpioTermWpd20K}},//TCH_PNL_RST_N
+  {GPIO_SKL_LP_GPP_F0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SCLK
+  {GPIO_SKL_LP_GPP_F1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_SFRM
+  {GPIO_SKL_LP_GPP_F2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_TXD
+  {GPIO_SKL_LP_GPP_F3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SSP2_RXD
+  {GPIO_SKL_LP_GPP_F4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
+  {GPIO_SKL_LP_GPP_F5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
+  {GPIO_SKL_LP_GPP_F6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
+  {GPIO_SKL_LP_GPP_F7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
+  {GPIO_SKL_LP_GPP_F8,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
+  {GPIO_SKL_LP_GPP_F9,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
+  {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
+  {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
+  {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CMD
+  {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA0
+  {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA1
+  {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA2
+  {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA3
+  {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA4
+  {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA5
+  {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA6
+  {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_DATA7
+  {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_RCLK
+  {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//EMMC_CLK
+  {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
+  {GPIO_SKL_LP_GPP_G0,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CMD
+  {GPIO_SKL_LP_GPP_G1,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA0
+  {GPIO_SKL_LP_GPP_G2,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA1
+  {GPIO_SKL_LP_GPP_G3,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA2
+  {GPIO_SKL_LP_GPP_G4,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_DATA3
+  {GPIO_SKL_LP_GPP_G5,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CDB
+  {GPIO_SKL_LP_GPP_G6,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_CLK
+  {GPIO_SKL_LP_GPP_G7,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioHostDeepReset,  GpioTermNone}},//SD_WP
+  {GPIO_SKL_LP_GPD0,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_BATLOW_R_N
+  {GPIO_SKL_LP_GPD1,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//AC_PRESENT_R
+  {GPIO_SKL_LP_GPD2,   {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset,  GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
+  {GPIO_SKL_LP_GPD3,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermWpu20K}},//PM_PWRBTN_R_N
+  {GPIO_SKL_LP_GPD4,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S3_R_N
+  {GPIO_SKL_LP_GPD5,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S4_R_N
+  {GPIO_SKL_LP_GPD6,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_M_R_N
+  {GPIO_SKL_LP_GPD7,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
+  {GPIO_SKL_LP_GPD8,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SUS_CLK
+  {GPIO_SKL_LP_GPD9,   {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PCH_SLP_WLAN_N
+  {GPIO_SKL_LP_GPD10,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//SLP_S5_R_N
+  {GPIO_SKL_LP_GPD11,  {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//PM_LANPHY_ENABLE
+  {END_OF_GPIO_TABLE,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//Marking End of Table
+};
+
+UINT16 mGpioTableLpDdr3Rvp3Size = sizeof (mGpioTableLpDdr3Rvp3) / sizeof (GPIO_INIT_CONFIG) - 1;
+
+GPIO_INIT_CONFIG mGpioTableKabyLakeYLpddr3Rvp3[] =
+{
+  { GPIO_SKL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone } },//REALSENSE_ISH_WAKE
+  { GPIO_SKL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//IRIS_PROXI_INTR
+  { GPIO_SKL_LP_GPP_D9,  { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirOut,  GpioOutHigh,    GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
+  { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone } },//SD_CARD_WAKE
+  { GPIO_SKL_LP_GPP_D11, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_P1_DCI_CLK
+  { GPIO_SKL_LP_GPP_D12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_P1_DCI_DATA
+};
+
+UINT16 mGpioTableKabyLakeYLpddr3Rvp3Size = sizeof (mGpioTableKabyLakeYLpddr3Rvp3) / sizeof (GPIO_INIT_CONFIG);
+
+GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[] =
+{
+    { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B0
+    { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone } }, //GPP_B1
+};
+
+UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize = sizeof (mGpioTableLpddr3Rvp3UcmcDevice) / sizeof (GPIO_INIT_CONFIG);
+
+GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel =
+  {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,  GpioTermNone}};
+
+GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3SdhcSidebandCardDetect =
+  {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset,  GpioTermNone}}; //SD_CDB D3
+
+//IO Expander Table for SKL RVP7, RVP13 and RVP15
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =
+{
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_8,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_9,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}//M.2_WIGIG_PWREN_IOEXP
+};
+
+UINT16 mGpioTableIoExpanderSize = sizeof (mGpioTableIoExpander) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+
+//IO Expander Table for KBL -Refresh
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =
+{
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_8,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_9,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//Unused pin
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RTD3_USB_PD1_PWR_EN
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//HRESET_PD1_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+  //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
+  // We want the initial state to be high.
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_WAKE_CTRL_R_N
+  // Turn off WWAN power and will turn it on later.
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
+};
+UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 = sizeof (mGpioTableIoExpanderKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+
+//IO Expander Table for KBL -kc
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =
+{
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_8,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_9,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_8,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_9,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_FLEX_PWREN
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB_UART_SEL
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_DOCK_PWREN_IOEXP_R
+};
+UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 = sizeof (mGpioTableIoExpanderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+//IO Expander Table Full table for KBL RVP3
+IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRvp3[] =
+{
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_8,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_9,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD)
+//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD)
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26
+  {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_0,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_1,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_2,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_INPUT,  IO_EXPANDER_GPO_LEVEL_LOW,  IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED },//Not Connected (KBK_RVP3_BOARD)
+//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD)
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_4,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_5,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_6,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_7,  IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN (KBL_RVP3_BOARD)
+  {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N  (KBL_RVP3_BOARD)
+};
+
+UINT16 mGpioTableIoExpanderKabylakeRvp3Size = sizeof (mGpioTableIoExpanderKabylakeRvp3) / sizeof (IO_EXPANDER_GPIO_CONFIG);
+
+#endif // _KABYLAKE_RVP3_GPIO_TABLE_H_

+ 238 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3HdaVerbTables.c

@@ -0,0 +1,238 @@
+/** @file
+  HDA Verb table for KabylakeRvp3
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _KABYLAKE_RVP3_HDA_VERB_TABLES_H_
+#define _KABYLAKE_RVP3_HDA_VERB_TABLES_H_
+
+#include <Ppi/SiPolicy.h>
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 = HDAUDIO_VERB_TABLE_INIT (
+  //
+  //  VerbTable: (Realtek ALC286) for RVP3
+  //  Revision ID = 0xff
+  //  Codec Verb Table for SKL PCH boards
+  //  Codec Address: CAd value (0/1/2)
+  //  Codec Vendor: 0x10EC0286
+  //
+  0x10EC, 0x0286,
+  0xFF, 0xFF,
+  //===================================================================================================
+  //
+  //                               Realtek Semiconductor Corp.
+  //
+  //===================================================================================================
+
+  //Realtek High Definition Audio Configuration - Version : 5.0.2.9
+  //Realtek HD Audio Codec : ALC286
+  //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+  //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E
+  //The number of verb command block : 16
+
+  //    NID 0x12 : 0x411111F0
+  //    NID 0x13 : 0x40000000
+  //    NID 0x14 : 0x9017011F
+  //    NID 0x17 : 0x90170110
+  //    NID 0x18 : 0x03A11040
+  //    NID 0x19 : 0x411111F0
+  //    NID 0x1A : 0x411111F0
+  //    NID 0x1D : 0x4066A22D
+  //    NID 0x1E : 0x411111F0
+  //    NID 0x21 : 0x03211020
+
+
+  //===== HDA Codec Subsystem ID Verb-table =====
+  //HDA Codec Subsystem ID  : 0x10EC108E
+  0x0017208E,
+  0x00172110,
+  0x001722EC,
+  0x00172310,
+
+  //===== Pin Widget Verb-table =====
+  //Widget node 0x01 :
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  //Pin widget 0x12 - DMIC
+  0x01271CF0,
+  0x01271D11,
+  0x01271E11,
+  0x01271F41,
+  //Pin widget 0x13 - DMIC
+  0x01371C00,
+  0x01371D00,
+  0x01371E00,
+  0x01371F40,
+  //Pin widget 0x14 - SPEAKER-OUT (Port-D)
+  0x01771C1F,
+  0x01771D01,
+  0x01771E17,
+  0x01771F90,
+  //Pin widget 0x17 - I2S-OUT
+  0x01771C10,
+  0x01771D01,
+  0x01771E17,
+  0x01771F90,
+  //Pin widget 0x18 - MIC1 (Port-B)
+  0x01871C40,
+  0x01871D10,
+  0x01871EA1,
+  0x01871F03,
+  //Pin widget 0x19 - I2S-IN
+  0x01971CF0,
+  0x01971D11,
+  0x01971E11,
+  0x01971F41,
+  //Pin widget 0x1A - LINE1 (Port-C)
+  0x01A71CF0,
+  0x01A71D11,
+  0x01A71E11,
+  0x01A71F41,
+  //Pin widget 0x1D - PC-BEEP
+  0x01D71C2D,
+  0x01D71DA2,
+  0x01D71E66,
+  0x01D71F40,
+  //Pin widget 0x1E - S/PDIF-OUT
+  0x01E71CF0,
+  0x01E71D11,
+  0x01E71E11,
+  0x01E71F41,
+  //Pin widget 0x21 - HP-OUT (Port-A)
+  0x02171C20,
+  0x02171D10,
+  0x02171E21,
+  0x02171F03,
+  //Widget node 0x20 :
+  0x02050071,
+  0x02040014,
+  0x02050010,
+  0x02040C22,
+  //Widget node 0x20 - 1 :
+  0x0205004F,
+  0x02045029,
+  0x0205004F,
+  0x02045029,
+  //Widget node 0x20 - 2 :
+  0x0205002B,
+  0x02040DD0,
+  0x0205002D,
+  0x02047020,
+  //Widget node 0x20 - 3 :
+  0x0205000E,
+  0x02046C80,
+  0x01771F90,
+  0x01771F90,
+  //TI AMP settings :
+  0x02050022,
+  0x0204004C,
+  0x02050023,
+  0x02040000,
+  0x02050025,
+  0x02040000,
+  0x02050026,
+  0x0204B010,
+
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+
+  0x02050022,
+  0x0204004C,
+  0x02050023,
+  0x02040002,
+  0x02050025,
+  0x02040011,
+  0x02050026,
+  0x0204B010,
+
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+
+  0x02050022,
+  0x0204004C,
+  0x02050023,
+  0x0204000D,
+  0x02050025,
+  0x02040010,
+  0x02050026,
+  0x0204B010,
+
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+
+  0x02050022,
+  0x0204004C,
+  0x02050023,
+  0x02040025,
+  0x02050025,
+  0x02040008,
+  0x02050026,
+  0x0204B010,
+
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+
+  0x02050022,
+  0x0204004C,
+  0x02050023,
+  0x02040002,
+  0x02050025,
+  0x02040000,
+  0x02050026,
+  0x0204B010,
+
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+  0x000F0000,
+
+  0x02050022,
+  0x0204004C,
+  0x02050023,
+  0x02040003,
+  0x02050025,
+  0x02040000,
+  0x02050026,
+  0x0204B010
+);
+
+#endif // _KABYLAKE_RVP3_HDA_VERB_TABLES_H_

+ 111 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3HsioPtssTables.c

@@ -0,0 +1,111 @@
+/** @file
+    KabylakeRvp3 HSIO PTSS H File
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef KABYLAKE_RVP3_HSIO_PTSS_H_
+#define KABYLAKE_RVP3_HSIO_PTSS_H_
+
+#include <PchHsioPtssTables.h>
+
+#ifndef HSIO_PTSS_TABLE_SIZE
+#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES)
+#endif
+
+//BoardId KabylakeRvp3
+HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[] = {
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoM2},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+  {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+  {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchSataTopoM2},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect},
+  {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoM2},
+  {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+  {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown}
+};
+
+UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size = sizeof(PchLpHsioPtss_Cx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES);
+
+HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[] = {
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchPcieTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F000000}, PchSataTopoDirectConnect},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F000000}, PchSataTopoUnknown},
+  {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopox4},
+  {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+  {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}, PchPcieTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}, PchSataTopoDirectConnect},
+  {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopox1},
+  {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0000}, PchPcieTopoUnknown},
+  {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+  {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, PchSataTopoUnknown},
+};
+
+UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size = sizeof(PchLpHsioPtss_Bx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES);
+
+#endif // KABYLAKE_RVP3_HSIO_PTSS_H_

+ 432 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/KabylakeRvp3SpdTable.c

@@ -0,0 +1,432 @@
+/** @file
+  GPIO definition table for KabylakeRvp3
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _KABYLAKE_RVP3_SPD_TABLE_H_
+#define _KABYLAKE_RVP3_SPD_TABLE_H_
+
+//
+// DQByteMap[0] - ClkDQByteMap:
+//   If clock is per rank, program to [0xFF, 0xFF]
+//   If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+//   If clock is shared by 2 ranks but does not go to all bytes,
+//           Entry[i] defines which DQ bytes Group i services
+// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
+// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
+// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
+//                For DDR, DQByteMap[3:1] = [0xFF, 0]
+// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
+//                               Variable only exists to make the code easier to use
+// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
+//                               Variable only exists to make the code easier to use
+//
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL SDS - used by SKL/KBL MRC
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] = {
+  // Channel 0:
+  {
+    { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+    { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+    { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+    { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+    { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+    { 0xFF, 0x00 }  // CA Vref is one for all bytes
+  },
+  // Channel 1:
+  {
+    { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+    { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+    { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+    { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+    { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+    { 0xFF, 0x00 }  // CA Vref is one for all bytes
+  }
+};
+
+//
+// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP
+//
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] = {
+  { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
+  { 1, 0, 4, 5, 2, 3, 6, 7 }  // Channel 1
+};
+
+// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16
+// or Hynix H9CCNNNBLTALAR-NUD
+// or similar
+// 1867, 14-17-17-40
+// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb = 4GB total per channel
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] = {
+  0x24,                                 ///< 0   Number of Serial PD Bytes Written / SPD Device Size
+  0x20,                                 ///< 1   SPD Revision
+  0x0F,                                 ///< 2   DRAM Device Type
+  0x0E,                                 ///< 3   Module Type
+  0x14,                                 ///< 4   SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density
+  0x12,                                 ///< 5   SDRAM Addressing: 14 Rows, 11 Columns
+  0xB5,                                 ///< 6   SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
+  0x00,                                 ///< 7   SDRAM Optional Features
+  0x00,                                 ///< 8   SDRAM Thermal and Refresh Options
+  0x00,                                 ///< 9   Other SDRAM Optional Features
+  0x00,                                 ///< 10  Reserved - must be coded as 0x00
+  0x03,                                 ///< 11  Module Nominal Voltage, VDD
+  0x0A,                                 ///< 12  Module Organization, SDRAM width: 16 bits, 2 Ranks
+  0x23,                                 ///< 13  Module Memory Bus Width: 2 channels, 64 bit channel bus width
+  0x00,                                 ///< 14  Module Thermal Sensor
+  0x00,                                 ///< 15  Extended Module Type
+  0x00,                                 ///< 16  Reserved - must be coded as 0x00
+  0x00,                                 ///< 17  Timebases
+  0x09,                                 ///< 18  SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071ns (LPDDR3-1867)
+  0xFF,                                 ///< 19  SDRAM Minimum Cycle Time (tCKmax)
+  0xD4,                                 ///< 20  CAS Latencies Supported, First Byte (tCK): 14, 12, 10, 8
+  0x00,                                 ///< 21  CAS Latencies Supported, Second Byte
+  0x00,                                 ///< 22  CAS Latencies Supported, Third Byte
+  0x00,                                 ///< 23  CAS Latencies Supported, Fourth Byte
+  0x78,                                 ///< 24  Minimum CAS Latency Time (tAAmin) = 14.994 ns
+  0x00,                                 ///< 25  Read and Write Latency Set Options
+  0x90,                                 ///< 26  Minimum RAS# to CAS# Delay Time (tRCDmin)
+  0xA8,                                 ///< 27  Minimum Row Precharge Delay Time for all banks (tRPab)
+  0x90,                                 ///< 28  Minimum Row Precharge Delay Time per bank (tRPpb)
+  0x10,                                 ///< 29  Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
+  0x04,                                 ///< 30  Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
+  0xE0,                                 ///< 31  Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
+  0x01,                                 ///< 32  Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
+  0, 0, 0, 0, 0, 0, 0,                  ///< 33 - 39
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 40 - 49
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 50 - 59
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 60 - 69 Connector to SDRAM Bit Mapping
+  0, 0, 0, 0, 0, 0, 0, 0,               ///< 70 - 77 Connector to SDRAM Bit Mapping
+  0, 0,                                 ///< 78 - 79
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 80 - 89
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 90 - 99
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 100 - 109
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 110 - 119
+  0x00,                                 ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
+  0x00,                                 ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
+  0x00,                                 ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  0xFA,                                 ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
+  0x7F,                                 ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax): 32.002 ns
+  0xCA,                                 ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867)
+  0x00,                                 ///< 126 CRC A
+  0x00,                                 ///< 127 CRC B
+  0, 0,                                 ///< 128 - 129
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 130 - 139
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 140 - 149
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 150 - 159
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 160 - 169
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 170 - 179
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 180 - 189
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 190 - 199
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 200 - 209
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 210 - 219
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 220 - 229
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 230 - 239
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 240 - 249
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 250 - 259
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 260 - 269
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 270 - 279
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 280 - 289
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 290 - 299
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 300 - 309
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 310 - 319
+  0x00,                                 ///< 320 Module Manufacturer ID Code, Least Significant Byte
+  0x00,                                 ///< 321 Module Manufacturer ID Code, Most Significant Byte
+  0x00,                                 ///< 322 Module Manufacturing Location
+  0x00,                                 ///< 323 Module Manufacturing Date Year
+  0x00,                                 ///< 324 Module Manufacturing Date Week
+  0x55,                                 ///< 325 Module Serial Number A
+  0x00,                                 ///< 326 Module Serial Number B
+  0x00,                                 ///< 327 Module Serial Number C
+  0x00,                                 ///< 328 Module Serial Number D
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 334 - 338 Module Part Number
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 339 - 343 Module Part Number
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 344 - 348 Module Part Number
+  0x00,                                 ///< 349 Module Revision Code
+  0x00,                                 ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+  0x00,                                 ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+  0x00,                                 ///< 352 DRAM Stepping
+  0, 0, 0, 0, 0, 0, 0,                  ///< 353 - 359
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 360 - 369
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 370 - 379
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 380 - 389
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 390 - 399
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 400 - 409
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 410 - 419
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 420 - 429
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 430 - 439
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 440 - 449
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 450 - 459
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 460 - 469
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 470 - 479
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 480 - 489
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 490 - 499
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 500 - 509
+  0, 0                                  ///< 510 - 511
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize = sizeof (mSkylakeRvp16Spd);
+
+//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die
+//1867
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] = {
+    0x91,                                 ///< 0   Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+    0x20,                                 ///< 1   SPD Revision
+    0xF1,                                 ///< 2   DRAM Device Type
+    0x03,                                 ///< 3   Module Type
+    0x05,                                 ///< 4   SDRAM Density and Banks, 8Gb
+    0x19,                                 ///< 5   SDRAM Addressing: 15 Rows, 10 Columns
+    0x05,                                 ///< 6   Module Nominal Voltage
+    0x0B,                                 ///< 7   Module Organization: 32 bits, 2 Ranks
+    0x03,                                 ///< 8   Module Memory Bus Width
+    0x11,                                 ///< 9   Fine Timebase (FTB) Dividend / Divisor
+    0x01,                                 ///< 10  Medium Timebase (MTB) Dividend
+    0x08,                                 ///< 11  Medium Timebase (MTB) Divisor
+    0x09,                                 ///< 12  SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071 ns (LPDDR3-1867)
+    0x00,                                 ///< 13  Reserved0
+    0x50,                                 ///< 14  CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
+    0x05,                                 ///< 15  CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
+    0x78,                                 ///< 16  Minimum CAS Latency (tAAmin) = 14.994 ns
+    0x78,                                 ///< 17  Minimum Write Recovery Time (tWRmin)
+    0x90,                                 ///< 18  Minimum RAS# to CAS# Delay Time (tRCDmin)
+    0x50,                                 ///< 19  Minimum Row Active to Row Active Delay Time (tRRDmin)
+    0x90,                                 ///< 20  Minimum Row Precharge Delay Time (tRPmin)
+    0x11,                                 ///< 21  Upper Nibbles for tRAS and tRC
+    0x50,                                 ///< 22  Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+    0xE0,                                 ///< 23  Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+    0x90,                                 ///< 24  Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
+    0x06,                                 ///< 25  Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
+    0x3C,                                 ///< 26  Minimum Internal Write to Read Command Delay Time (tWTRmin)
+    0x3C,                                 ///< 27  Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+    0x01,                                 ///< 28  Upper Nibble for tFAW
+    0x90,                                 ///< 29  Minimum Four Activate Window Delay Time (tFAWmin)
+    0x00,                                 ///< 30  SDRAM Optional Features
+    0x00,                                 ///< 31  SDRAMThermalAndRefreshOptions
+    0x00,                                 ///< 32  ModuleThermalSensor
+    0x00,                                 ///< 33  SDRAM Device Type
+    0xCA,                                 ///< 34  Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867)
+    0xFA,                                 ///< 35  Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
+    0x00,                                 ///< 36  Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+    0x00,                                 ///< 37  Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+    0x00,                                 ///< 38  Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+    0xA8,                                 ///< 39  Row precharge time for all banks (tRPab)
+    0x00,                                 ///< 40  FTB for Row precharge time for all banks (tRPab)
+    0, 0, 0, 0, 0, 0, 0, 0, 0,            ///< 41 - 49
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 50 - 59
+    0, 0,                                 ///< 60 - 61
+    0x00,                                 ///< 62  Reference Raw Card Used
+    0x00,                                 ///< 63  Address Mapping from Edge Connector to DRAM
+    0x00,                                 ///< 64  ThermalHeatSpreaderSolution
+    0, 0, 0, 0, 0,                        ///< 65 - 69
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 70 - 79
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 80 - 89
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 90 - 99
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 100 - 109
+    0, 0, 0, 0, 0, 0, 0,                  ///< 110 - 116
+    0x00,                                 ///< 117 Module Manufacturer ID Code, Least Significant Byte
+    0x00,                                 ///< 118 Module Manufacturer ID Code, Most Significant Byte
+    0x00,                                 ///< 119 Module Manufacturing Location
+    0x00,                                 ///< 120 Module Manufacturing Date Year
+    0x00,                                 ///< 121 Module Manufacturing Date creation work week
+    0x55,                                 ///< 122 Module Serial Number A
+    0x00,                                 ///< 123 Module Serial Number B
+    0x00,                                 ///< 124 Module Serial Number C
+    0x00,                                 ///< 125 Module Serial Number D
+    0x00,                                 ///< 126 CRC A
+    0x00                                  ///< 127 CRC B
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size = sizeof (mSkylakeRvp3Spd110);
+
+//
+// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] = {
+    0x91,                                 ///< 0   128 SPD bytes used, 256 total, CRC covers 0..116
+    0x20,                                 ///< 1   SPD Revision 2.0
+    0xF1,                                 ///< 2   DRAM Type: LPDDR3 SDRAM
+    0x03,                                 ///< 3   Module Type: SO-DIMM
+    0x05,                                 ///< 4   8 Banks, 8 Gb SDRAM density
+    0x19,                                 ///< 5   SDRAM Addressing: 15 Rows, 10 Columns
+    0x05,                                 ///< 6   Module Nominal Voltage VDD: 1.2v
+    0x0B,                                 ///< 7   SDRAM width: 32 bits, 2 Ranks
+    0x03,                                 ///< 8   SDRAM bus width: 64 bits, no ECC
+    0x11,                                 ///< 9   Fine Timebase (FTB) granularity: 1 ps
+    0x01,                                 ///< 10  Medium Timebase (MTB) : 0.125 ns
+    0x08,                                 ///< 11  Medium Timebase Divisor
+    0x08,                                 ///< 12  tCKmin = 0.938 ns (LPDDR3-2133)
+    0x00,                                 ///< 13  Reserved
+    0x50,                                 ///< 14  CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (LSB)
+    0x15,                                 ///< 15  CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (MSB)
+    0x78,                                 ///< 16  Minimum CAS Latency (tAAmin) = 15.008 ns
+    0x78,                                 ///< 17  tWR = 15 ns
+    0x90,                                 ///< 18  Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+    0x50,                                 ///< 19  tRRD = 10 ns
+    0x90,                                 ///< 20  Minimum row precharge time (tRPmin) = 18 ns
+    0x11,                                 ///< 21  Upper nibbles for tRAS and tRC
+    0x50,                                 ///< 22  tRASmin = 42 ns
+    0xE0,                                 ///< 23  tRCmin  = (tRASmin + tRPmin) = 60 ns
+    0x90,                                 ///< 24  tRFCmin = (tRFCab) = 210 ns (8Gb)
+    0x06,                                 ///< 25  tRFCmin MSB
+    0x3C,                                 ///< 26  tWTRmin = 7.5 ns
+    0x3C,                                 ///< 27  tRTPmin = 7.5 ns
+    0x01,                                 ///< 28  tFAWmin upper nibble
+    0x90,                                 ///< 29  tFAWmin = 50 ns
+    0x00,                                 ///< 30  SDRAM Optional Features - none
+    0x00,                                 ///< 31  SDRAM Thermal / Refresh options - none
+    0x00,                                 ///< 32  ModuleThermalSensor
+    0x00,                                 ///< 33  SDRAM Device Type
+    0xC2,                                 ///< 34  FTB for tCKmin = 0.938 ns (LPDDR3-2133)
+    0x08,                                 ///< 35  FTB for tAAmin = 15.008 ns (LPDDR3-2133)
+    0x00,                                 ///< 36  Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+    0x00,                                 ///< 37  Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+    0x00,                                 ///< 38  Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+    0xA8,                                 ///< 39  Row precharge time for all banks (tRPab)= 21 ns
+    0x00,                                 ///< 40  FTB for Row precharge time for all banks (tRPab) = 0
+    0, 0, 0, 0, 0, 0, 0, 0, 0,            ///< 41 - 49
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 50 - 59
+    0, 0,                                 ///< 60 - 61
+    0x00,                                 ///< 62  Reference Raw Card Used
+    0x00,                                 ///< 63  Rank1 Mapping: Standard
+    0x00,                                 ///< 64  ThermalHeatSpreaderSolution
+    0, 0, 0, 0, 0,                        ///< 65 - 69
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 70 - 79
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 80 - 89
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 90 - 99
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 100 - 109
+    0, 0, 0, 0, 0, 0, 0,                  ///< 110 - 116
+    0x00,                                 ///< 117 Module Manufacturer ID Code, Least Significant Byte
+    0x00,                                 ///< 118 Module Manufacturer ID Code, Most Significant Byte
+    0x00,                                 ///< 119 Module Manufacturing Location
+    0x00,                                 ///< 120 Module Manufacturing Date Year
+    0x00,                                 ///< 121 Module Manufacturing Date creation work week
+    0x55,                                 ///< 122 Module ID: Module Serial Number
+    0x00,                                 ///< 123 Module Serial Number B
+    0x00,                                 ///< 124 Module Serial Number C
+    0x00,                                 ///< 125 Module Serial Number D
+    0x00,                                 ///< 126 CRC A
+    0x00                                  ///< 127 CRC B
+};
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size = sizeof (mKblRSpdLpddr32133);
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] = {
+  0x24,                                 ///< 0   Number of Serial PD Bytes Written / SPD Device Size
+  0x01,                                 ///< 1   SPD Revision
+  0x0F,                                 ///< 2   DRAM Device Type
+  0x0E,                                 ///< 3   Module Type
+  0x15,                                 ///< 4   SDRAM Density and Banks: 8 Banks, 8 Gb SDRAM density
+  0x19,                                 ///< 5   SDRAM Addressing: 15 Rows, 10 Columns
+  0x90,                                 ///< 6   SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
+  0x00,                                 ///< 7   SDRAM Optional Features
+  0x00,                                 ///< 8   SDRAM Thermal and Refresh Options
+  0x00,                                 ///< 9   Other SDRAM Optional Features
+  0x00,                                 ///< 10  Reserved - must be coded as 0x00
+  0x0B,                                 ///< 11  Module Nominal Voltage, VDD
+  0x0B,                                 ///< 12  Module Organization, SDRAM width: 32 bits, 2 Ranks
+  0x03,                                 ///< 13  Module Memory Bus Width: 2 channels, 64 bit channel bus width
+  0x00,                                 ///< 14  Module Thermal Sensor
+  0x00,                                 ///< 15  Extended Module Type
+  0x00,                                 ///< 16  Reserved - must be coded as 0x00
+  0x00,                                 ///< 17  Timebases
+  0x08,                                 ///< 18  SDRAM Minimum Cycle Time (tCKmin)
+  0xFF,                                 ///< 19  SDRAM Minimum Cycle Time (tCKmax)
+  0xD4,                                 ///< 20  CAS Latencies Supported, First Byte
+  0x01,                                 ///< 21  CAS Latencies Supported, Second Byte
+  0x00,                                 ///< 22  CAS Latencies Supported, Third Byte
+  0x00,                                 ///< 23  CAS Latencies Supported, Fourth Byte
+  0x78,                                 ///< 24  Minimum CAS Latency Time (tAAmin)
+  0x00,                                 ///< 25  Read and Write Latency Set Options
+  0x90,                                 ///< 26  Minimum RAS# to CAS# Delay Time (tRCDmin)
+  0xA8,                                 ///< 27  Minimum Row Precharge Delay Time for all banks (tRPab)
+  0x90,                                 ///< 28  Minimum Row Precharge Delay Time per bank (tRPpb)
+  0x90,                                 ///< 29  Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
+  0x06,                                 ///< 30  Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
+  0xD0,                                 ///< 31  Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
+  0x02,                                 ///< 32  Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
+  0, 0, 0, 0, 0, 0, 0,                  ///< 33 - 39
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 40 - 49
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 50 - 59
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 60 - 69 Connector to SDRAM Bit Mapping
+  0, 0, 0, 0, 0, 0, 0, 0,               ///< 70 - 77 Connector to SDRAM Bit Mapping
+  0, 0,                                 ///< 78 - 79
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 80 - 89
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 90 - 99
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 100 - 109
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 110 - 119
+  0x00,                                 ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
+  0x00,                                 ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
+  0x00,                                 ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+  0x08,                                 ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
+  0x7F,                                 ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
+  0xC2,                                 ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+  0x00,                                 ///< 126 CRC A
+  0x00,                                 ///< 127 CRC B
+  0, 0,                                 ///< 128 - 129
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 130 - 139
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 140 - 149
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 150 - 159
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 160 - 169
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 170 - 179
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 180 - 189
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 190 - 199
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 200 - 209
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 210 - 219
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 220 - 229
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 230 - 239
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 240 - 249
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 250 - 259
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 260 - 269
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 270 - 279
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 280 - 289
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 290 - 299
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 300 - 309
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 310 - 319
+  0x00,                                 ///< 320 Module Manufacturer ID Code, Least Significant Byte
+  0x00,                                 ///< 321 Module Manufacturer ID Code, Most Significant Byte
+  0x00,                                 ///< 322 Module Manufacturing Location
+  0x00,                                 ///< 323 Module Manufacturing Date Year
+  0x00,                                 ///< 324 Module Manufacturing Date Week
+  0x55,                                 ///< 325 Module Serial Number A
+  0x00,                                 ///< 326 Module Serial Number B
+  0x00,                                 ///< 327 Module Serial Number C
+  0x00,                                 ///< 328 Module Serial Number D
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 334 - 338 Module Part Number
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 339 - 343 Module Part Number
+  0x20, 0x20, 0x20, 0x20, 0x20,         ///< 344 - 348 Module Part Number
+  0x00,                                 ///< 349 Module Revision Code
+  0x00,                                 ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+  0x00,                                 ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+  0x00,                                 ///< 352 DRAM Stepping
+  0, 0, 0, 0, 0, 0, 0,                  ///< 353 - 359
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 360 - 369
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 370 - 379
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 380 - 389
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 390 - 399
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 400 - 409
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 410 - 419
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 420 - 429
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 430 - 439
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 440 - 449
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 450 - 459
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 460 - 469
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 470 - 479
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 480 - 489
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 490 - 499
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,         ///< 500 - 509
+  0, 0                                  ///< 510 - 511
+};
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size = sizeof (mSpdLpddr32133);
+
+#endif // _KABYLAKE_RVP3_SPD_TABLE_H_

+ 45 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPostMemLib.c

@@ -0,0 +1,45 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardInitBeforeSiliconInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeSiliconInit (
+  VOID
+  )
+{
+  KabylakeRvp3BoardInitBeforeSiliconInit ();
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterSiliconInit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}

+ 59 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf

@@ -0,0 +1,59 @@
+## @file
+# Component information file for KabylakeRvp3InitLib in PEI post memory phase.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiBoardPostMemInitLib
+  FILE_GUID                      = 7fcc3900-d38d-419f-826b-72481e8b5509
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = BoardInitLib
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  GpioExpanderLib
+  PcdLib
+  SiliconInitLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiKabylakeRvp3InitPostMemLib.c
+  KabylakeRvp3GpioTable.c
+  KabylakeRvp3HdaVerbTables.c
+  PeiBoardInitPostMemLib.c
+
+[FixedPcd]
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+  gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
+  gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
+
+  gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
+
+  gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
+  gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize

+ 111 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.c

@@ -0,0 +1,111 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDetect (
+  VOID
+  );
+
+EFI_BOOT_MODE
+EFIAPI
+KabylakeRvp3BoardBootModeDetect (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDebugInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardInitBeforeMemoryInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+BoardDetect (
+  VOID
+  )
+{
+  KabylakeRvp3BoardDetect ();
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardDebugInit (
+  VOID
+  )
+{
+  KabylakeRvp3BoardDebugInit ();
+  return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+BoardBootModeDetect (
+  VOID
+  )
+{
+  return KabylakeRvp3BoardBootModeDetect ();
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeMemoryInit (
+  VOID
+  )
+{
+  KabylakeRvp3BoardInitBeforeMemoryInit ();
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterMemoryInit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeTempRamExit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterTempRamExit (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+

+ 138 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf

@@ -0,0 +1,138 @@
+## @file
+# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Library
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiBoardInitPreMemLib
+  FILE_GUID                      = ec3675bc-1470-417d-826e-37378140213d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = BoardInitLib
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  PcdLib
+  SiliconInitLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiKabylakeRvp3Detect.c
+  PeiKabylakeRvp3InitPreMemLib.c
+  KabylakeRvp3HsioPtssTables.c
+  KabylakeRvp3SpdTable.c
+  PeiBoardInitPreMemLib.c
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+  # PCH-LP HSIO PTSS Table
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+  # PCH-H HSIO PTSS Table
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+
+  # SA Misc Config
+  gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+  gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+  gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+  gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+  gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+  # PEG Reset By GPIO
+  gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
+  gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+  # SPD Address Table
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+  # CA Vref Configuration
+
+  # Root Port Clock Info
+  gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo
+
+  # USB 2.0 Port AFE
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
+
+  # USB 2.0 Port Over Current Pin
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+  # USB 3.0 Port Over Current Pin
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+  # Misc
+  gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
+
+

+ 71 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3Detect.c

@@ -0,0 +1,71 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <Library/SiliconInitLib.h>
+
+#include "PeiKabylakeRvp3InitLib.h"
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h>
+
+BOOLEAN
+IsKabylakeRvp3 (
+  VOID
+  )
+{
+  // TBD: Do detection - BoardIdKabylakeRvp3 v.s. BoardIdKabyLakeYLpddr3Rvp3
+  return TRUE;
+}
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDetect (
+  VOID
+  )
+{
+  if (LibPcdGetSku () != 0) {
+    return EFI_SUCCESS;
+  }
+
+  DEBUG ((EFI_D_INFO, "KabylakeRvp3DetectionCallback\n"));
+
+  if (IsKabylakeRvp3 ()) {
+    LibPcdSetSku (BoardIdKabyLakeYLpddr3Rvp3);
+
+    DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+    ASSERT (LibPcdGetSku() == BoardIdKabyLakeYLpddr3Rvp3);
+  }
+  return EFI_SUCCESS;
+}

+ 48 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h

@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_
+#define _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchHsioPtssTables.h>
+#include <IoExpander.h>
+
+#include <KabylakeRvp3Id.h>
+
+extern const UINT8 mDqByteMapSklRvp3[2][6][2];
+extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8];
+extern const UINT8 mSkylakeRvp3Spd110[];
+extern const UINT16 mSkylakeRvp3Spd110Size;
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[];
+extern UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size;
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[];
+extern UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size;
+
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3;
+extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[];
+extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize;
+
+extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[];
+extern UINT16 mGpioTableIoExpanderSize;
+extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel;
+extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[];
+extern UINT16 mGpioTableLpDdr3Rvp3Size;
+
+#endif // _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_

+ 214 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPostMemLib.c

@@ -0,0 +1,214 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <IoExpander.h>
+#include <Library/PcdLib.h>
+#include <Library/SiliconInitLib.h>
+
+#include "PeiKabylakeRvp3InitLib.h"
+
+/**
+  SkylaeA0Rvp3 board configuration init function for PEI post memory phase.
+
+  PEI_BOARD_CONFIG_PCD_INIT
+
+  @param  Content  pointer to the buffer contain init information for board init.
+
+  @retval EFI_SUCCESS             The function completed successfully.
+  @retval EFI_INVALID_PARAMETER   The parameter is NULL.
+**/
+EFI_STATUS
+EFIAPI
+KabylakeRvp3Init (
+  VOID
+  )
+{
+  PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3);
+
+  //
+  // Assign the GPIO table with pin configs to be used for UCMC
+  //
+  PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableLpddr3Rvp3UcmcDevice);
+  PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableLpddr3Rvp3UcmcDeviceSize);
+
+  return EFI_SUCCESS;
+}
+
+#define EXPANDERS                                 2                    // defines expander's quantity
+
+/**
+  Configures GPIO
+
+  @param[in]  GpioTable       Point to Platform Gpio table
+  @param[in]  GpioTableCount  Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+  IN GPIO_INIT_CONFIG                 *GpioDefinition,
+  IN UINT16                           GpioTableCount
+  )
+{
+  EFI_STATUS          Status;
+
+  DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+  Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+  DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+VOID
+SetBit (
+  IN OUT UINT32  *Value,
+  IN     UINT32  BitNumber,
+  IN     BOOLEAN NewBitValue
+  )
+{
+  if (NewBitValue) {
+    *Value |= 1 << BitNumber;
+  } else {
+    *Value &= ~(1 << BitNumber);
+  }
+}
+
+/**
+  Configures IO Expander GPIO device
+
+  @param[in]  IOExpGpioDefinition  Point to IO Expander Gpio table
+  @param[in]  IOExpGpioTableCount  Number of Gpio table entries
+
+**/
+void
+ConfigureIoExpanderGpio (
+  IN IO_EXPANDER_GPIO_CONFIG        *IoExpGpioDefinition,
+  IN UINT16                          IoExpGpioTableCount
+  )
+{
+  UINT8               Index;
+  UINT32              Direction[EXPANDERS] = {0x00FFFFFF, 0x00FFFFFF};
+  UINT32              Level[EXPANDERS] = {0};
+  UINT32              Polarity[EXPANDERS] = {0};
+
+   // IoExpander {TCA6424A}
+  DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n"));
+  for (Index = 0; Index < IoExpGpioTableCount; Index++) {   //Program IO Expander as per the table defined in PeiPlatformHooklib.c
+    SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioDirection);
+    SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLevel);
+    SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioInversion);
+  }
+  for (Index = 0; Index < EXPANDERS; Index++) {
+    GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Index]);
+  }
+  DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n"));
+  return;
+}
+
+/**
+  Configure GPIO behind IoExpander.
+
+  @param[in]  PeiServices       General purpose services available to every PEIM.
+  @param[in]  NotifyDescriptor
+  @param[in]  Interface
+
+  @retval     EFI_SUCCESS       Operation success.
+**/
+VOID
+ExpanderGpioInit (
+  VOID
+  )
+{
+  ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize);
+}
+
+/**
+  Configure single GPIO pad for touchpanel interrupt
+
+**/
+VOID
+TouchpanelGpioInit (
+  VOID
+  )
+{
+  GPIO_INIT_CONFIG*     TouchpanelPad;
+  GPIO_PAD_OWN          PadOwnVal;
+
+  PadOwnVal = 0;
+  TouchpanelPad = &mGpioTableLpDdr3Rvp3Touchpanel;
+
+  GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);
+  if (PadOwnVal == GpioPadOwnHost) {
+    GpioConfigurePads (1, TouchpanelPad);
+  }
+}
+
+
+/**
+  Configure GPIO
+
+**/
+VOID
+GpioInit (
+  VOID
+  )
+{
+  ConfigureGpio (mGpioTableLpDdr3Rvp3, mGpioTableLpDdr3Rvp3Size);
+
+  TouchpanelGpioInit();
+
+  return;
+}
+
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardInitBeforeSiliconInit (
+  VOID
+  )
+{
+  KabylakeRvp3Init ();
+
+  GpioInit ();
+  ExpanderGpioInit ();
+    
+  ///
+  /// Do Late PCH init
+  ///
+  LateSiliconInit ();
+
+  return EFI_SUCCESS;
+}

+ 235 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c

@@ -0,0 +1,235 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <Library/SiliconInitLib.h>
+
+#include "PeiKabylakeRvp3InitLib.h"
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h>
+
+//
+// Reference RCOMP resistors on motherboard - for SKL RVP1
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
+
+/**
+  SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
+
+  PEI_BOARD_CONFIG_PCD_INIT
+
+  @param  Content  pointer to the buffer contain init information for board init.
+
+  @retval EFI_SUCCESS             The function completed successfully.
+  @retval EFI_INVALID_PARAMETER   The parameter is NULL.
+**/
+EFI_STATUS
+EFIAPI
+KabylakeRvp3InitPreMem (
+  VOID
+  )
+{
+  PcdSet32S (PcdPcie0WakeGpioNo, 0);
+  PcdSet8S  (PcdPcie0HoldRstExpanderNo, 0);
+  PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
+  PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
+  PcdSet8S  (PcdPcie0PwrEnableExpanderNo, 0);
+  PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
+  PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+  //
+  // HSIO PTSS Table
+  //
+  PcdSet32S (PcdSpecificLpHsioPtssTable1,     (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
+  PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
+  PcdSet32S (PcdSpecificLpHsioPtssTable2,     (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
+  PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
+
+  //
+  // DRAM related definition
+  //
+  PcdSet8S (PcdSaMiscUserBd, 5);
+
+  PcdSet8S (PcdMrcSpdAddressTable0, 0xA2);
+  PcdSet8S (PcdMrcSpdAddressTable1, 0xA0);
+  PcdSet8S (PcdMrcSpdAddressTable2, 0xA2);
+  PcdSet8S (PcdMrcSpdAddressTable3, 0xA0);
+
+  PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
+  PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
+  PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
+  PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
+  PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
+  PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
+
+    PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);
+    PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);
+
+  PcdSetBoolS (PcdIoExpanderPresent, TRUE);
+  
+  return EFI_SUCCESS;
+}
+
+#define SIO_RUNTIME_REG_BASE_ADDRESS                          0x0680
+
+/**
+  Configures GPIO
+
+  @param[in]  GpioTable       Point to Platform Gpio table
+  @param[in]  GpioTableCount  Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+  IN GPIO_INIT_CONFIG                 *GpioDefinition,
+  IN UINT16                           GpioTableCount
+  )
+{
+  EFI_STATUS          Status;
+
+  DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+  Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+  DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+  Configure GPIO Before Memory is not ready.
+
+**/
+VOID
+GpioInitPreMem (
+  VOID
+  )
+{
+  // ConfigureGpio ();
+}
+
+/**
+  Configure Super IO
+
+**/
+VOID
+SioInit (
+  VOID
+  )
+{
+  //
+  // Program and Enable Default Super IO Configuration Port Addresses and range
+  //
+  PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
+
+  //
+  // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
+  //
+  PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS  & (~0x7F), 0x10);
+
+  return;
+}
+
+/**
+  Configues the IC2 Controller on which GPIO Expander Communicates.
+  This Function is to enable the I2CGPIOExapanderLib to programm the Gpios
+  Complete intilization will be done in later Stage
+
+**/
+VOID
+EFIAPI
+I2CGpioExpanderInitPreMem(
+  VOID
+  )
+{
+  ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
+  SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
+}
+
+/**
+  Configure GPIO and SIO before memory ready
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardInitBeforeMemoryInit (
+  VOID
+  )
+{
+  KabylakeRvp3InitPreMem ();
+
+  //
+  // Configures the I2CGpioExpander
+  //
+  if (PcdGetBool (PcdIoExpanderPresent)) {
+    I2CGpioExpanderInitPreMem();
+  }
+
+  GpioInitPreMem ();
+  SioInit ();
+    
+  ///
+  /// Do basic PCH init
+  ///
+  SiliconInit ();
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDebugInit (
+  VOID
+  )
+{
+  ///
+  /// Do Early PCH init
+  ///
+  EarlySiliconInit ();
+  return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+KabylakeRvp3BoardBootModeDetect (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+

+ 46 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c

@@ -0,0 +1,46 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <KabylakeRvp3Id.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardInitBeforeSiliconInit (
+  VOID
+  );
+
+BOARD_POST_MEM_INIT_FUNC  mKabylakeRvp3BoardInitFunc = {
+  KabylakeRvp3BoardInitBeforeSiliconInit,
+  NULL, // BoardInitAfterSiliconInit
+};
+
+EFI_STATUS
+EFIAPI
+PeiKabylakeRvp3MultiBoardInitLibConstructor (
+  VOID
+  )
+{
+  if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
+    return RegisterBoardPostMemInit (&mKabylakeRvp3BoardInitFunc);
+  }
+  return EFI_SUCCESS;
+}

+ 61 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf

@@ -0,0 +1,61 @@
+## @file
+# Component information file for KabylakeRvp3InitLib in PEI post memory phase.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiKabylakeRvp3MultiBoardInitLib
+  FILE_GUID                      = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = PeiKabylakeRvp3MultiBoardInitLibConstructor
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  GpioExpanderLib
+  PcdLib
+  SiliconInitLib
+  MultiBoardInitSupportLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiKabylakeRvp3InitPostMemLib.c
+  KabylakeRvp3GpioTable.c
+  KabylakeRvp3HdaVerbTables.c
+  PeiMultiBoardInitPostMemLib.c
+
+[FixedPcd]
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+  gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
+  gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
+
+  gBoardModuleTokenSpaceGuid.PcdHdaVerbTable
+
+  gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
+  gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize

+ 88 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c

@@ -0,0 +1,88 @@
+/** @file
+  Platform Hook Library instances
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <KabylakeRvp3Id.h>
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDetect (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3MultiBoardDetect (
+  VOID
+  );
+
+EFI_BOOT_MODE
+EFIAPI
+KabylakeRvp3BoardBootModeDetect (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardDebugInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3BoardInitBeforeMemoryInit (
+  VOID
+  );
+
+BOARD_DETECT_FUNC  mKabylakeRvp3BoardDetectFunc = {
+  KabylakeRvp3MultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC  mKabylakeRvp3BoardPreMemInitFunc = {
+  KabylakeRvp3BoardDebugInit,
+  KabylakeRvp3BoardBootModeDetect,
+  KabylakeRvp3BoardInitBeforeMemoryInit,
+  NULL, // BoardInitAfterMemoryInit
+  NULL, // BoardInitBeforeTempRamExit
+  NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+KabylakeRvp3MultiBoardDetect (
+  VOID
+  )
+{
+  KabylakeRvp3BoardDetect ();
+  if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
+    RegisterBoardPreMemInit (&mKabylakeRvp3BoardPreMemInitFunc);
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor (
+  VOID
+  )
+{
+  return RegisterBoardDetect (&mKabylakeRvp3BoardDetectFunc);
+}

+ 140 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf

@@ -0,0 +1,140 @@
+## @file
+# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Library
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiKabylakeRvp3MultiBoardInitPreMemLib
+  FILE_GUID                      = EA05BD43-136F-45EE-BBBA-27D75817574F
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  PcdLib
+  SiliconInitLib
+  MultiBoardInitSupportLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiKabylakeRvp3InitPreMemLib.c
+  KabylakeRvp3HsioPtssTables.c
+  KabylakeRvp3SpdTable.c
+  PeiMultiBoardInitPreMemLib.c  
+  PeiKabylakeRvp3Detect.c
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+  # PCH-LP HSIO PTSS Table
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+  gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+  # PCH-H HSIO PTSS Table
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+  #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+
+  # SA Misc Config
+  gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+  gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+  gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+  gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+  gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+  # PEG Reset By GPIO
+  gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
+  gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+  gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+  # SPD Address Table
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+  # CA Vref Configuration
+
+  # Root Port Clock Info
+  gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo
+  gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo
+
+  # USB 2.0 Port AFE
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
+  gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
+
+  # USB 2.0 Port Over Current Pin
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+  # USB 3.0 Port Over Current Pin
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+  # Misc
+  gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
+
+

+ 272 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc

@@ -0,0 +1,272 @@
+## @file
+#  Platform description.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+[Defines]
+  #
+  # Set platform specific package/folder name, same as passed from PREBUILD script.
+  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder
+  # DEFINE only takes effect at R9 DSC and FDF.
+  #
+  DEFINE      PLATFORM_PACKAGE                = MinPlatformPkg
+  DEFINE      PLATFORM_SI_PACKAGE             = KabylakeSiliconPkg
+  DEFINE      PLATFORM_SI_BIN_PACKAGE         = KabylakeSiliconBinPkg
+  DEFINE      PLATFORM_FSP_BIN_PACKAGE        = KabylakeFspBinPkg
+  DEFINE      PLATFORM_BOARD_PACKAGE          = KabylakeOpenBoardPkg
+  DEFINE      BOARD                           = KabylakeRvp3
+  DEFINE      PROJECT                         = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
+
+[PcdsFeatureFlag]
+  #
+  # Platform On/Off features are defined here
+  #
+  !include OpenBoardPkgConfig.dsc
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                       = $(PLATFORM_PACKAGE)
+  PLATFORM_GUID                       = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
+  PLATFORM_VERSION                    = 0.1
+  DSC_SPECIFICATION                   = 0x00010005
+  OUTPUT_DIRECTORY                    = Build/$(PROJECT)
+  SUPPORTED_ARCHITECTURES             = IA32|X64
+  BUILD_TARGETS                       = DEBUG|RELEASE
+  SKUID_IDENTIFIER                    = ALL
+
+
+  FLASH_DEFINITION                    = $(PROJECT)/OpenBoardPkg.fdf
+
+  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0x0
+  DEFINE   TOP_MEMORY_ADDRESS         = 0x0
+
+  #
+  # Default value for OpenBoardPkg.fdf use
+  #
+  DEFINE BIOS_SIZE_OPTION = SIZE_70
+
+  DEFINE     TRACEHUB     =
+  EDK_GLOBAL TRACEHUB     =
+
+  DEFINE   COV_TOOLS                  = VS2008
+
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+#                              Platform.
+#
+################################################################################
+[SkuIds]
+  0|DEFAULT              # The entry: 0|DEFAULT is reserved and always required.
+  4|KabylakeRvp3
+  0x60|KabyLakeYLpddr3Rvp3
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses.common]
+
+  PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
+
+  PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf
+  PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+  I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
+  GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
+
+  PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+
+  FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+  PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+  
+  FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+  FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
+
+  FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
+  FspPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+  FspPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf
+
+  ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
+  SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.inf
+
+  BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
+
+[LibraryClasses.IA32]
+  #
+  # PEI phase common
+  #
+  FspWrapperPlatformResetLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformResetLib/PeiFspWrapperPlatformResetLib.inf
+!if $(TARGET) == DEBUG
+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+!endif
+  TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+  MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+  BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
+
+[LibraryClasses.IA32.SEC]
+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
+  SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+
+[LibraryClasses.X64]
+  #
+  # DXE phase common
+  #
+  FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformResetLib/DxeFspWrapperPlatformResetLib.inf
+!if $(TARGET) == DEBUG
+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf
+!endif
+  TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf
+  MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+  BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+  MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
+  BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+  SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+!if $(TARGET) == DEBUG
+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+!endif
+  TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf
+  MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+  BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+  ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
+
+!include OpenBoardPkgPcd.dsc
+
+[Components.IA32]
+
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
+
+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+    <LibraryClasses>
+!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+      BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+!else
+      NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+!endif
+  }
+
+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+    <LibraryClasses>
+!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+      BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
+!else
+      NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
+!endif
+  }
+  
+  IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+  IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+
+!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE
+  $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
+
+[Components.X64]
+
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
+
+#
+# Silicon Init Package
+#
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
+
+  $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf {
+    <LibraryClasses>
+!if $(TARGET) == DEBUG
+      # Use serial debug lib here to print debug message in OsLoader progress code.
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  }
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE
+  $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf {
+    <LibraryClasses>
+!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+      BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
+!else
+      NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
+!endif
+  }
+  $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf {
+    <LibraryClasses>
+!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+      BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
+!else
+      NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
+!endif
+  }
+  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
+    <LibraryClasses>
+!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+      BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+!else
+      NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
+!endif
+  }
+
+  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+!endif
+
+  IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
+  $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+  $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+  
+  $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
+
+!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE
+  $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+
+  $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
+  
+  ShellBinPkg/UefiShell/UefiShell.inf
+
+!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
+!include OpenBoardPkgBuildOption.dsc

+ 555 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf

@@ -0,0 +1,555 @@
+## @file
+#  FDF file of Platform.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+   !include $(PLATFORM_BOARD_PACKAGE)/Include/Fdf/FlashMapInclude.fdf
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.KabylakeRvp3]
+#
+# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
+# assigned with PCD values. Instead, it uses the definitions for its variety, which
+# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
+#
+BaseAddress   = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress      #The base address of the FLASH Device.
+Size          = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize             #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize     = $(FLASH_BLOCK_SIZE)
+NumBlocks     = $(FLASH_NUM_BLOCKS)
+
+DEFINE SIPKG_DXE_SMM_BIN  = INF
+DEFINE SIPKG_PEI_BIN      = INF
+
+# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
+# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
+SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Offset)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gPlatformModuleTokenSpaceGuid.PcdFlashMicrocodeFvBase    = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+SET gPlatformModuleTokenSpaceGuid.PcdFlashMicrocodeFvSize    = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+SET gPlatformModuleTokenSpaceGuid.PcdFlashMicrocodeFvOffset  = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize        = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspWrapperBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Offset)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspWrapperSize = $(gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size)
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000
+#
+################################################################################
+gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x40000
+  0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  #
+  # Be careful on CheckSum field.
+  #
+  0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 4 Blocks  0x10000 Bytes / Block
+  0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+!if gPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+  #  Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+  #  Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+  #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xDF, 0x01, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
+
+
+gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Offset|gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Size
+gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Size
+FV = FVMAIN2_COMPACT
+
+gPlatformModuleTokenSpaceGuid.PcdFlashFvMainOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
+gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Offset|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size
+#FvRecovery3
+FV = FVRECOVERY3_COMPACT
+
+gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsSize
+gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsSize
+# FSP_S Section
+FV=FSP_S
+
+
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+#Microcode
+FV = MICROCODE_FV
+
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Offset|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
+#FvRecovery
+FV = FVRECOVERY2
+
+gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtSize
+gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtSize
+# FSP_M & T Section
+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M_T.fd
+
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
+#FvRecovery
+FV = FVRECOVERY
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.MICROCODE_FV]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = FALSE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = FALSE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
+  $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin
+}
+
+
+
+[FV.FSP_S]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE FV_IMAGE = 3417F275-4CF1-42D8-A0C3-B3F60779dF4D  {
+# Use Padded file which adds 0xC bytes of data (Note: Section will add 4 bytes of SECTION Header). This is done to align the FSP Header to 16 bytes
+  SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S_padded.fd
+}
+
+[FV.FVRECOVERY3_COMPACT]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
+!if $(TARGET) == DEBUG
+      SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+        SECTION FV_IMAGE = FVRECOVERY3
+      }
+!else
+    SECTION FV_IMAGE = FVRECOVERY3
+!endif
+}
+
+[FV.FVRECOVERY3]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = 8579D1CA-45E8-4f1c-A789-FFA770672099
+
+################################################################################
+#
+# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image.
+# Parsing tools will scan the INF file to determine the type of component or module.
+# The component or module type is used to reference the standard rules
+# defined elsewhere in the FDF file.
+#
+# The format for INF statements is:
+# INF $(PathAndInfFileName)
+#
+################################################################################
+
+
+# Init Board Config PCD
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+
+INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePeiPostMemInclude.fdf
+
+!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
+FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {
+  SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
+  SECTION UI  = "Vbt"
+}
+FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
+  SECTION RAW = MdeModulePkg/Logo/Logo.bmp
+}
+!endif # PcdPeiDisplayEnable
+
+
+[FV.FVRECOVERY2]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270091
+
+################################################################################
+#
+# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image.
+# Parsing tools will scan the INF file to determine the type of component or module.
+# The component or module type is used to reference the standard rules
+# defined elsewhere in the FDF file.
+#
+# The format for INF statements is:
+# INF $(PathAndInfFileName)
+#
+################################################################################
+  ##
+  #  PEI Apriori file example, more PEIM module added later.
+  ##
+APRIORI PEI {
+}
+
+  ##
+  #  PEI Phase modules
+  ##
+  
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePeiPreMemInclude.fdf
+
+!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+
+[FV.FVRECOVERY]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = BA34AA5B-110E-4B10-B729-E559EFD075D3
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePeiBfvInclude.fdf
+
+
+[FV.FVMAIN2]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvForceRebase      = FALSE
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B92CF322-8AFA-4aa4-B946-005DF1D69778
+
+
+#INF ShellBinPkg/UefiShell/UefiShell.inf
+
+
+[FV.FVMAIN2_COMPACT]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE FV_IMAGE = 4E35FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+      SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+        SECTION FV_IMAGE = FVMAIN2
+      }
+}
+
+[FV.FVMAIN]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = A881D567-6CB0-4eee-8435-2E72D33E45B5
+
+  ##
+  #  DXE Apriori file example, more DXE module added later.
+  ##
+
+APRIORI DXE {
+}
+
+  ##
+  #  DXE Phase modules
+  ##
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreDxeInclude.fdf
+
+INF  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE
+INF  $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
+
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+
+INF  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
+
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
+
+INF  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+!endif
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
+
+INF  RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
+INF  RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
+
+INF  $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf
+
+INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+
+!endif
+
+INF  IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
+
+!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+
+INF ShellBinPkg/UefiShell/UefiShell.inf
+
+[FV.FVMAIN_COMPACT]
+BlockSize     = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+         SECTION FV_IMAGE = FVMAIN
+       }
+     }
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
+

+ 155 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc

@@ -0,0 +1,155 @@
+## @file
+# platform build option configuration file.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[BuildOptions]
+# Define Build Options both for EDK and EDKII drivers.
+
+
+  DEFINE DSC_S3_BUILD_OPTIONS =
+
+  DEFINE DSC_CSM_BUILD_OPTIONS =
+
+!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
+  DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1
+!else
+  DEFINE DSC_ACPI_BUILD_OPTIONS =
+!endif
+
+  DEFINE BIOS_GUARD_BUILD_OPTIONS =
+
+  DEFINE OVERCLOCKING_BUILD_OPTION =
+
+  DEFINE FSP_BINARY_BUILD_OPTIONS =
+
+  DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG
+
+  DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =
+
+  DEFINE RESTRICTED_OPTION =
+
+
+  DEFINE SV_BUILD_OPTIONS =
+
+  DEFINE TEST_MENU_BUILD_OPTION =
+
+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
+  DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-
+!else
+  DEFINE OPTIMIZE_DISABLE_OPTIONS =
+!endif
+
+  DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =
+
+
+  DEFINE TPM_BUILD_OPTION =
+
+  DEFINE TPM2_BUILD_OPTION =
+
+  DEFINE DSC_TBT_BUILD_OPTIONS =
+
+  DEFINE DSC_DCTT_BUILD_OPTIONS =
+
+  DEFINE EMB_BUILD_OPTIONS =
+
+  DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1
+
+  DEFINE DSC_KBCEMUL_BUILD_OPTIONS =
+
+  DEFINE BOOT_GUARD_BUILD_OPTIONS =
+
+  DEFINE SECURE_BOOT_BUILD_OPTIONS =
+
+  DEFINE USBTYPEC_BUILD_OPTION =
+
+  DEFINE CAPSULE_BUILD_OPTIONS =
+
+  DEFINE PERFORMANCE_BUILD_OPTION =
+
+  DEFINE DEBUGUSEUSB_BUILD_OPTION =
+
+  DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION = -DDISABLE_NEW_DEPRECATED_INTERFACES=1
+
+  DEFINE SINITBIN_BUILD_OPTION =
+
+  DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1
+
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)  $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
+
+[BuildOptions.Common.EDKII]
+
+#
+# For IA32 Global Build Flag
+#
+       *_*_IA32_CC_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+       *_*_IA32_VFRPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_IA32_APP_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_IA32_ASLPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_IA32_ASLCC_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_IA32_NASM_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+GCC:   *_*_IA32_PP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT:  *_*_IA32_ASM_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT:  *_*_IA32_CC_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+MSFT:  *_*_IA32_VFRPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT:  *_*_IA32_APP_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT:  *_*_IA32_ASLPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT:  *_*_IA32_ASLCC_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+       *_*_X64_CC_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+       *_*_X64_VFRPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_X64_APP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_X64_ASLPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_X64_ASLCC_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+       *_*_X64_NASM_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+
+#
+# For X64 Specific Build Flag
+#
+GCC:   *_*_X64_PP_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT:  *_*_X64_ASM_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT:  *_*_X64_CC_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+MSFT:  *_*_X64_VFRPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT:  *_*_X64_APP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT:  *_*_X64_ASLPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT:  *_*_X64_ASLCC_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection
+[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+  
+# Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support NX protection
+[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPLICATION]
+  #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+  #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+

+ 133 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc

@@ -0,0 +1,133 @@
+## @file
+#  Platform configuration file.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+  #
+  # Please select BootStage here.
+  # Stage 1 - enable debug (system deadloop after debug init)
+  # Stage 2 - mem init (system deadloop after mem init)
+  # Stage 3 - boot to shell only
+  # Stage 4 - boot to OS
+  # Stage 5 - boot to OS with security boot enabled
+  #
+  gPlatformModuleTokenSpaceGuid.PcdBootStage|4
+  
+  gPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+  gPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+  gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|FALSE
+  gPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
+  gPlatformModuleTokenSpaceGuid.PcdTpm2Enable|FALSE
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 1
+  gPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 2
+  gPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+  gPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 3
+  gPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+  gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 4
+  gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif
+
+!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 5
+  gPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+  gPlatformModuleTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif
+  
+  #
+  # More fine granularity control below:
+  #
+  
+  
+  gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE
+
+
+
+#
+# TRUE is ENABLE. FALSE is DISABLE.
+#
+
+#
+# BIOS build switches configuration
+#
+  gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
+
+# CPU
+  gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
+  gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE  #Set to FALSE for GCC Build @todo Convert TXT ASM to NASM
+  gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE
+
+# SA
+  gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
+
+# ME
+  gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
+
+  gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
+  gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE
+  gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE
+  gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE                       # TRUE - HPET / FALSE - 8254 timer is used.
+  gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
+  gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
+
+#
+# Override some PCDs for specific build requirements.
+#
+  #
+  # Disable USB debug message when Source Level Debug is enabled
+  # because they cannot be enabled at the same time.
+  #
+
+    gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
+    gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE
+    gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE
+
+
+
+  !if $(TARGET) == DEBUG
+    gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
+  !else
+    gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
+  !endif

+ 205 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc

@@ -0,0 +1,205 @@
+## @file
+#  Platform description.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+!if $(TARGET) == RELEASE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+  gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+  gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize        | 0x00026000
+
+  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|10
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|60
+
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
+
+
+
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
+
+#
+# 8MB Default
+#
+gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
+
+#
+# 16MB TSEG in Debug build only.
+#
+!if $(TARGET) == DEBUG
+  gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
+!endif
+
+
+
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
+
+  !if $(TARGET) == RELEASE
+  gPlatformModuleTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
+  !else
+  gPlatformModuleTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
+  !endif
+
+
+  gPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
+  !if $(TARGET) == RELEASE
+  gPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25
+  !else
+  gPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80
+  !endif
+
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFF7F000
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFF20000
+
+  ## Specifies max supported number of Logical Processors.
+  # @Prompt Configure max supported number of Logical Processorss
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12
+
+  ## Specifies the size of the microcode Region.
+  # @Prompt Microcode Region size.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
+
+  ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
+  # @Prompt Timeout for the BSP to detect all APs for the first time.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
+
+  ## Specifies the AP wait loop state during POST phase.
+  #  The value is defined as below.
+  #  1: Place AP in the Hlt-Loop state.
+  #  2: Place AP in the Mwait-Loop state.
+  #  3: Place AP in the Run-Loop state.
+  # @Prompt The AP wait loop state.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+
+
+  #
+  # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
+  #
+  # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
+  # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
+  #       that lie entirely within the expected fixed memory regions.
+  # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
+  # BIT3-31: Reserved
+  #
+  gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+  #
+  # See HstiFeatureBit.h for the definition
+  #
+  gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
+  gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
+
+[PcdsFixedAtBuild.IA32]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
+  gPlatformModuleTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
+  gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
+
+[PcdsFixedAtBuild.X64]
+  gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8
+
+
+  # Default platform supported RFC 4646 languages: (American) English
+  gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
+
+
+[PcdsPatchableInModule.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+
+!if $(TARGET) == DEBUG
+  gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
+!endif
+
+[PcdsDynamicHii.X64.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+  gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+
+[PcdsDynamicDefault]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFCF0070
+
+[PcdsDynamicDefault.common.DEFAULT]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
+  #
+  #  Set video to native resolution as Windows 8 WHCK requirement.
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
+  
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+
+[PcdsDynamicDefault.common.DEFAULT]
+  # gEfiTpmDeviceInstanceTpm20DtpmGuid
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+  gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
+

+ 166 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat

@@ -0,0 +1,166 @@
+@REM @file
+@REM
+@REM Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution.  The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+:: Useage: bld [/s] [/f <FEATURE_PCD_NAME> <FALSE or TRUE>] [/r]
+::
+:: For a given build command, 3 options may be passed into this batch file via command prompt:
+:: 1) /s = Redirects all output to a file called EDK2.log(Prep.log must be existed), which will be located at the root.
+:: 2) /f = Defines the passing in of a single override to a feature PCD that is used in the platform
+::    DSC file.  If this parameter is used, it is to be followed immediately after by both the feature
+::    pcd name and value. FeaturePcd is the full PCD name, like gPlatformModuleTokenSpaceGuid.PcdOptimizeCompilerEnable
+:: 3) /r = Useful for faster rebuilds when no changes have been made to .inf files. Passes -u to
+::    build.exe to skip the generation of makefiles.
+:: 4) rom = Build Bios.rom only and building SPIs will be skipped.
+::
+
+@echo on
+
+cd %WORKSPACE%
+
+@REM
+@REM Build FSP Binary
+@REM
+@if not defined FSP_BINARY_BUILD goto :SkipFspBinaryBuild
+@if %FSP_BINARY_BUILD% EQU FALSE goto :SkipFspBinaryBuild
+@set FSP_BUILD_PARAMETER=/d
+@set FSP_PKG_NAME=KabylakeFspPkg
+@if /I "%TARGET%" == "RELEASE" (
+  @if "%FSP_TEST_RELEASE%"=="TRUE" (
+    set FSP_BUILD_PARAMETER=/tr
+  ) else (
+    set FSP_BUILD_PARAMETER=/r
+  )
+)
+
+@if %FSP_WRAPPER_BUILD% EQU FALSE goto :BldEnd
+:SkipFspBinaryBuild
+
+@if %FSP_WRAPPER_BUILD% EQU FALSE goto :SkipPatchFspBinFvsBaseAddress
+del /f %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased*.fd
+
+cd %WORKSPACE%
+
+if exist %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc attrib -r %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc
+@call python %WORKSPACE_PLATFORM%\%PLATFORM_PACKAGE%\Tools\Fsp\RebaseAndPatchFspBinBaseAddress.py %WORKSPACE_PLATFORM%\%PLATFORM_BOARD_PACKAGE%\Include\Fdf\FlashMapInclude.fdf %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg Fsp.fd %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc 0x70
+
+cd %WORKSPACE%
+
+@if %ERRORLEVEL% NEQ 0 (
+  @echo !!! ERROR:RebaseAndPatchFspBinBaseAddress failed!!!
+  set SCRIPT_ERROR=1
+  goto :BldFail
+)
+copy /y /b %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_M.fd+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_T.fd %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_M_T.fd
+@REM prefix pad.bin file which adds 0xC bytes of data (Note: Section will add 4 bytes of SECTION Header). This is done to align the FSP Header to 16 bytes
+copy /y /b %WORKSPACE_PLATFORM%\%PLATFORM_PACKAGE%\Tools\Fsp\pad.bin+%WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S.fd %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S_padded.fd
+:SkipPatchFspBinFvsBaseAddress
+
+
+@SET SILENT_MODE=FALSE
+@SET REBUILD_MODE=
+@SET BUILD_ROM_ONLY=
+
+:: Loop through arguements until all are processed
+
+:BUILD_FLAGS_LOOP
+
+@if "%~1" == "" goto BUILD_FLAGS_LOOP_DONE
+
+@if "%~1" == "/f" (
+  shift
+  goto BUILD_FLAGS_LOOP
+)
+@if "%~1" == "/s" (
+  SET SILENT_MODE=TRUE
+  shift
+  goto BUILD_FLAGS_LOOP
+)
+@if "%~1" == "/r" (
+  SET REBUILD_MODE=-u
+  shift
+  goto BUILD_FLAGS_LOOP
+)
+@if "%~1" == "rom" (
+  SET BUILD_ROM_ONLY=rom
+  shift
+  goto BUILD_FLAGS_LOOP
+)
+:: Unknown build flag.
+shift
+goto BUILD_FLAGS_LOOP
+:BUILD_FLAGS_LOOP_DONE
+
+:: Output the build variables the user has selected.
+
+@echo.
+@echo  User Selected build options:
+@echo    SILENT_MODE = %SILENT_MODE%
+@echo    REBUILD_MODE = %REBUILD_MODE%
+@echo    BUILD_ROM_ONLY = %BUILD_ROM_ONLY%
+@echo.
+
+@if %SILENT_MODE% EQU TRUE goto BldSilent
+
+build -n %NUMBER_OF_PROCESSORS% %REBUILD_MODE% %EXT_BUILD_FLAGS%
+
+@if %ERRORLEVEL% NEQ 0 goto BldFail
+@echo.
+@echo Running postbuild.bat to complete the build process.
+@echo.
+call %WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat %BUILD_ROM_ONLY%
+@if %SCRIPT_ERROR% EQU 1 goto BldFail
+@goto BldSuccess
+
+:BldSilent
+@if exist Build.log del Build.log
+
+@echo. > Build.log
+@echo ************************************************************************ >> Build.log
+@echo ***********             Build.bat is launched here           *********** >> Build.log
+@echo ************************************************************************ >> Build.log
+@echo. >> Build.log
+
+build -n %NUMBER_OF_PROCESSORS% %REBUILD_MODE% %EXT_BUILD_FLAGS% 1>>Build.log 2>&1
+
+@if %ERRORLEVEL% NEQ 0 goto BldFail
+@echo. >> Build.log
+@echo Running postbuild.bat to complete the build process. >> Build.log
+@echo. >> Build.log
+@call %WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat %BUILD_ROM_ONLY% 1>>Build.log 2>&1
+@If %SCRIPT_ERROR% EQU 1 goto BldFail
+
+:BldSuccess
+@echo.
+@echo TARGET:               %TARGET%
+@echo TOOL_CHAIN_TAG:       %TOOL_CHAIN_TAG%
+@echo BIOS location:        %BUILD_DIR%\FV
+@echo.
+@echo The EDKII BIOS build has successfully completed!
+@echo.
+@REM
+
+@goto BldEnd
+
+:BldFail
+cd %WORKSPACE_PLATFORM%\%PROJECT%
+@echo.
+@echo The EDKII BIOS Build has failed!
+@echo.
+@exit /b 1
+
+:BldEnd
+@if %SILENT_MODE% EQU TRUE (
+  @if exist EDK2.log del EDK2.log
+  @if exist Prep.log if exist Build.log copy Prep.log+Build.log EDK2.log
+)
+
+cd %WORKSPACE_PLATFORM%\%PROJECT%

+ 54 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/cln.bat

@@ -0,0 +1,54 @@
+@REM @file
+@REM
+@REM Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution.  The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+@echo off
+echo.
+echo Run build cleanall...
+echo.
+
+cd ..
+
+if not defined WORKSPACE set WORKSPACE=%cd%
+if not defined WORKSPACE_PLATFORM set WORKSPACE_PLATFORM=%cd%
+if not defined WORKSPACE_SILICON set WORKSPACE_SILICON=%cd%
+
+REM build cleanall
+
+echo.
+echo Directories to clean...
+echo.
+
+if exist %WORKSPACE%\build rmdir /q /s %WORKSPACE%\build
+if exist %WORKSPACE%\conf\.cache rmdir /q /s %WORKSPACE%\conf\.cache
+
+echo.
+echo Files to clean...
+echo.
+
+if exist %WORKSPACE%\edk2.log del %WORKSPACE%\edk2.log
+if exist %WORKSPACE%\Conf\build_rule.txt del %WORKSPACE%\Conf\build_rule.txt
+if exist %WORKSPACE%\Conf\FrameworkDatabase.db del %WORKSPACE%\Conf\FrameworkDatabase.db
+if exist %WORKSPACE%\Conf\target.txt del %WORKSPACE%\Conf\target.txt
+if exist %WORKSPACE%\Conf\tools_def.txt del %WORKSPACE%\Conf\tools_def.txt
+@REM *.c.c is generated by Catalog Debug feature across code tree.
+@REM
+del /s *.c.c > nul 2>&1
+
+cd %WORKSPACE_PLATFORM%\%PROJECT%
+
+del /f /q Prep.log > nul 2>&1
+del /f /q ..\Build.log > nul 2>&1
+
+echo.
+echo All done...
+echo.
+@echo on

+ 45 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/postbuild.bat

@@ -0,0 +1,45 @@
+@REM @file
+@REM
+@REM Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution.  The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+@REM #
+@REM #  Module Name:
+@REM #
+@REM #    postbuild.bat
+@REM #
+@REM #  Abstract:
+@REM #
+@REM #    Post build script.
+@REM #
+@REM #--*/
+
+@set SCRIPT_ERROR=0
+
+@if /I not "%0" == "%WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat" (
+  if /I not "%0" == "%WORKSPACE_PLATFORM%\%PROJECT%\postbuild" (
+    echo.
+    echo !!! ERROR !!! This postbuild.bat must run under workspace root using "%WORKSPACE_PLATFORM%\%PROJECT%\postbuild.bat" !!!
+    echo.
+    set SCRIPT_ERROR=1
+    goto :EOF
+  )
+)
+
+@cd %WORKSPACE_PLATFORM%
+
+@cd %WORKSPACE%
+
+@if %FSP_WRAPPER_BUILD% EQU TRUE (
+  del /f %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased*.fd
+)
+
+@if %FSP_WRAPPER_BUILD% EQU TRUE exit /b
+

+ 221 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prebuild.bat

@@ -0,0 +1,221 @@
+@REM @file
+@REM  Pre build script.
+@REM
+@REM Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution.  The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+cd ..
+
+
+@REM
+@REM Set build capsule flag with default being OFF
+@REM
+
+@set CAPSULE_BUILD=0
+
+@if /I "%2" == "TRUE" (
+  @set CAPSULE_BUILD=1
+  goto StartCapsulePrep
+)
+
+:StartCapsulePrep
+@REM
+@REM Define platform specific environment variables.
+@REM
+if not defined WORKSPACE_PLATFORM set WORKSPACE_PLATFORM=%WORKSPACE%\edk2-platforms\Platform\Intel
+if not defined WORKSPACE_SILICON set WORKSPACE_SILICON=%WORKSPACE%\edk2-platforms\Silicon\Intel
+if not defined WORKSPACE_PLATFORM_BIN set WORKSPACE_PLATFORM_BIN=%WORKSPACE%\edk2-non-osi\Platform\Intel
+if not defined WORKSPACE_SILICON_BIN set WORKSPACE_SILICON_BIN=%WORKSPACE%\edk2-non-osi\Silicon\Intel
+if not defined WORKSPACE_FSP_BIN set WORKSPACE_FSP_BIN=%WORKSPACE%\FSP
+if not defined WORKSPACE_CORE set WORKSPACE_CORE=%WORKSPACE%\edk2
+if not defined PLATFORM_PACKAGE set PLATFORM_PACKAGE=MinPlatformPkg
+if not defined PLATFORM_BOARD_PACKAGE set PLATFORM_BOARD_PACKAGE=KabylakeOpenBoardPkg
+if not defined BOARD set BOARD=KabylakeRvp3
+if not defined PROJECT set PROJECT=%PLATFORM_BOARD_PACKAGE%\%BOARD%
+
+@set SCRIPT_ERROR=0
+
+@set CATALOG_DEBUG=0
+
+@REM Set basic environment.
+@echo.
+@echo Prebuild:  Run edksetup.bat batch file.
+@echo.
+@if %CATALOG_DEBUG% == 0 (
+  @del Conf\build_rule.txt
+)
+cd %WORKSPACE_CORE%
+@call edksetup.bat
+cd %WORKSPACE%
+@set EFI_SOURCE=%WORKSPACE_CORE%
+
+@REM
+@REM Setup Visual Studio environment. Order of precedence is 2012, 2013, 2010 and then 2008.
+@REM
+@REM NOTE: To override precedence set TOOL_CHAIN_TAG before calling prep.bat.
+@REM       Example: set TOOL_CHAIN_TAG=VS2008
+@REM
+
+@REM Check if tool chain has not been selected and Visual Studio 2014 is installed.
+@if not defined TOOL_CHAIN_TAG (
+  if defined VS140COMNTOOLS (
+    set TOOL_CHAIN_TAG=VS2015
+  )
+)
+
+@REM If Visual Studio 2014 is selected by priority or by preference, setup the environment variables.
+@if /I "%TOOL_CHAIN_TAG%"=="VS2015" (
+  echo.
+  echo Prebuild:  Set the VS2015 environment.
+  echo.
+  if not defined VSINSTALLDIR call "%VS140COMNTOOLS%\vsvars32.bat"
+  if /I "%VS140COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 14.0\Common7\Tools\" (
+    set TOOL_CHAIN_TAG=VS2015
+  ) else (
+    set TOOL_CHAIN_TAG=VS2015x86
+  )
+)
+
+@REM Check if tool chain has not been selected and Visual Studio 2013 is installed.
+@if not defined TOOL_CHAIN_TAG (
+  if defined VS120COMNTOOLS (
+    set TOOL_CHAIN_TAG=VS2013
+  )
+)
+
+@REM If Visual Studio 2013 is selected by priority or by preference, setup the environment variables.
+@if /I "%TOOL_CHAIN_TAG%"=="VS2013" (
+  echo.
+  echo Prebuild:  Set the VS2013 environment.
+  echo.
+  if not defined VSINSTALLDIR call "%VS120COMNTOOLS%\vsvars32.bat"
+  if /I "%VS120COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 12.0\Common7\Tools\" (
+    set TOOL_CHAIN_TAG=VS2013
+  ) else (
+    set TOOL_CHAIN_TAG=VS2013x86
+  )
+)
+
+@REM If no supported version of Visual Studio was detected, return an error.
+@if not defined TOOL_CHAIN_TAG (
+  echo.
+  echo !!! ERROR !!! Visual Studio not installed correctly!!!
+  echo.
+  set SCRIPT_ERROR=1
+  goto :EndPreBuild
+)
+
+echo Show CL revision
+cl
+
+@REM Set build TARGET.
+@if /I "%1" == "" (
+  set TARGET=DEBUG
+  set TARGET_SHORT=D
+) else if /I "%1" == "DEBUG" (
+  set TARGET=DEBUG
+  set TARGET_SHORT=D
+) else if /I "%1" == "TEST_RELEASE" (
+  set TARGET=RELEASE
+  set TARGET_SHORT=R
+) else if /I "%1" == "RELEASE" (
+  set TARGET=RELEASE
+  set TARGET_SHORT=R
+) else if /I "%1" == "RELEASE_PDB" (
+  set TARGET=RELEASE
+  set TARGET_SHORT=R
+) else (
+  echo.
+  echo !!! ERROR !!! Incorrect TARGET option for prebuild.bat. !!!
+  echo.
+  set SCRIPT_ERROR=1
+  goto :EndPreBuild
+)
+
+@set BUILD_DIR_PATH=%WORKSPACE%\Build\%PROJECT%\%TARGET%_%TOOL_CHAIN_TAG%
+@set BUILD_DIR=Build\%PROJECT%\%TARGET%_%TOOL_CHAIN_TAG%
+@set BUILD_X64=%BUILD_DIR_PATH%\X64
+@set BUILD_IA32=%BUILD_DIR_PATH%\IA32
+
+
+@echo.
+@echo Prebuild:  Set build environment.
+@echo.
+@if not exist %BUILD_DIR_PATH% (
+  mkdir %BUILD_DIR_PATH%
+)
+
+@findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG BUILD_RULE_CONF" %WORKSPACE%\Conf\target.txt > %BUILD_DIR_PATH%\target.txt
+@echo ACTIVE_PLATFORM = %WORKSPACE_PLATFORM%/%PLATFORM_BOARD_PACKAGE%/%BOARD%/OpenBoardPkg.dsc        >> %BUILD_DIR_PATH%\target.txt
+@echo TARGET          = %TARGET%                                  >> %BUILD_DIR_PATH%\target.txt
+@echo TARGET_ARCH     = IA32 X64                                  >> %BUILD_DIR_PATH%\target.txt
+@echo TOOL_CHAIN_TAG  = %TOOL_CHAIN_TAG%                          >> %BUILD_DIR_PATH%\target.txt
+@echo BUILD_RULE_CONF = Conf/build_rule.txt                       >> %BUILD_DIR_PATH%\target.txt
+@move /Y %BUILD_DIR_PATH%\target.txt Conf
+
+@if %CAPSULE_BUILD% == 1 (
+  goto EndCapsulePrep
+)
+
+@REM
+@REM Set %FSP_WRAPPER_BUILD%
+@REM
+@set FSP_WRAPPER_BUILD=TRUE
+
+@if %FSP_WRAPPER_BUILD% EQU TRUE (
+  @REM Create dummy Fsp_Rebased_S_padded.fd to build the BiosInfo.inf if it is wrapper build, due to the SECTION inclusion
+  echo "" > %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S_padded.fd
+  attrib -r %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased_S_padded.fd
+)
+
+@REM
+@REM Set %PERFORMANCE_BUILD%
+@REM
+@set PERFORMANCE_BUILD=FALSE
+
+@REM
+@REM Set %FSP_BINARY_BUILD% and %FSP_TEST_RELEASE%
+@REM
+@set FSP_BINARY_BUILD=FALSE
+@set FSP_TEST_RELEASE=FALSE
+
+@if "FSP_BINARY_BUILD"=="TRUE" (
+  @if %FSP_WRAPPER_BUILD% EQU FALSE goto :EndPreBuild
+)
+
+@if not exist %BUILD_X64% (
+  mkdir %BUILD_X64%
+)
+
+@set SECURE_BOOT_ENABLE=FALSE
+
+@REM
+@REM Skip BIOS_SIZE_OPTION if it is predefined
+@REM
+@if NOT "%BIOS_SIZE_OPTION%" == "" goto BiosSizeDone
+
+@set BIOS_SIZE_OPTION=
+
+@REM default size option is 7M
+@set BIOS_SIZE_OPTION=-DBIOS_SIZE_OPTION=SIZE_70
+
+:BiosSizeDone
+@echo BIOS_SIZE_OPTION=%BIOS_SIZE_OPTION%
+
+@echo   EFI_SOURCE           = %EFI_SOURCE%
+@echo   TARGET               = %TARGET%
+@echo   TARGET_ARCH          = IA32 X64
+@echo   TOOL_CHAIN_TAG       = %TOOL_CHAIN_TAG%
+@echo   WORKSPACE            = %WORKSPACE%
+@echo   WORKSPACE_CORE       = %WORKSPACE_CORE%
+@echo   EXT_BUILD_FLAGS      = %EXT_BUILD_FLAGS%
+@echo.
+:EndPreBuild
+cd %WORKSPACE_PLATFORM%\%PROJECT%

+ 85 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/prep.bat

@@ -0,0 +1,85 @@
+@REM @file
+@REM
+@REM Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+@REM This program and the accompanying materials
+@REM are licensed and made available under the terms and conditions of the BSD License
+@REM which accompanies this distribution.  The full text of the license may be found at
+@REM http://opensource.org/licenses/bsd-license.php
+@REM
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+@REM
+
+@echo OFF
+@set PrepRELEASE=DEBUG
+@set SILENT_MODE=FALSE
+@set CapsuleBuild=FALSE
+
+@set EXT_CONFIG_CLEAR=
+@set EXT_BUILD_FLAGS=
+
+:CmdLineParse
+if "" == "%1" (
+  goto Continue
+) else if "r" == "%1" (
+  set PrepRELEASE=RELEASE
+) else if "tr" == "%1" (
+  set PrepRELEASE=TEST_RELEASE
+) else if "rp" == "%1" (
+  set PrepRELEASE=RELEASE_PDB
+) else if "s" == "%1" (
+  set SILENT_MODE=TRUE
+) else if "help" == "%1" (
+  goto PrepHelp
+) else (
+  echo Invalid input arguments: %1
+  echo.
+  goto PrepHelp
+)
+SHIFT
+goto CmdLineParse
+
+:PrepHelp
+@echo Preparation for BIOS build.
+@echo.
+@echo prep [r][rp][s][help]
+@echo.
+@echo   r         To do release build. Default is debug build. See note 1
+@echo   rp        To do release build with Symbols - For source level debugging. See note 1
+@echo   s         To build in silent mode. . See note 1
+@echo.
+@echo 1) Re-running prep without these arguments cannot be used for
+@echo    incremental build. Hence, these inputs must be supplied each time
+@echo    prep are desired to be re-run.
+@echo.
+goto PrepDone
+
+:Continue
+@echo ==============================================
+
+if exist %WORKSPACE%\Prep.log del %WORKSPACE%\Prep.log
+
+:PrepReleaseCheck
+
+@if %SILENT_MODE% EQU TRUE goto BldSilent
+
+call prebuild.bat %PrepRelease% %CapsuleBuild%
+goto PrePrepDone
+
+:BldSilent
+@echo ************************************************************************ >> %WORKSPACE%\Prep.log
+@echo ***********           Prebuild.bat is launched here          *********** >> %WORKSPACE%\Prep.log
+@echo ************************************************************************ >> %WORKSPACE%\Prep.log
+call prebuild.bat %PrepRelease% %CapsuleBuild% 1>>%WORKSPACE%\Prep.log 2>&1
+
+:PrePrepDone
+@If %SCRIPT_ERROR% EQU 1 goto PrepFail
+@goto PrepDone
+
+:PrepFail
+@echo.
+@echo !! The EDKII BIOS build has failed in prep!
+@echo.
+@exit /b 1
+
+:PrepDone

+ 315 - 0
Platform/Intel/KabylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c

@@ -0,0 +1,315 @@
+/** @file
+  Support for IO expander TCA6424.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/GpioExpanderLib.h>
+#include <Library/I2cAccessLib.h>
+
+//
+// Addresses of registers inside expander
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mInputRegister[3]    = {0x0,0x1,0x2};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mOutputRegister[3]   = {0x4,0x5,0x6};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mConfigRegister[3]   = {0xC,0xD,0xE};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mPolarityRegister[3] = {0x8,0x9,0xA};
+
+#define PCH_SERIAL_IO_I2C4                 4
+#define TCA6424_I2C_ADDRESS 0x22
+#define PINS_PER_REGISTER                  8
+#define GPIO_EXP_PIN_DIRECTION_OUT         1
+#define GPIO_EXP_PIN_DIRECTION_IN          0
+#define GPIO_EXP_PIN_POLARITY_NORMAL       0
+#define GPIO_EXP_PIN_POLARITY_INVERTED     1
+#define GPIO_EXP_SET_OUTPUT                0
+#define GPIO_EXP_SET_DIR                   1
+#define GPIO_EXP_GET_INPUT                 2
+#define GPIO_EXP_SET_POLARITY              3
+#define AUTO_INCREMENT 0x80
+
+/**
+  Returns the Controller on which GPIO expander is present.
+
+  This function returns the Controller value
+
+  @param[out] Controller              Pointer to a Controller value on
+                                      which I2C expander is configured.
+
+  @retval     EFI_SUCCESS              non.
+**/
+EFI_STATUS
+GpioExpGetController (
+  OUT UINT8 *Controller
+  )
+{
+  *Controller = PCH_SERIAL_IO_I2C4;
+  return EFI_SUCCESS;
+}
+
+/**
+  Returns the data from register value giving in the input.
+
+  This function is to get the data from the Expander
+  Registers by following the I2C Protocol communication
+
+
+  @param[in]  Bar0       Bar address of the SerialIo Controller
+  @param[in]  Address    Expander Value with in the Contoller
+  @param[in]  Register   Address of Input/Output/Configure/Polarity
+                         registers with in the Expander
+
+  @retval     UINT8      Value returned from the register
+**/
+UINT8
+GpioExpGetRegister (
+  IN UINTN Bar0,
+  IN UINT8 Address,
+  IN UINT8 Register
+  )
+{
+  EFI_STATUS Status;
+  UINT8 WriBuf[1];
+  UINT8 ReBuf[1] = {0};
+
+  WriBuf[0] = Register;
+  Status = I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 1, WriBuf, 1, ReBuf, WAIT_1_SECOND);
+
+  return ReBuf[0];
+}
+/**
+  Set the input register to a give value mentioned in the function.
+
+  This function is to Programm the data value to the Expander
+  Register by following the I2C Protocol communication.
+
+  @param[in]  Bar0       Bar address of the SerialIo Controller
+  @param[in]  Address    Expander Value with in the Contoller
+  @param[in]  Register   Address of Input/Output/Configure/Polarity
+                         registers with in the Expander
+  @param[in]  Value      Value to set in the mentioned the register
+**/
+VOID
+GpioExpSetRegister (
+  IN UINTN Bar0,
+  IN UINT8 Address,
+  IN UINT8 Register,
+  IN UINT8 Value
+  )
+{
+  EFI_STATUS Status;
+  UINT8 WriBuf[2];
+
+  WriBuf[0] = Register;
+  WriBuf[1] = Value;
+  Status = I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 2, WriBuf, 0, NULL, WAIT_1_SECOND);
+
+}
+/**
+  Set the input register to a give value mentioned in the function.
+
+  This function is to update the status of the Gpio Expander
+  pin based on the input Operation value of the caller.This
+  function calculates the exact address of the register with
+  the help of the Register Bank
+
+  @param[in]  Controller  SerialIo Controller value
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+  @param[in]  Operation   Type of operation (Setoutput/Setdirection
+                          /Getinput/Setpolarity)
+  @retval     UINT8       Final Value returned from the register
+**/
+UINT8
+GpioExpDecodeRegAccess (
+  IN UINT8 Controller,
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value,
+  IN UINT8 Operation
+  )
+{
+  UINT8* RegisterBank;
+  UINT8 OldValue;
+  UINT8 NewValue;
+  UINT8 RegisterAddress;
+  UINT8 PinNumber;
+  UINT8 ReturnValue = 0;
+
+  DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n", Controller, Expander, Pin, Value, Operation));
+  ASSERT(Controller<6);
+  ASSERT(Expander<2);
+  ASSERT(Pin<24);
+  ASSERT(Value<2);
+  ASSERT(Operation<4);
+  //
+  // Find the register Address value based on the OPeration
+  //
+  switch(Operation) {
+    case GPIO_EXP_SET_OUTPUT:
+      RegisterBank = mOutputRegister;
+      break;
+    case GPIO_EXP_SET_DIR:
+      RegisterBank = mConfigRegister;
+      break;
+    case GPIO_EXP_GET_INPUT:
+      RegisterBank = mInputRegister;
+      break;
+    case GPIO_EXP_SET_POLARITY:
+      RegisterBank = mPolarityRegister;
+      break;
+    default:
+      ASSERT(FALSE);
+      return 0;
+    }
+  //
+  // Each bit of register represents each Pin
+  // calaulate the register address and Pinnumber(offset with in register)
+  //
+  if (Pin >= 24) {
+    //
+    // Avoid out-of-bound usage of RegisterBank
+    //
+    return 0;
+  }
+
+  RegisterAddress = RegisterBank[(Pin/PINS_PER_REGISTER)];
+  PinNumber = Pin%PINS_PER_REGISTER;
+
+  OldValue = GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expander, RegisterAddress);
+  //
+  // If it to get the data ,just returned otherwise mark the input value and write the register
+  //
+  if (Operation == GPIO_EXP_GET_INPUT) {
+    ReturnValue = 0x1 & (OldValue>>PinNumber);
+  } else {
+    NewValue = OldValue;
+    NewValue &= ~(BIT0<<PinNumber);
+    NewValue |= (Value<<PinNumber);
+    if(NewValue!=OldValue) {
+      GpioExpSetRegister(FindSerialIoBar(Controller, 0), Expander, RegisterAddress, NewValue);
+    }
+  }
+  return ReturnValue;
+}
+/**
+  Set the Output value for the given Expander Gpio pin.
+
+  This function is to Set the Output value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetOutput (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value
+  )
+{
+  UINT8 Controller;
+  if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+    GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_OUTPUT);
+  }
+}
+/**
+  Set the Direction value for the given Expander Gpio pin.
+
+  This function is to Set the direction value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+**/
+VOID
+GpioExpSetDirection (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value
+  )
+{
+
+  UINT8 Controller;
+  if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+    GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_DIR);
+  }
+}
+
+
+/**
+  Get the input value for the given Expander Gpio pin.
+
+  This function is to get the input value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+
+  @retval     UINT8       Final Value returned from the register
+**/
+UINT8
+GpioExpGetInput (
+  IN UINT8 Expander,
+  IN UINT8 Pin
+  )
+{
+  UINT8 Controller;
+  if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+    return GpioExpDecodeRegAccess(Controller,Expander,Pin,0,GPIO_EXP_GET_INPUT);
+  }
+  return 0;
+}
+
+/**
+  Configures all registers of a single IO Expander in one go.
+
+  @param[in]  Expander    Expander number (0/1)
+  @param[in]  Direction   Bit-encoded direction values. BIT0 is for pin0, etc. 0=output, 1=input
+  @param[in]  Polarity    Bit-encoded input inversion values. BIT0 is for pin0, etc. 0=normal, 1=inversion
+  @param[in]  Output      Bit-encoded output state, ignores polarity, only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
+
+**/
+VOID
+GpioExpBulkConfig (
+  IN UINT8  Expander,
+  IN UINT32 Direction,
+  IN UINT32 Polarity,
+  IN UINT32 Output
+  )
+{
+  UINT8 WriteBuf[4];
+  UINT8 Controller;
+
+  GpioExpGetController(&Controller);
+
+  WriteBuf[0] = mOutputRegister[0] + AUTO_INCREMENT;
+  WriteBuf[1] = Output & 0xFF;
+  WriteBuf[2] = (Output>>8) & 0xFF;
+  WriteBuf[3] = (Output>>16) & 0xFF;
+  I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+  WriteBuf[0] = mPolarityRegister[0] + AUTO_INCREMENT;
+  WriteBuf[1] = Polarity & 0xFF;
+  WriteBuf[2] = (Polarity>>8) & 0xFF;
+  WriteBuf[3] = (Polarity>>16) & 0xFF;
+  I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+  WriteBuf[0] = mConfigRegister[0] + AUTO_INCREMENT;
+  WriteBuf[1] = Direction & 0xFF;
+  WriteBuf[2] = (Direction>>8) & 0xFF;
+  WriteBuf[3] = (Direction>>16) & 0xFF;
+  I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+
+}
+

+ 39 - 0
Platform/Intel/KabylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf

@@ -0,0 +1,39 @@
+### @file
+# Library producing Gpio Expander functionality.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = BaseGpioExpanderLib
+  FILE_GUID                      = D10AE2A4-782E-427E-92FB-BB74505ED329
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = GpioExpanderLib
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  DebugLib
+  TimerLib
+  PchSerialIoLib
+  I2cAccessLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  BaseGpioExpanderLib.c

+ 121 - 0
Platform/Intel/KabylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.c

@@ -0,0 +1,121 @@
+/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/I2cAccessLib.h>
+
+EFI_STATUS
+I2cWriteRead (
+  IN UINTN  MmioBase,
+  IN UINT8  SlaveAddress,
+  IN UINT8  WriteLength,
+  IN UINT8  *WriteBuffer,
+  IN UINT8  ReadLength,
+  IN UINT8  *ReadBuffer,
+  IN UINT64  TimeBudget
+  //TODO: add Speed parameter
+  )
+{
+  UINT8 ReadsNeeded = ReadLength;
+  UINT64 CutOffTime;
+
+  if ((WriteLength == 0 && ReadLength == 0) ||
+      (WriteLength != 0 && WriteBuffer == NULL) ||
+      (ReadLength != 0 && ReadBuffer == NULL) ) {
+    DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Sanity checks to verify the I2C controller is alive
+  // Conveniently, ICON register's values of 0 or FFFFFFFF indicate
+  // I2c controller is out-of-order: either disabled, in D3 or in reset.
+  //
+  if (MmioRead32(MmioBase+R_IC_CON) == 0xFFFFFFFF || MmioRead32(MmioBase+R_IC_CON) == 0x0) {
+    DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  MmioWrite32(MmioBase+R_IC_ENABLE, 0x0);
+  MmioRead32(MmioBase+0x40);
+  MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
+  MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C);
+  //
+  // Set I2C Bus Speed at 400 kHz for GPIO Expander
+  //
+  MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128);
+  MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160);
+  MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress);
+  MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE | V_IC_SPEED_FAST | B_IC_RESTART_EN | B_IC_SLAVE_DISABLE );
+  MmioWrite32(MmioBase+R_IC_ENABLE, 0x1);
+  CutOffTime = AsmReadTsc() + TimeBudget;
+
+  while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==0 ) {
+    if (AsmReadTsc() > CutOffTime) {
+      DEBUG ((DEBUG_ERROR, "I2cWR timeout\n"));
+      return EFI_TIMEOUT;
+    }
+  }
+
+  while(1) {
+    if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) {
+      DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason = 0x%08x\n",MmioRead32(MmioBase+R_IC_TX_ABRT_SOURCE)));
+      MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
+      MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+      while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
+      return EFI_DEVICE_ERROR;
+    }
+    if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) {
+      if (WriteLength > 1) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
+        WriteBuffer++;
+        WriteLength--;
+      } else if (WriteLength==1 && ReadLength != 0) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
+        WriteBuffer++;
+        WriteLength--;
+      } else if (WriteLength==1 && ReadLength == 0) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer | B_IC_CMD_STOP);
+        WriteBuffer++;
+        WriteLength--;
+      } else if (ReadLength > 1) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ);
+        ReadLength--;
+      } else if (ReadLength == 1) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ|B_IC_CMD_STOP);
+        ReadLength--;
+      }
+    }
+
+    if (ReadsNeeded) {
+      if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) {
+        *ReadBuffer = (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD);
+        ReadBuffer++;
+        ReadsNeeded--;
+      }
+    }
+    if (WriteLength==0 && ReadsNeeded==0 && !(MmioRead32(MmioBase+R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) {
+      MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+      while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
+      DEBUG ((DEBUG_INFO, "I2cWR success\n"));
+      return EFI_SUCCESS;
+    }
+    if (AsmReadTsc() > CutOffTime) {
+      MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+      while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
+      DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n"));
+      return EFI_TIMEOUT;
+    }
+
+  }
+}
+

+ 42 - 0
Platform/Intel/KabylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf

@@ -0,0 +1,42 @@
+### @file
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiI2cAccessLib
+  FILE_GUID                      = 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = PeiI2cAccessLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  TimerLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  SecurityPkg/SecurityPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiI2cAccessLib.c

+ 25 - 0
Platform/Intel/KabylakeOpenBoardPkg/License.txt

@@ -0,0 +1,25 @@
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in
+  the documentation and/or other materials provided with the
+  distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.

+ 262 - 0
Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec

@@ -0,0 +1,262 @@
+## @file
+# Module describe the entire platform configuration.
+#
+# The DEC files are used by the utilities that parse DSC and
+# INF files to generate AutoGen.c and AutoGen.h files
+# for the build infrastructure.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = OpenBoardPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E
+
+[Includes]
+Include
+KabylakeRvp3\Include
+
+[Guids]
+
+gBoardModuleTokenSpaceGuid            =  {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
+
+[Protocols]
+
+[Ppis]
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+
+[PcdsFixedAtBuild]
+
+gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004
+gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005
+
+gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018
+gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F
+
+gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000001C
+gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D
+
+gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000021
+gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x90000022
+
+
+
+
+gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015
+
+[PcdsDynamic]
+
+# Board GPIO Table
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114
+
+# Board Expander GPIO Table
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046
+gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047
+
+# TouchPanel & SDHC CD GPIO Table
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048
+
+# PCH-LP HSIO PTSS Table
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x0000004C
+gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x0000004D
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x00000050
+gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x00000051
+
+# PCH-H HSIO PTSS Table
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054
+gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000058
+gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000059
+
+# HDA Verb Table
+gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A
+gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B
+gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C
+gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D
+gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E
+gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F
+gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060
+
+# SA Misc Configuration
+gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067
+gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101
+
+# DRAM Configuration
+gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068
+gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069
+gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A
+gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B
+gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C
+gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D
+gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x0000006E
+gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F
+gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070
+gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071
+
+# PEG RESET GPIO
+gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072
+gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073
+gBoardModuleTokenSpaceGuid.PcdPegResetGpioPad|0|UINT32|0x00000074
+gBoardModuleTokenSpaceGuid.PcdPegResetGpioActive|FALSE|BOOLEAN|0x00000075
+gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079
+gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A
+gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B
+gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C
+gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D
+gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E
+gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F
+
+# SPD Address Table
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B
+gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C
+
+# CA Vref Configuration
+gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D
+
+# Root Port Clock Info
+gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo|0|UINT64|0x0000009E
+gBoardModuleTokenSpaceGuid.PcdRootPort1ClkInfo|0|UINT64|0x0000009F
+gBoardModuleTokenSpaceGuid.PcdRootPort2ClkInfo|0|UINT64|0x000000A0
+gBoardModuleTokenSpaceGuid.PcdRootPort3ClkInfo|0|UINT64|0x000000A1
+gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo|0|UINT64|0x000000A2
+gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo|0|UINT64|0x000000A3
+gBoardModuleTokenSpaceGuid.PcdRootPort6ClkInfo|0|UINT64|0x000000A4
+gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo|0|UINT64|0x000000A5
+gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo|0|UINT64|0x000000A6
+gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo|0|UINT64|0x000000A7
+gBoardModuleTokenSpaceGuid.PcdRootPort10ClkInfo|0|UINT64|0x000000A8
+gBoardModuleTokenSpaceGuid.PcdRootPort11ClkInfo|0|UINT64|0x000000A9
+gBoardModuleTokenSpaceGuid.PcdRootPort12ClkInfo|0|UINT64|0x000000AA
+gBoardModuleTokenSpaceGuid.PcdRootPort13ClkInfo|0|UINT64|0x000000AB
+gBoardModuleTokenSpaceGuid.PcdRootPort14ClkInfo|0|UINT64|0x000000AC
+gBoardModuleTokenSpaceGuid.PcdRootPort15ClkInfo|0|UINT64|0x000000AD
+gBoardModuleTokenSpaceGuid.PcdRootPort16ClkInfo|0|UINT64|0x000000AE
+gBoardModuleTokenSpaceGuid.PcdRootPort17ClkInfo|0|UINT64|0x000000AF
+gBoardModuleTokenSpaceGuid.PcdRootPort18ClkInfo|0|UINT64|0x000000B0
+gBoardModuleTokenSpaceGuid.PcdRootPort19ClkInfo|0|UINT64|0x000000B1
+gBoardModuleTokenSpaceGuid.PcdRootPort20ClkInfo|0|UINT64|0x000000B2
+gBoardModuleTokenSpaceGuid.PcdRootPort21ClkInfo|0|UINT64|0x000000B3
+gBoardModuleTokenSpaceGuid.PcdRootPort22ClkInfo|0|UINT64|0x000000B4
+gBoardModuleTokenSpaceGuid.PcdRootPort23ClkInfo|0|UINT64|0x000000B5
+gBoardModuleTokenSpaceGuid.PcdRootPort24ClkInfo|0|UINT64|0x000000B6
+gBoardModuleTokenSpaceGuid.PcdRootPort25ClkInfo|0|UINT64|0x000000B7
+gBoardModuleTokenSpaceGuid.PcdRootPort26ClkInfo|0|UINT64|0x000000B8
+gBoardModuleTokenSpaceGuid.PcdRootPort27ClkInfo|0|UINT64|0x000000B9
+gBoardModuleTokenSpaceGuid.PcdRootPort28ClkInfo|0|UINT64|0x000000BA
+gBoardModuleTokenSpaceGuid.PcdRootPort29ClkInfo|0|UINT64|0x000000BB
+gBoardModuleTokenSpaceGuid.PcdRootPort30ClkInfo|0|UINT64|0x000000BC
+gBoardModuleTokenSpaceGuid.PcdRootPort31ClkInfo|0|UINT64|0x000000BD
+gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo|0|UINT64|0x000000BE
+
+# USB 2.0 Port AFE
+gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF
+gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0
+gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1
+gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2
+gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3
+gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4
+gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5
+gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6
+gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7
+gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8
+gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9
+gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA
+gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB
+gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC
+gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD
+gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE
+
+# USB 2.0 Port Over Current Pin
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD
+gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE
+
+# USB 3.0 Port Over Current Pin
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7
+gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8
+
+# UCMC GPIO Table
+gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111
+gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112
+
+# Misc
+gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC
+
+gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000009
+
+
+  gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002
+  gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003
+  gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A
+  gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B
+  gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C
+  # 0: Type-C
+  # 1: Stacked-Jack
+  gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012
+
+  gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013
+
+[PcdsDynamicEx]
+
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+  gBoardModuleTokenSpaceGuid.PcdIntelGopEnable      |TRUE|BOOLEAN|0xF0000062
+
+  gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport   |TRUE|BOOLEAN|0xF0000000

+ 71 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/DxeSaPolicyUpdate.c

@@ -0,0 +1,71 @@
+/** @file
+  This file is the library for SA DXE Policy initialization.
+  
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SaPolicyInitDxe.h"
+
+#define SA_VTD_RMRR_USB_LENGTH  0x20000
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS                  mAddress;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN                                 mSize;
+
+/**
+  Update RMRR Base and Limit Address for USB.
+
+**/
+VOID
+UpdateRmrrUsbAddress (
+  IN OUT  SA_POLICY_PROTOCOL    *SaPolicy
+  )
+{
+  EFI_STATUS              Status;
+  MISC_DXE_CONFIG         *MiscDxeConfig;
+
+  Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  if (1) {
+    mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);
+    mAddress = SIZE_4GB;
+
+    Status = (gBS->AllocatePages) (
+                     AllocateMaxAddress,
+                     EfiReservedMemoryType,
+                     mSize,
+                     &mAddress
+                    );
+    ASSERT_EFI_ERROR (Status);
+
+    MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress;
+    MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1;
+  }
+}
+
+/**
+  Get data for platform policy from setup options.
+
+  @param[in] SaPolicy                  The pointer to get SA Policy protocol instance
+
+  @retval EFI_SUCCESS                  Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+  IN OUT  SA_POLICY_PROTOCOL    *SaPolicy
+  )
+{
+  UpdateRmrrUsbAddress (SaPolicy);
+  return EFI_SUCCESS;
+}
+

+ 181 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c

@@ -0,0 +1,181 @@
+/** @file
+  This file initialises and Installs GopPolicy Protocol.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "GopPolicyInitDxe.h"
+#include <Protocol/GopPolicy.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL        mGOPPolicy;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32                     mVbtSize = 0;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS       mVbtAddress = 0;
+
+//
+// Function implementations
+//
+
+/**
+
+  @param[out] CurrentLidStatus
+
+  @retval     EFI_SUCCESS
+  @retval     EFI_UNSUPPORTED
+**/
+EFI_STATUS
+EFIAPI
+GetPlatformLidStatus (
+  OUT LID_STATUS *CurrentLidStatus
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+/**
+
+  @param[out] CurrentDockStatus
+
+  @retval     EFI_SUCCESS
+  @retval     EFI_UNSUPPORTED
+**/
+EFI_STATUS
+EFIAPI
+GetPlatformDockStatus (
+  OUT DOCK_STATUS  CurrentDockStatus
+  )
+{
+    return EFI_UNSUPPORTED;
+}
+
+
+/**
+
+  @param[out] VbtAddress
+  @param[out] VbtSize
+
+  @retval     EFI_SUCCESS
+  @retval     EFI_NOT_FOUND
+**/
+EFI_STATUS
+EFIAPI
+GetVbtData (
+  OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+  OUT UINT32               *VbtSize
+  )
+{
+  EFI_STATUS                    Status;
+  UINTN                         FvProtocolCount;
+  EFI_HANDLE                    *FvHandles;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+  UINTN                         Index;
+  UINT32                        AuthenticationStatus;
+  UINT8                         *Buffer;
+  UINTN                         VbtBufferSize;
+
+
+  Status = EFI_NOT_FOUND;
+  if ( mVbtAddress == 0) {
+    Fv           = NULL;
+
+    Buffer = 0;
+    FvHandles       = NULL;
+    Status = gBS->LocateHandleBuffer (
+                    ByProtocol,
+                    &gEfiFirmwareVolume2ProtocolGuid,
+                    NULL,
+                    &FvProtocolCount,
+                    &FvHandles
+                    );
+    if (!EFI_ERROR (Status)) {
+      for (Index = 0; Index < FvProtocolCount; Index++) {
+        Status = gBS->HandleProtocol (
+                        FvHandles[Index],
+                        &gEfiFirmwareVolume2ProtocolGuid,
+                        (VOID **) &Fv
+                        );
+        VbtBufferSize = 0;
+        Status = Fv->ReadSection (
+                       Fv,
+                       &gIntelPeiGraphicsVbtGuid,
+                       EFI_SECTION_RAW,
+                       0,
+                       (VOID **) &Buffer,
+                       &VbtBufferSize,
+                       &AuthenticationStatus
+                       );
+        if (!EFI_ERROR (Status)) {
+          *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer;
+          *VbtSize = (UINT32)VbtBufferSize;
+          mVbtAddress = *VbtAddress;
+          mVbtSize = *VbtSize;
+          Status = EFI_SUCCESS;
+          break;
+        }
+      }
+    } else {
+      Status = EFI_NOT_FOUND;
+    }
+
+    if (FvHandles != NULL) {
+      FreePool (FvHandles);
+      FvHandles = NULL;
+    }
+  } else {
+    *VbtAddress = mVbtAddress;
+    *VbtSize = mVbtSize;
+    Status = EFI_SUCCESS;
+  }
+
+  return Status;
+}
+
+
+
+/**
+Initialize GOP DXE Policy
+
+@param[in] ImageHandle          Image handle of this driver.
+
+@retval EFI_SUCCESS             Initialization complete.
+@retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.
+@retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.
+@retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.
+**/
+
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe (
+  IN EFI_HANDLE       ImageHandle
+  )
+{
+  EFI_STATUS         Status;
+
+  //
+  // Initialize the EFI Driver Library
+  //
+  SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
+
+  mGOPPolicy.Revision                = GOP_POLICY_PROTOCOL_REVISION_03;
+  mGOPPolicy.GetPlatformLidStatus    = GetPlatformLidStatus;
+  mGOPPolicy.GetVbtData              = GetVbtData;
+  mGOPPolicy.GetPlatformDockStatus   = GetPlatformDockStatus;
+
+  //
+  // Install protocol to allow access to this Policy.
+  //
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gGopPolicyProtocolGuid,
+                  &mGOPPolicy,
+                  NULL
+                  );
+
+  return Status;
+}

+ 45 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h

@@ -0,0 +1,45 @@
+/** @file
+Header file for the GopPolicyInitDxe Driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _GOP_POLICY_INIT_DXE_H_
+#define _GOP_POLICY_INIT_DXE_H_
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+
+/**
+Initialize GOP DXE Policy
+
+@param[in] ImageHandle          Image handle of this driver.
+
+@retval EFI_SUCCESS             Initialization complete.
+@retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.
+@retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.
+@retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe(
+  IN EFI_HANDLE           ImageHandle
+  );
+
+#endif

+ 62 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c

@@ -0,0 +1,62 @@
+/** @file
+  This file is a wrapper for Platform Policy driver. Get Setup
+  Value to initialize Intel DXE Platform Policy.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PolicyInitDxe.h"
+
+#include <KabylakeRvp3Id.h>
+
+/**
+  Initialize  DXE Platform Policy
+
+  @param[in] ImageHandle       Image handle of this driver.
+  @param[in] SystemTable       Global system service table.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED       The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+PolicyInitDxeEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS           Status;
+  
+  if (LibPcdGetSku () != BoardIdKabyLakeYLpddr3Rvp3) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // SystemAgent Dxe Platform Policy Initialization
+  //
+  Status = SaPolicyInitDxe (ImageHandle);
+  DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization done\n"));
+  ASSERT_EFI_ERROR (Status);
+
+  if (PcdGetBool(PcdIntelGopEnable)) {
+    //
+    // GOP Dxe Policy Initialization
+    //
+    Status = GopPolicyInitDxe(ImageHandle);
+    DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
+    ASSERT_EFI_ERROR(Status);
+  }
+
+  return Status;
+
+}

+ 46 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h

@@ -0,0 +1,46 @@
+/** @file
+  Header file for the PolicyInitDxe Driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _POLICY_INIT_DXE_H_
+#define _POLICY_INIT_DXE_H_
+
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+#include "SaPolicyInitDxe.h"
+#include "GopPolicyInitDxe.h"
+
+/**
+  Initialize DXE Platform Policy
+
+  @param[in] ImageHandle - Image handle of this driver.
+  @param[in] SystemTable - Global system service table.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED       The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+
+EFI_STATUS
+EFIAPI
+PolicyInitDxeEntryPoint (
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+;
+
+#endif

+ 72 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf

@@ -0,0 +1,72 @@
+### @file
+# Module Information file for the PolicyInit DXE driver.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = KabylakeRvp3PolicyInitDxe
+  FILE_GUID                      = 490D0119-4448-440D-8F5C-F58FB53EE057
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = DXE_DRIVER
+  ENTRY_POINT                    = PolicyInitDxeEntryPoint
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  CpuPlatformLib
+  DebugLib
+  DxeServicesTableLib
+  IoLib
+  MemoryAllocationLib
+  DxeSaPolicyLib
+  MmPciLib
+  PcdLib
+  PostCodeLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+  UefiRuntimeServicesTableLib
+  ConfigBlockLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
+
+[Sources]
+  PolicyInitDxe.c
+  PolicyInitDxe.h
+  SaPolicyInitDxe.c
+  SaPolicyInitDxe.h
+  GopPolicyInitDxe.c
+  GopPolicyInitDxe.h
+  DxeSaPolicyUpdate.c
+
+[Protocols]
+  gEfiFirmwareVolume2ProtocolGuid               ## CONSUMES
+  gSaPolicyProtocolGuid                         ## CONSUMES
+  gDxeSiPolicyProtocolGuid                      ## PRODUCES
+  gGopPolicyProtocolGuid                        ## PRODUCES
+
+[Guids]
+  gIntelPeiGraphicsVbtGuid                      ## CONSUMES
+  gMiscDxeConfigGuid
+
+[Depex]
+  gEfiVariableArchProtocolGuid
+

+ 73 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c

@@ -0,0 +1,73 @@
+/** @file
+  This file is SampleCode for SA DXE Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "SaPolicyInitDxe.h"
+
+//
+// Function implementations
+//
+
+/**
+  Get data for platform policy from setup options.
+
+  @param[in] SaPolicy                  The pointer to get SA Policy protocol instance
+
+  @retval EFI_SUCCESS                  Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+  IN OUT  SA_POLICY_PROTOCOL    *SaPolicy
+  );
+
+
+/**
+  Initialize SA DXE Policy
+
+  @param[in] ImageHandle          Image handle of this driver.
+
+  @retval EFI_SUCCESS             Initialization complete.
+  @exception EFI_UNSUPPORTED      The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+  IN EFI_HANDLE                   ImageHandle
+  )
+{
+  EFI_STATUS               Status;
+  SA_POLICY_PROTOCOL       *SaPolicy;
+
+  //
+  // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
+  // and get all Intel default policy settings.
+  //
+  Status = CreateSaDxeConfigBlocks(&SaPolicy);
+  DEBUG((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+  ASSERT_EFI_ERROR(Status);
+
+    UpdateDxeSaPolicy (SaPolicy);
+
+  //
+  // Install SaInstallPolicyProtocol.
+  // While installed, RC assumes the Policy is ready and finalized. So please
+  // update and override any setting before calling this function.
+  //
+  Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}

+ 56 - 0
Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h

@@ -0,0 +1,56 @@
+/** @file
+  Header file for the SaPolicyInitDxe Driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_POLICY_INIT_DXE_H_
+#define _SA_POLICY_INIT_DXE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/SaPolicy.h>
+#include <Library/DxeSaPolicyLib.h>
+
+#include <SaAccess.h>
+
+
+/**
+  <b>SA DXE Policy Driver Entry Point</b> \n
+  - <b>Introduction</b> \n
+    System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
+    Platform policy Protocol is initialized with default settings in this funciton.
+    This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
+
+  - @pre
+    - Runtime variable service should be ready if policy initialization required.
+
+  - @result
+    SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use.
+
+  - <b>Porting Recommendations</b> \n
+    Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
+
+  @param[in] ImageHandle - Image handle of this driver.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED    The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+  IN EFI_HANDLE           ImageHandle
+  );
+
+#endif