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Platform/ARM: Bump Dsdt/Ssdt ACPI table revision

From ACPI 5.1, s19.5.28 DefinitionBlock (Declare Definition Block):
  Note: For compatibility with ACPI versions before
  ACPI 2.0, the bit width of Integer objects is
  dependent on the ComplianceRevision of the DSDT.
  If the ComplianceRevision is less than 2, all
  integers are restricted to 32 bits. Otherwise,
  full 64-bit integers are used. The version of the DSDT
  sets the global integer width for all integers,
  including integers in SSDTs.

To be up-to-date with the latest table revision, bump the version
of all dsdt/ssdt tables that are relying on an ACPI specification
version above 2.0.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Pierre Gondois 1 年之前
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d13436b384

+ 1 - 1
Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl

@@ -57,7 +57,7 @@
                                                     // Device 0 for Bridge.
 
 
-DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
+DefinitionBlock("SsdtPci.aml", "SSDT", 2, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
   Scope(_SB) {
     //
     // PCI Root Complex

+ 1 - 1
Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl

@@ -8,7 +8,7 @@
 
 #include "ArmPlatform.h"
 
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
   Scope(_SB) {
     //
     // A57x2-A53x4 Processor declaration

+ 1 - 1
Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl

@@ -8,7 +8,7 @@
 
 #include "ArmPlatform.h"
 
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
   Scope(_SB) {
     //
     // A57x2-A53x4 Processor declaration

+ 1 - 1
Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtJunoUsb.asl

@@ -8,7 +8,7 @@
 
 #include "ArmPlatform.h"
 
-DefinitionBlock("SsdtJunoUSB.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
+DefinitionBlock("SsdtJunoUSB.aml", "SSDT", 2, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
   Scope(_SB) {
     //
     // USB EHCI Host Controller

+ 1 - 1
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl

@@ -8,7 +8,7 @@
 
 #include "ConfigurationManager.h"
 
-DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) {
+DefinitionBlock("Dsdt.aml", "DSDT", 2, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) {
   Scope(_SB) {
     Device(CP00) { // Cluster 0, Cpu 0
       Name(_HID, "ACPI0007")

+ 1 - 1
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl

@@ -30,7 +30,7 @@
 
 #define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, Link)  // Device 0 for Bridge.
 
-DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO",
+DefinitionBlock("SsdtPci.aml", "SSDT", 2, "ARMLTD", "MORELLO",
                 CFG_MGR_OEM_REVISION)
 {
   Scope (_SB) {

+ 1 - 1
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl

@@ -59,7 +59,7 @@
 #define CS_OUTPUT_PORT(_port, _rport, _rphandle)      \
     CS_PORT(_port, _rport, _rphandle, CS_LINK_MASTER)
 
-DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_OEM_REVISION) {
+DefinitionBlock("Dsdt.aml", "DSDT", 2, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_OEM_REVISION) {
   Scope(_SB) {
     Device(CP00) { // Ares-0: Cluster 0, Cpu 0
       Name(_HID, "ACPI0007")

+ 1 - 1
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl

@@ -61,7 +61,7 @@
 */
 #define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, Link)  // Device 0 for Bridge.
 
-DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
+DefinitionBlock("SsdtPci.aml", "SSDT", 2, "ARMLTD", "N1Sdp",
                 EFI_ACPI_ARM_OEM_REVISION)
 {
   Scope (_SB) {

+ 1 - 1
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl

@@ -61,7 +61,7 @@
 */
 #define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, Link)  // Device 0 for Bridge.
 
-DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
+DefinitionBlock("SsdtRemotePci.aml", "SSDT", 2, "ARMLTD", "N1Sdp",
                 EFI_ACPI_ARM_OEM_REVISION)
 {
   Scope (_SB) {

+ 1 - 1
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl

@@ -9,7 +9,7 @@
 
 **/
 
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-VEXP", 1) {
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARM-VEXP", 1) {
   Scope(_SB) {
     //
     // Processor