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+## @file
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+# Component description file for the CN9130 Development Board (variant A)
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+#
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+# Copyright (c) 2019 Marvell International Ltd.<BR>
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+#
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+# SPDX-License-Identifier: BSD-2-Clause-Patent
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+#
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+##
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+
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+################################################################################
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+#
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+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
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+#
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+################################################################################
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+[PcdsFixedAtBuild.common]
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+ # CP115 count
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+ gMarvellTokenSpaceGuid.PcdMaxCpCount|1
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+
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+ # MPP
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+ gMarvellTokenSpaceGuid.PcdMppChipCount|2
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+
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+ # APN807 MPP
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+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
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+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
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+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
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+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
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+
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+ # CP115 #0 MPP
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+ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
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+ gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
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+ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
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+ gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
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+ gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 }
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+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
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+ gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
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+
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+ # I2C
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+ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
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+ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
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+ gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
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+ gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
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+
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+ # SPI
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+ gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
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+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
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+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
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+
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+ gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
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+ gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
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+
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+ # ComPhy
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+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
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+ # ComPhy0
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+ # 0: PCIE0 5 Gbps
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+ # 1: PCIE0 5 Gbps
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+ # 2: PCIE0 5 Gbps
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+ # 3: PCIE0 5 Gbps
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+ # 4: SFI 10.31 Gbps
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+ # 5: SATA1 5 Gbps
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+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
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+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
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+
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+ # UtmiPhy
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+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
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+
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+ # MDIO
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+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
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+
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+ # PHY
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+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
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+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
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+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
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+
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+ # NET
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+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
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+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
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+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
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+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) }
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+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
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+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
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+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
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+
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+ # NonDiscoverableDevices
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+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
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+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
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+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
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+
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+ # PCIE
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+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000
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+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000
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+
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+ # RTC
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+ gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
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+
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+ # SoC Configuration Space
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+ gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000
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+
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+ # Variable store
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+ gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE
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