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@@ -28,24 +28,24 @@
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interrupt type as PCI defaults (Level Triggered, Active Low) are not
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compatible with GICv2.
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*/
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-#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
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- Device(Link_Name) { \
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- Name(_HID, EISAID("PNP0C0F")) \
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- Name(_UID, Unique_Id) \
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- Name(_PRS, ResourceTemplate() { \
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- Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
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- }) \
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- Method (_CRS, 0) { Return (_PRS) } \
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- Method (_SRS, 1) { } \
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- Method (_DIS) { } \
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- }
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-
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-#define PRT_ENTRY(Address, Pin, Link) \
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+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
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+ Device(Link_Name) { \
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+ Name(_HID, EISAID("PNP0C0F")) \
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+ Name(_UID, Unique_Id) \
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+ Name(_PRS, ResourceTemplate() { \
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+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
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+ }) \
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+ Method (_CRS, 0) { Return (_PRS) } \
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+ Method (_SRS, 1) { } \
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+ Method (_DIS) { } \
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+ }
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+
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+#define PRT_ENTRY(Address, Pin, Link) \
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Package (4) { \
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Address, /* uses the same format as _ADR */ \
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Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
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- Link, /* Interrupt allocated via Link device. */ \
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- Zero /* global system interrupt number (no used) */ \
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+ Link, /* Interrupt allocated via Link device. */ \
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+ Zero /* global system interrupt number (no used) */ \
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}
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/*
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@@ -59,155 +59,155 @@
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DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
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Scope(_SB) {
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- //
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- // PCI Root Complex
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- //
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- LNK_DEVICE(1, LNKA, 168)
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- LNK_DEVICE(2, LNKB, 169)
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- LNK_DEVICE(3, LNKC, 170)
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- LNK_DEVICE(4, LNKD, 171)
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-
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- Device(PCI0)
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+ //
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+ // PCI Root Complex
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+ //
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+ LNK_DEVICE(1, LNKA, 168)
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+ LNK_DEVICE(2, LNKB, 169)
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+ LNK_DEVICE(3, LNKC, 170)
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+ LNK_DEVICE(4, LNKD, 171)
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+
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+ Device(PCI0)
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{
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- Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
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- Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
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- Name(_SEG, Zero) // PCI Segment Group number
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- Name(_BBN, Zero) // PCI Base Bus Number
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- Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1)
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-
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- // Root Complex 0
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- Device (RP0) {
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- Name(_ADR, 0xF0000000) // Dev 0, Func 0
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- }
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+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
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+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
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+ Name(_SEG, Zero) // PCI Segment Group number
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+ Name(_BBN, Zero) // PCI Base Bus Number
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+ Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1)
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+
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+ // Root Complex 0
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+ Device (RP0) {
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+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
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+ }
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+
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+ // PCI Routing Table
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+ Name(_PRT, Package() {
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+ ROOT_PRT_ENTRY(0, LNKA), // INTA
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+ ROOT_PRT_ENTRY(1, LNKB), // INTB
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+ ROOT_PRT_ENTRY(2, LNKC), // INTC
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+ ROOT_PRT_ENTRY(3, LNKD), // INTD
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+ })
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+ // Root complex resources
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+ Method (_CRS, 0, Serialized) {
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+ Name (RBUF, ResourceTemplate () {
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+ WordBusNumber ( // Bus numbers assigned to this root
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+ ResourceProducer,
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+ MinFixed, MaxFixed, PosDecode,
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+ 0, // AddressGranularity
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+ 0, // AddressMinimum - Minimum Bus Number
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+ 255, // AddressMaximum - Maximum Bus Number
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+ 0, // AddressTranslation - Set to 0
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+ 256 // RangeLength - Number of Busses
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+ )
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+
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+ DWordMemory ( // 32-bit BAR Windows
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+ ResourceProducer, PosDecode,
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+ MinFixed, MaxFixed,
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+ Cacheable, ReadWrite,
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+ 0x00000000, // Granularity
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+ 0x50000000, // Min Base Address
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+ 0x57FFFFFF, // Max Base Address
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+ 0x00000000, // Translate
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+ 0x08000000 // Length
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+ )
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+
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+ QWordMemory ( // 64-bit BAR Windows
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+ ResourceProducer, PosDecode,
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+ MinFixed, MaxFixed,
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+ Cacheable, ReadWrite,
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+ 0x00000000, // Granularity
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+ 0x4000000000, // Min Base Address
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+ 0x40FFFFFFFF, // Max Base Address
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+ 0x00000000, // Translate
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+ 0x100000000 // Length
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+ )
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+
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+ DWordIo ( // IO window
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+ ResourceProducer,
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+ MinFixed,
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+ MaxFixed,
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+ PosDecode,
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+ EntireRange,
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+ 0x00000000, // Granularity
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+ 0x00000000, // Min Base Address
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+ 0x007fffff, // Max Base Address
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+ 0x5f800000, // Translate
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+ 0x00800000, // Length
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+ ,,,TypeTranslation
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+ )
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+ }) // Name(RBUF)
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+
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+ Return (RBUF)
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+ } // Method(_CRS)
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+
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+ //
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+ // OS Control Handoff
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+ //
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+ Name(SUPP, Zero) // PCI _OSC Support Field value
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+ Name(CTRL, Zero) // PCI _OSC Control Field value
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+
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+ /*
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+ See [1] 6.2.10, [2] 4.5
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+ */
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+ Method(_OSC,4) {
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+ // Check for proper UUID
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+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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+ // Create DWord-adressable fields from the Capabilities Buffer
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+ CreateDWordField(Arg3,0,CDW1)
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+ CreateDWordField(Arg3,4,CDW2)
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+ CreateDWordField(Arg3,8,CDW3)
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+
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+ // Save Capabilities DWord2 & 3
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+ Store(CDW2,SUPP)
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+ Store(CDW3,CTRL)
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+
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+ // Only allow native hot plug control if OS supports:
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+ // * ASPM
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+ // * Clock PM
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+ // * MSI/MSI-X
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+ If(LNotEqual(And(SUPP, 0x16), 0x16)) {
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+ And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
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+ }
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+
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+ // Always allow native PME, AER (no dependencies)
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- // PCI Routing Table
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- Name(_PRT, Package() {
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- ROOT_PRT_ENTRY(0, LNKA), // INTA
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- ROOT_PRT_ENTRY(1, LNKB), // INTB
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- ROOT_PRT_ENTRY(2, LNKC), // INTC
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- ROOT_PRT_ENTRY(3, LNKD), // INTD
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- })
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- // Root complex resources
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- Method (_CRS, 0, Serialized) {
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- Name (RBUF, ResourceTemplate () {
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- WordBusNumber ( // Bus numbers assigned to this root
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- ResourceProducer,
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- MinFixed, MaxFixed, PosDecode,
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- 0, // AddressGranularity
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- 0, // AddressMinimum - Minimum Bus Number
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- 255, // AddressMaximum - Maximum Bus Number
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- 0, // AddressTranslation - Set to 0
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- 256 // RangeLength - Number of Busses
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- )
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-
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- DWordMemory ( // 32-bit BAR Windows
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- ResourceProducer, PosDecode,
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- MinFixed, MaxFixed,
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- Cacheable, ReadWrite,
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- 0x00000000, // Granularity
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- 0x50000000, // Min Base Address
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- 0x57FFFFFF, // Max Base Address
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- 0x00000000, // Translate
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- 0x08000000 // Length
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- )
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-
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- QWordMemory ( // 64-bit BAR Windows
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- ResourceProducer, PosDecode,
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- MinFixed, MaxFixed,
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- Cacheable, ReadWrite,
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- 0x00000000, // Granularity
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- 0x4000000000, // Min Base Address
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- 0x40FFFFFFFF, // Max Base Address
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- 0x00000000, // Translate
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- 0x100000000 // Length
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- )
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-
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- DWordIo ( // IO window
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- ResourceProducer,
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- MinFixed,
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- MaxFixed,
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- PosDecode,
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- EntireRange,
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- 0x00000000, // Granularity
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- 0x00000000, // Min Base Address
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- 0x007fffff, // Max Base Address
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- 0x5f800000, // Translate
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- 0x00800000, // Length
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- ,,,TypeTranslation
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- )
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- }) // Name(RBUF)
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-
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- Return (RBUF)
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- } // Method(_CRS)
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-
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- //
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- // OS Control Handoff
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- //
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- Name(SUPP, Zero) // PCI _OSC Support Field value
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- Name(CTRL, Zero) // PCI _OSC Control Field value
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-
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- /*
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- See [1] 6.2.10, [2] 4.5
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- */
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- Method(_OSC,4) {
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- // Check for proper UUID
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- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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- // Create DWord-adressable fields from the Capabilities Buffer
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- CreateDWordField(Arg3,0,CDW1)
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- CreateDWordField(Arg3,4,CDW2)
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- CreateDWordField(Arg3,8,CDW3)
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-
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- // Save Capabilities DWord2 & 3
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- Store(CDW2,SUPP)
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- Store(CDW3,CTRL)
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-
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- // Only allow native hot plug control if OS supports:
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- // * ASPM
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- // * Clock PM
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- // * MSI/MSI-X
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- If(LNotEqual(And(SUPP, 0x16), 0x16)) {
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- And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
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- }
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-
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- // Always allow native PME, AER (no dependencies)
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-
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- // Never allow SHPC (no SHPC controller in this system)
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- And(CTRL,0x1D,CTRL)
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+ // Never allow SHPC (no SHPC controller in this system)
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+ And(CTRL,0x1D,CTRL)
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#if 0
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- If(LNot(And(CDW1,1))) { // Query flag clear?
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- // Disable GPEs for features granted native control.
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- If(And(CTRL,0x01)) { // Hot plug control granted?
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- Store(0,HPCE) // clear the hot plug SCI enable bit
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- Store(1,HPCS) // clear the hot plug SCI status bit
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- }
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- If(And(CTRL,0x04)) { // PME control granted?
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- Store(0,PMCE) // clear the PME SCI enable bit
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- Store(1,PMCS) // clear the PME SCI status bit
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- }
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- If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?
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- // Set status to not restore PCIe cap structure
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- // upon resume from S3
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- Store(1,S3CR)
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- }
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- }
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+ If(LNot(And(CDW1,1))) { // Query flag clear?
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+ // Disable GPEs for features granted native control.
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+ If(And(CTRL,0x01)) { // Hot plug control granted?
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+ Store(0,HPCE) // clear the hot plug SCI enable bit
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+ Store(1,HPCS) // clear the hot plug SCI status bit
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+ }
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+ If(And(CTRL,0x04)) { // PME control granted?
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+ Store(0,PMCE) // clear the PME SCI enable bit
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+ Store(1,PMCS) // clear the PME SCI status bit
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+ }
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+ If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?
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+ // Set status to not restore PCIe cap structure
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+ // upon resume from S3
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+ Store(1,S3CR)
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+ }
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+ }
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#endif
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- If(LNotEqual(Arg1,One)) { // Unknown revision
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- Or(CDW1,0x08,CDW1)
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- }
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-
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- If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
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- Or(CDW1,0x10,CDW1)
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- }
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- // Update DWORD3 in the buffer
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- Store(CTRL,CDW3)
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- Return(Arg3)
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- } Else {
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- Or(CDW1,4,CDW1) // Unrecognized UUID
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- Return(Arg3)
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- }
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- } // End _OSC
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+ If(LNotEqual(Arg1,One)) { // Unknown revision
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+ Or(CDW1,0x08,CDW1)
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+ }
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+
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+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
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+ Or(CDW1,0x10,CDW1)
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+ }
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+ // Update DWORD3 in the buffer
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+ Store(CTRL,CDW3)
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+ Return(Arg3)
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+ } Else {
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+ Or(CDW1,4,CDW1) // Unrecognized UUID
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+ Return(Arg3)
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+ }
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+ } // End _OSC
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} // PCI0
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}
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}
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